From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Lorenzo Pieralisi To: linux-pci@vger.kernel.org Subject: [PATCH v3 04/32] asm-generic: add ioremap_nopost() remap interface Date: Tue, 11 Apr 2017 13:28:44 +0100 Message-Id: <20170411122923.6285-5-lorenzo.pieralisi@arm.com> In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonas Bonn , Rich Felker , Catalin Marinas , Will Deacon , "James E.J. Bottomley" , David Howells , Max Filippov , Paul Mackerras , Huacai Chen , Guan Xuetao , Thomas Gleixner , Hans-Christian Egtvedt , linux-arch@vger.kernel.org, Jesper Nilsson , Lorenzo Pieralisi , Yoshinori Sato , Michael Ellerman , Helge Deller , Russell King , Ingo Molnar , Geert Uytterhoeven , Benjamin Herrenschmidt , Matt Turner , Haavard Skinnemoen , Fenghua Yu , James Hogan , Chris Metcalf , Arnd Bergmann , Heiko Carstens , Stefan Kristiansson , Mikael Starvik , Ivan Kokshaysky , Bjorn Helgaas , Stafford Horne , linux-arm-kernel@lists.infradead.org, Richard Henderson , Chris Zankel , Michal Simek , Tony Luck , Vineet Gupta , linux-kernel@vger.kernel.org, Ralf Baechle , Richard Kuo , Niklas Cassel , "Luis R . Rodriguez" , Martin Schwidefsky , Ley Foon Tan , "David S. Miller" MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Current DT and ACPI host bridge controllers map PCI configuration space (ECAM and ECAM-derivative) into the virtual address space through ioremap() calls, that are non-cacheable device accesses on most architectures, but may provide "bufferable" or "posted" write semantics in architecture like eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus connecting the host CPU to the PCI fabric; this behaviour, as underlined in the PCIe specifications, may trigger transactions ordering rules and must be prevented. Introduce a new generic and explicit API to create a memory mapping for ECAM and ECAM-derivative config space area (and a corresponding generic asm-generic header file) that defaults to ioremap_nocache() (which should provide a sane default behaviour) and can be included by all architectures that do not require an arch specific memory mapping for ioremap_nopost() to guarantee non-posted writes behaviour. Signed-off-by: Lorenzo Pieralisi Cc: Arnd Bergmann Cc: Bjorn Helgaas Cc: Russell King Cc: Luis R. Rodriguez --- include/asm-generic/ioremap-nopost.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 include/asm-generic/ioremap-nopost.h diff --git a/include/asm-generic/ioremap-nopost.h b/include/asm-generic/ioremap-nopost.h new file mode 100644 index 0000000..015911f --- /dev/null +++ b/include/asm-generic/ioremap-nopost.h @@ -0,0 +1,9 @@ +#ifndef __ASM_GENERIC_IOREMAP_NOPOST_H +#define __ASM_GENERIC_IOREMAP_NOPOST_H + +static inline void __iomem *ioremap_nopost(phys_addr_t offset, size_t size) +{ + return ioremap_nocache(offset, size); +} + +#endif /* __ASM_GENERIC_IOREMAP_NOPOST_H */ -- 2.10.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lorenzo Pieralisi Subject: [PATCH v3 04/32] asm-generic: add ioremap_nopost() remap interface Date: Tue, 11 Apr 2017 13:28:44 +0100 Message-ID: <20170411122923.6285-5-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: linux-pci@vger.kernel.org Cc: Jonas Bonn , Rich Felker , Catalin Marinas , Will Deacon , "James E.J. Bottomley" , David Howells , Max Filippov , Paul Mackerras , Huacai Chen , Guan Xuetao , Thomas Gleixner , Hans-Christian Egtvedt , linux-arch@vger.kernel.org, Jesper Nilsson , Lorenzo Pieralisi , Yoshinori Sato , Michael Ellerman , Helge Deller , Russell King , Ingo Molnar , Geert Uytterhoeven , Benjamin Herrenschmidt , Matt Turner , Haa List-Id: linux-arch.vger.kernel.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Current DT and ACPI host bridge controllers map PCI configuration space (ECAM and ECAM-derivative) into the virtual address space through ioremap() calls, that are non-cacheable device accesses on most architectures, but may provide "bufferable" or "posted" write semantics in architecture like eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus connecting the host CPU to the PCI fabric; this behaviour, as underlined in the PCIe specifications, may trigger transactions ordering rules and must be prevented. Introduce a new generic and explicit API to create a memory mapping for ECAM and ECAM-derivative config space area (and a corresponding generic asm-generic header file) that defaults to ioremap_nocache() (which should provide a sane default behaviour) and can be included by all architectures that do not require an arch specific memory mapping for ioremap_nopost() to guarantee non-posted writes behaviour. Signed-off-by: Lorenzo Pieralisi Cc: Arnd Bergmann Cc: Bjorn Helgaas Cc: Russell King Cc: Luis R. Rodriguez --- include/asm-generic/ioremap-nopost.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 include/asm-generic/ioremap-nopost.h diff --git a/include/asm-generic/ioremap-nopost.h b/include/asm-generic/ioremap-nopost.h new file mode 100644 index 0000000..015911f --- /dev/null +++ b/include/asm-generic/ioremap-nopost.h @@ -0,0 +1,9 @@ +#ifndef __ASM_GENERIC_IOREMAP_NOPOST_H +#define __ASM_GENERIC_IOREMAP_NOPOST_H + +static inline void __iomem *ioremap_nopost(phys_addr_t offset, size_t size) +{ + return ioremap_nocache(offset, size); +} + +#endif /* __ASM_GENERIC_IOREMAP_NOPOST_H */ -- 2.10.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: lorenzo.pieralisi@arm.com (Lorenzo Pieralisi) Date: Tue, 11 Apr 2017 13:28:44 +0100 Subject: [PATCH v3 04/32] asm-generic: add ioremap_nopost() remap interface In-Reply-To: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> References: <20170411122923.6285-1-lorenzo.pieralisi@arm.com> Message-ID: <20170411122923.6285-5-lorenzo.pieralisi@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The PCI specifications (Rev 3.0, 3.2.5 "Transaction Ordering and Posting") mandate non-posted configuration transactions. As further highlighted in the PCIe specifications (4.0 - Rev0.3, "Ordering Considerations for the Enhanced Configuration Access Mechanism"), through ECAM and ECAM-derivative configuration mechanism, the memory mapped transactions from the host CPU into Configuration Requests on the PCI express fabric may create ordering problems for software because writes to memory address are typically posted transactions (unless the architecture can enforce through virtual address mapping non-posted write transactions behaviour) but writes to Configuration Space are not posted on the PCI express fabric. Current DT and ACPI host bridge controllers map PCI configuration space (ECAM and ECAM-derivative) into the virtual address space through ioremap() calls, that are non-cacheable device accesses on most architectures, but may provide "bufferable" or "posted" write semantics in architecture like eg ARM/ARM64 that allow ioremap'ed regions writes to be buffered in the bus connecting the host CPU to the PCI fabric; this behaviour, as underlined in the PCIe specifications, may trigger transactions ordering rules and must be prevented. Introduce a new generic and explicit API to create a memory mapping for ECAM and ECAM-derivative config space area (and a corresponding generic asm-generic header file) that defaults to ioremap_nocache() (which should provide a sane default behaviour) and can be included by all architectures that do not require an arch specific memory mapping for ioremap_nopost() to guarantee non-posted writes behaviour. Signed-off-by: Lorenzo Pieralisi Cc: Arnd Bergmann Cc: Bjorn Helgaas Cc: Russell King Cc: Luis R. Rodriguez --- include/asm-generic/ioremap-nopost.h | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 include/asm-generic/ioremap-nopost.h diff --git a/include/asm-generic/ioremap-nopost.h b/include/asm-generic/ioremap-nopost.h new file mode 100644 index 0000000..015911f --- /dev/null +++ b/include/asm-generic/ioremap-nopost.h @@ -0,0 +1,9 @@ +#ifndef __ASM_GENERIC_IOREMAP_NOPOST_H +#define __ASM_GENERIC_IOREMAP_NOPOST_H + +static inline void __iomem *ioremap_nopost(phys_addr_t offset, size_t size) +{ + return ioremap_nocache(offset, size); +} + +#endif /* __ASM_GENERIC_IOREMAP_NOPOST_H */ -- 2.10.0