From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753360AbdDKTiU (ORCPT ); Tue, 11 Apr 2017 15:38:20 -0400 Received: from mga09.intel.com ([134.134.136.24]:43583 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752580AbdDKTiS (ORCPT ); Tue, 11 Apr 2017 15:38:18 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,186,1488873600"; d="scan'208";a="86212335" Date: Tue, 11 Apr 2017 12:38:10 -0700 From: "Luebbers, Enno" To: Jerome Glisse Cc: Wu Hao , atull@kernel.org, moritz.fischer@ettus.com, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org, luwei.kang@intel.com, yi.z.zhang@intel.com Subject: Re: [PATCH 00/16] Intel FPGA Device Drivers Message-ID: <20170411193806.GA33858@eluebber-mac02.jf.intel.com> References: <1490875696-15145-1-git-send-email-hao.wu@intel.com> <20170406202700.GA3674@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170406202700.GA3674@redhat.com> User-Agent: Mutt/1.8.0 (2017-02-23) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jerome, On Thu, Apr 06, 2017 at 04:27:00PM -0400, Jerome Glisse wrote: > Do we have an open source toolchain to generate the FPGA configuration > (bitstream) ? As it is required for the GPU sub-system that any driver > API must comes with open source userspace. As far as I know, no FPGA vendor currently provides an open-source version of their FPGA synthesis tools - there are, however, free (as in beer) versions available for download that can be used for generating FPGA bitstreams. Also, there are a number of projects to replace parts of the vendor tools with open alternatives (yosys comes to mind, which I believe recently added initial support for synthesizing logic for Intel FPGAs). As an aside, we are also working on an open-source user-space library that would allow you to use this driver to load existing accelerator bitstreams as well as enumerate and access accelerators present in the system. This would enable workflows where users have access to e.g. a library of FPGA accelerator bitstreams and want to write applications that take advantage of these accelerators, even without having access to an FPGA synthesis tool. Thanks - Enno