From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755913AbdDMTo4 (ORCPT ); Thu, 13 Apr 2017 15:44:56 -0400 Received: from mail-oi0-f67.google.com ([209.85.218.67]:35845 "EHLO mail-oi0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755510AbdDMTox (ORCPT ); Thu, 13 Apr 2017 15:44:53 -0400 Date: Thu, 13 Apr 2017 14:44:51 -0500 From: Rob Herring To: Anurup M Cc: mark.rutland@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com, tanxiaojun@huawei.com, xuwei5@hisilicon.com, sanil.kumar@hisilicon.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, shiju.jose@huawei.com, huangdaode@hisilicon.com, wangkefeng.wang@huawei.com, linuxarm@huawei.com, dikshit.n@huawei.com, shyju.pv@huawei.com Subject: Re: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU Message-ID: <20170413194451.jhi7c62iar5dqvyy@rob-hp-laptop> References: <1491303333-140338-1-git-send-email-anurup.m@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m@huawei.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote: > 1) Device tree bindings for Hisilicon SoC PMU. > 2) Add example for Hisilicon L3 cache and MN PMU. > 3) Add child nodes of L3C and MN in djtag bindings example. > > Signed-off-by: Anurup M > Signed-off-by: Shaokun Zhang > --- > .../devicetree/bindings/arm/hisilicon/djtag.txt | 29 +++++++ > .../devicetree/bindings/arm/hisilicon/pmu.txt | 93 ++++++++++++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt Acked-by: Rob Herring From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Herring Subject: Re: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU Date: Thu, 13 Apr 2017 14:44:51 -0500 Message-ID: <20170413194451.jhi7c62iar5dqvyy@rob-hp-laptop> References: <1491303333-140338-1-git-send-email-anurup.m@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Anurup M Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, will.deacon-5wv7dgnIgG8@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, anurup.m-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, zhangshaokun-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, tanxiaojun-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, sanil.kumar-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, gabriele.paoloni-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, shiju.jose-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, huangdaode-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, wangkefeng.wang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, dikshit.n-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, shyju.pv-hv44wF8Li93QT0dZR+AlfA@public.gmane.org List-Id: devicetree@vger.kernel.org On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote: > 1) Device tree bindings for Hisilicon SoC PMU. > 2) Add example for Hisilicon L3 cache and MN PMU. > 3) Add child nodes of L3C and MN in djtag bindings example. > > Signed-off-by: Anurup M > Signed-off-by: Shaokun Zhang > --- > .../devicetree/bindings/arm/hisilicon/djtag.txt | 29 +++++++ > .../devicetree/bindings/arm/hisilicon/pmu.txt | 93 ++++++++++++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt Acked-by: Rob Herring -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: robh@kernel.org (Rob Herring) Date: Thu, 13 Apr 2017 14:44:51 -0500 Subject: [PATCH v7 3/9] dt-bindings: perf: hisi: Add Devicetree bindings for Hisilicon SoC PMU In-Reply-To: <1491303333-140338-1-git-send-email-anurup.m@huawei.com> References: <1491303333-140338-1-git-send-email-anurup.m@huawei.com> Message-ID: <20170413194451.jhi7c62iar5dqvyy@rob-hp-laptop> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Apr 04, 2017 at 06:55:33AM -0400, Anurup M wrote: > 1) Device tree bindings for Hisilicon SoC PMU. > 2) Add example for Hisilicon L3 cache and MN PMU. > 3) Add child nodes of L3C and MN in djtag bindings example. > > Signed-off-by: Anurup M > Signed-off-by: Shaokun Zhang > --- > .../devicetree/bindings/arm/hisilicon/djtag.txt | 29 +++++++ > .../devicetree/bindings/arm/hisilicon/pmu.txt | 93 ++++++++++++++++++++++ > 2 files changed, 122 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/pmu.txt Acked-by: Rob Herring