From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753160AbdDND33 (ORCPT ); Thu, 13 Apr 2017 23:29:29 -0400 Received: from mail.kernel.org ([198.145.29.136]:33104 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751544AbdDND31 (ORCPT ); Thu, 13 Apr 2017 23:29:27 -0400 Date: Fri, 14 Apr 2017 11:28:54 +0800 From: Shawn Guo To: Andrey Smirnov Cc: yurovsky@gmail.com, Sascha Hauer , Fabio Estevam , Rob Herring , Mark Rutland , Russell King , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d' Message-ID: <20170414032853.GF14915@dragon> References: <20170413133242.5068-1-andrew.smirnov@gmail.com> <20170413133242.5068-4-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170413133242.5068-4-andrew.smirnov@gmail.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote: > In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and > it serves the function of granting permission to GPC IP block to alter > various bit-fields of the register. The reason why this property, that > trickeld here from Freescale BSP, is set to 31 is because in the code > it came from it is used in conjunction with a notifier handler for > REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE > events (not found in upstream kernel) that triggers GPC to start > manipulating aforementioned other bitfields. > > Since: > a) none of the aforementioned machinery is implemented by > upstream > b) using 'anatop-enable-bit' in that capacity is a bit of a > semantic stretch > > simplify the situation by setting the value of 'anatop-enable-bit' to > point to ENABLE_LINREG (same as i.MX6). > > Cc: yurovsky@gmail.com > Cc: Sascha Hauer > Cc: Fabio Estevam > Cc: Rob Herring > Cc: Mark Rutland > Cc: Russell King > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Signed-off-by: Andrey Smirnov Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash them into one patch? Shawn > --- > arch/arm/boot/dts/imx7s.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index 22c9788..8fee299 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -516,7 +516,7 @@ > anatop-min-bit-val = <8>; > anatop-min-voltage = <800000>; > anatop-max-voltage = <1200000>; > - anatop-enable-bit = <31>; > + anatop-enable-bit = <0>; > }; > }; > > -- > 2.9.3 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d' Date: Fri, 14 Apr 2017 11:28:54 +0800 Message-ID: <20170414032853.GF14915@dragon> References: <20170413133242.5068-1-andrew.smirnov@gmail.com> <20170413133242.5068-4-andrew.smirnov@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20170413133242.5068-4-andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Andrey Smirnov Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, Sascha Hauer , Fabio Estevam , Rob Herring , Mark Rutland , Russell King , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote: > In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and > it serves the function of granting permission to GPC IP block to alter > various bit-fields of the register. The reason why this property, that > trickeld here from Freescale BSP, is set to 31 is because in the code > it came from it is used in conjunction with a notifier handler for > REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE > events (not found in upstream kernel) that triggers GPC to start > manipulating aforementioned other bitfields. > > Since: > a) none of the aforementioned machinery is implemented by > upstream > b) using 'anatop-enable-bit' in that capacity is a bit of a > semantic stretch > > simplify the situation by setting the value of 'anatop-enable-bit' to > point to ENABLE_LINREG (same as i.MX6). > > Cc: yurovsky-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org > Cc: Sascha Hauer > Cc: Fabio Estevam > Cc: Rob Herring > Cc: Mark Rutland > Cc: Russell King > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org > Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > Signed-off-by: Andrey Smirnov Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash them into one patch? Shawn > --- > arch/arm/boot/dts/imx7s.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index 22c9788..8fee299 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -516,7 +516,7 @@ > anatop-min-bit-val = <8>; > anatop-min-voltage = <800000>; > anatop-max-voltage = <1200000>; > - anatop-enable-bit = <31>; > + anatop-enable-bit = <0>; > }; > }; > > -- > 2.9.3 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawnguo@kernel.org (Shawn Guo) Date: Fri, 14 Apr 2017 11:28:54 +0800 Subject: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d' In-Reply-To: <20170413133242.5068-4-andrew.smirnov@gmail.com> References: <20170413133242.5068-1-andrew.smirnov@gmail.com> <20170413133242.5068-4-andrew.smirnov@gmail.com> Message-ID: <20170414032853.GF14915@dragon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote: > In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and > it serves the function of granting permission to GPC IP block to alter > various bit-fields of the register. The reason why this property, that > trickeld here from Freescale BSP, is set to 31 is because in the code > it came from it is used in conjunction with a notifier handler for > REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE > events (not found in upstream kernel) that triggers GPC to start > manipulating aforementioned other bitfields. > > Since: > a) none of the aforementioned machinery is implemented by > upstream > b) using 'anatop-enable-bit' in that capacity is a bit of a > semantic stretch > > simplify the situation by setting the value of 'anatop-enable-bit' to > point to ENABLE_LINREG (same as i.MX6). > > Cc: yurovsky at gmail.com > Cc: Sascha Hauer > Cc: Fabio Estevam > Cc: Rob Herring > Cc: Mark Rutland > Cc: Russell King > Cc: devicetree at vger.kernel.org > Cc: linux-kernel at vger.kernel.org > Cc: linux-arm-kernel at lists.infradead.org > Signed-off-by: Andrey Smirnov Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash them into one patch? Shawn > --- > arch/arm/boot/dts/imx7s.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index 22c9788..8fee299 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -516,7 +516,7 @@ > anatop-min-bit-val = <8>; > anatop-min-voltage = <800000>; > anatop-max-voltage = <1200000>; > - anatop-enable-bit = <31>; > + anatop-enable-bit = <0>; > }; > }; > > -- > 2.9.3 >