From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S3001220AbdDZOa5 (ORCPT ); Wed, 26 Apr 2017 10:30:57 -0400 Received: from mga01.intel.com ([192.55.52.88]:39726 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S3001205AbdDZOat (ORCPT ); Wed, 26 Apr 2017 10:30:49 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,254,1488873600"; d="scan'208";a="1161230045" Date: Wed, 26 Apr 2017 17:30:40 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Michel =?iso-8859-1?Q?D=E4nzer?= Cc: Daniel Vetter , dri-devel@lists.freedesktop.org, Gerd Hoffmann , amd-gfx@lists.freedesktop.org, open list Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format Message-ID: <20170426143040.GW30290@intel.com> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> <20170425095259.GK30290@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 26, 2017 at 11:00:09AM +0900, Michel Dänzer wrote: > On 25/04/17 06:52 PM, Ville Syrjälä wrote: > > On Tue, Apr 25, 2017 at 12:18:52PM +0900, Michel Dänzer wrote: > >> On 24/04/17 03:25 PM, Gerd Hoffmann wrote: > >>> +#ifdef __BIG_ENDIAN > >>> + switch (bpp) { > >>> + case 8: > >>> + fmt = DRM_FORMAT_C8; > >>> + break; > >>> + case 24: > >>> + fmt = DRM_FORMAT_BGR888; > >>> + break; > >> > >> BTW, endianness as a concept cannot apply to 8 or 24 bpp formats. > > > > To 8bpp no, but it can easily apply to 24bpp. > > Any byte swapping rips apart the bytes of a 24bpp pixel, so those > formats only make sense as straight array formats. In my book little endian just means "lsb is stored in the lowest memory address". The fact that your CPU/GPU can't do 3 byte swaps is not relevant for that definition IMO. -- Ville Syrjälä Intel OTC From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 3/6] drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format Date: Wed, 26 Apr 2017 17:30:40 +0300 Message-ID: <20170426143040.GW30290@intel.com> References: <20170424062532.26722-1-kraxel@redhat.com> <20170424062532.26722-4-kraxel@redhat.com> <3b872a56-80b5-0c44-712f-a9517489eb24@daenzer.net> <20170425095259.GK30290@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: Michel =?iso-8859-1?Q?D=E4nzer?= Cc: Daniel Vetter , amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Gerd Hoffmann , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, open list List-Id: dri-devel@lists.freedesktop.org T24gV2VkLCBBcHIgMjYsIDIwMTcgYXQgMTE6MDA6MDlBTSArMDkwMCwgTWljaGVsIETDpG56ZXIg d3JvdGU6Cj4gT24gMjUvMDQvMTcgMDY6NTIgUE0sIFZpbGxlIFN5cmrDpGzDpCB3cm90ZToKPiA+ IE9uIFR1ZSwgQXByIDI1LCAyMDE3IGF0IDEyOjE4OjUyUE0gKzA5MDAsIE1pY2hlbCBEw6RuemVy IHdyb3RlOgo+ID4+IE9uIDI0LzA0LzE3IDAzOjI1IFBNLCBHZXJkIEhvZmZtYW5uIHdyb3RlOgo+ ID4+PiArI2lmZGVmIF9fQklHX0VORElBTgo+ID4+PiArCXN3aXRjaCAoYnBwKSB7Cj4gPj4+ICsJ Y2FzZSA4Ogo+ID4+PiArCQlmbXQgPSBEUk1fRk9STUFUX0M4Owo+ID4+PiArCQlicmVhazsKPiA+ Pj4gKwljYXNlIDI0Ogo+ID4+PiArCQlmbXQgPSBEUk1fRk9STUFUX0JHUjg4ODsKPiA+Pj4gKwkJ YnJlYWs7Cj4gPj4KPiA+PiBCVFcsIGVuZGlhbm5lc3MgYXMgYSBjb25jZXB0IGNhbm5vdCBhcHBs eSB0byA4IG9yIDI0IGJwcCBmb3JtYXRzLgo+ID4gCj4gPiBUbyA4YnBwIG5vLCBidXQgaXQgY2Fu IGVhc2lseSBhcHBseSB0byAyNGJwcC4KPiAKPiBBbnkgYnl0ZSBzd2FwcGluZyByaXBzIGFwYXJ0 IHRoZSBieXRlcyBvZiBhIDI0YnBwIHBpeGVsLCBzbyB0aG9zZQo+IGZvcm1hdHMgb25seSBtYWtl IHNlbnNlIGFzIHN0cmFpZ2h0IGFycmF5IGZvcm1hdHMuCgpJbiBteSBib29rIGxpdHRsZSBlbmRp YW4ganVzdCBtZWFucyAibHNiIGlzIHN0b3JlZCBpbiB0aGUgbG93ZXN0Cm1lbW9yeSBhZGRyZXNz Ii4gVGhlIGZhY3QgdGhhdCB5b3VyIENQVS9HUFUgY2FuJ3QgZG8gMyBieXRlIHN3YXBzCmlzIG5v dCByZWxldmFudCBmb3IgdGhhdCBkZWZpbml0aW9uIElNTy4KCi0tIApWaWxsZSBTeXJqw6Rsw6QK SW50ZWwgT1RDCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f CmFtZC1nZnggbWFpbGluZyBsaXN0CmFtZC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vYW1kLWdmeAo=