From: Luc MICHEL <luc.michel@git.antfield.fr>
To: qemu-devel@nongnu.org
Cc: Luc MICHEL <luc.michel@git.antfield.fr>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-trivial@nongnu.org
Subject: [Qemu-devel] [PATCH 1/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5
Date: Fri, 28 Apr 2017 14:56:32 +0200 [thread overview]
Message-ID: <20170428125632.5704-2-luc.michel@git.antfield.fr> (raw)
In-Reply-To: <20170428125632.5704-1-luc.michel@git.antfield.fr>
The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.
Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
---
target/arm/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b357aee778..47687a40c4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1062,6 +1062,8 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_CONST },
{ .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST },
+ { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
+ .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
2.12.2
next prev parent reply other threads:[~2017-04-28 12:57 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-28 12:56 [Qemu-devel] [PATCH 0/1] target/arm: add data cache invalidation cp15 instruction to cortex-r5 Luc MICHEL
2017-04-28 12:56 ` Luc MICHEL [this message]
2017-05-12 10:28 ` Luc MICHEL
2017-05-23 14:50 ` Michael Tokarev
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