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From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH 10/14] target/sh4: optimize gen_write_sr using extract op
Date: Tue,  2 May 2017 00:10:42 +0200	[thread overview]
Message-ID: <20170501221046.9369-11-aurelien@aurel32.net> (raw)
In-Reply-To: <20170501221046.9369-1-aurelien@aurel32.net>

This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target/sh4/translate.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 23636eeb4c..7de459c9a5 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src)
 {
     tcg_gen_andi_i32(cpu_sr, src,
                      ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T)));
-    tcg_gen_shri_i32(cpu_sr_q, src, SR_Q);
-    tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1);
-    tcg_gen_shri_i32(cpu_sr_m, src, SR_M);
-    tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1);
-    tcg_gen_shri_i32(cpu_sr_t, src, SR_T);
-    tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
+    tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1);
+    tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1);
+    tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1);
 }
 
 static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
-- 
2.11.0

  parent reply	other threads:[~2017-05-01 22:11 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-01 22:10 [Qemu-devel] [PATCH 00/14] target/sh4: misc fixes, cleanup and optimizations Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 01/14] target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags Aurelien Jarno
2017-05-02 12:16   ` Philippe Mathieu-Daudé
2017-05-02 19:38     ` Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 02/14] target/sh4: get rid of DELAY_SLOT_CLEARME Aurelien Jarno
2017-05-02 12:32   ` Philippe Mathieu-Daudé
2017-05-01 22:10 ` [Qemu-devel] [PATCH 03/14] target/sh4: do not include DELAY_SLOT_TRUE in the TB state Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 04/14] target/sh4: move DELAY_SLOT_TRUE flag into a separate global Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 05/14] target/sh4: fix BS_STOP exit Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 06/14] target/sh4: fix BS_EXCP exit Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 07/14] target/sh4: only save flags state at the end of the TB Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 08/14] target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 09/14] target/sh4: optimize gen_store_fpr64 Aurelien Jarno
2017-05-01 22:10 ` Aurelien Jarno [this message]
2017-05-01 22:10 ` [Qemu-devel] [PATCH 11/14] target/sh4: generate fences for SH4 Aurelien Jarno
2017-05-02 12:58   ` Philippe Mathieu-Daudé
2017-05-01 22:10 ` [Qemu-devel] [PATCH 12/14] target/sh4: implement tas.b using atomic helper Aurelien Jarno
2017-05-01 22:10 ` [Qemu-devel] [PATCH 13/14] target/sh4: movua.l is an SH4-A only instruction Aurelien Jarno
2017-05-02 12:52   ` Philippe Mathieu-Daudé
2017-05-01 22:10 ` [Qemu-devel] [PATCH 14/14] target/sh4: trap unaligned accesses Aurelien Jarno
2017-05-02 12:57   ` Philippe Mathieu-Daudé

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