From: Mahesh Kumar <mahesh1.kumar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: paulo.r.zanoni@intel.com, maarten.lankhorst@intel.com
Subject: [PATCH 00/11] Implement DDB algorithm and WM cleanup
Date: Mon, 8 May 2017 17:18:51 +0530 [thread overview]
Message-ID: <20170508114902.18965-1-mahesh1.kumar@intel.com> (raw)
This series implements new DDB allocation algorithm to solve the cases,
where we have sufficient DDB available to enable multiple planes, But
due to the current algorithm not dividing it properly among planes, we
end-up failing the flip.
It also takes care of enabling same watermark level for each
plane, for efficient power saving.
Series also fixes/cleans-up few bug in present code.
There are two steps in current WM programming.
1. Calculate minimum number of blocks required for a WM level to be
enabled. For 1440x2560 panel we need 41 blocks as minimum number of
blocks to enable WM0. This is the step which doesn't use vertical size.
It only depends on Pipe drain rate and plane horizontal size as per the
current Bspec algorithm.
So all the plane below have minimum number of blocks required to enable
WM0 as 41
Plane 1 - 1440x2560 - Min blocks to enable WM0 = 41
Plane 2 - 1440x2560 - Min blocks to enable WM0 = 41
Plane 3 - 1440x48 - Min blocks to enable WM0 = 41
Plane 4 - 1440x96 - Min blocks to enable WM0 = 41
2. Number of blocks allotted by the driver
Driver allocates 12 for Plane 3 & 16 for plane 4
Total Dbuf Available = 508
Dbuf Available after 32 blocks for cursor = 508 - (32) = 476
allocate minimum blocks for each plane 8 * 4 = 32
remaining blocks = 476 - 32 = 444
Relative Data Rate for Planes
Plane 1 = 1440 * 2560 * 3 = 11059200
Plane 2 = 1440 * 2560 * 3 = 11059200
Plane 3 = 1440 * 48 * 3 = 207360
Plane 4 = 1440 * 96 * 3 = 414720
Total Relative BW = 22740480
- Allocate Buffer
buffer allocation = (Plane relative data rate / total data rate)
* total remaming DDB + minimum plane DDB
Plane 1 buffer allocation = (11059200 / 22740480) * 444 + 8 = 223
Plane 2 buffer allocation = (11059200 / 22740480) * 444 + 8 = 223
Plane 3 buffer allocation = (207360 / 22740480) * 444 + 8 = 12
Plane 4 buffer allocation = (414720 / 22740480) * 444 + 8 = 16
In this case it forced driver to disable Plane 3 & 4. Driver need to use
more efficient way to allocate buffer that is optimum for power.
New Algorithm suggested by HW team is:
1. Calculate minimum buffer allocations for each plane and for each
watermark level
2. Add minimum buffer allocations required for enabling WM7
for all the planes
Level 0 = 41 + 41 + 41 + 41 = 164
Level 1 = 42 + 42 + 42 + 42 = 168
Level 2 = 42 + 42 + 42 + 42 = 168
Level 3 = 94 + 94 + 94 + 94 = 376
Level 4 = 94 + 94 + 94 + 94 = 376
Level 5 = 94 + 94 + 94 + 94 = 376
Level 6 = 94 + 94 + 94 + 94 = 376
Level 7 = 94 + 94 + 94 + 94 = 376
3. Check to see how many buffer allocation are left and enable
the best case. In this case since we have 476 blocks we can enable
WM0-7 on all 4 planes.
Let's say if we have only 200 block available then the best cases
allocation is to enable Level2 which requires 168 blocks
Mahesh Kumar (11):
drm/i915: fix naming of fixed_16_16 wrapper.
drm/i915: Add more wrapper for fixed_point_16_16 operations
drm/i915: Use fixed_16_16 wrapper for division operation
drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed
point
drm/i915/skl: Fail the flip if no FB for WM calculation
drm/i915/skl+: no need to memset again
drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe
allocation
drm/i915/skl+: Watermark calculation cleanup
drm/i915/skl+: use linetime latency if ddb size is not available
drm/i915/skl: New ddb allocation algorithm
drm/i915/skl+: consider max supported plane pixel rate while scaling
drivers/gpu/drm/i915/i915_drv.h | 56 +++-
drivers/gpu/drm/i915/intel_display.c | 3 +
drivers/gpu/drm/i915/intel_drv.h | 2 +
drivers/gpu/drm/i915/intel_pm.c | 520 +++++++++++++++++++++++------------
4 files changed, 395 insertions(+), 186 deletions(-)
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next reply other threads:[~2017-05-08 11:45 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-08 11:48 Mahesh Kumar [this message]
2017-05-08 11:48 ` [PATCH 01/11] drm/i915: fix naming of fixed_16_16 wrapper Mahesh Kumar
2017-05-12 0:21 ` Matt Roper
2017-05-08 11:48 ` [PATCH 02/11] drm/i915: Add more wrapper for fixed_point_16_16 operations Mahesh Kumar
2017-05-10 12:37 ` Maarten Lankhorst
2017-05-12 0:22 ` Matt Roper
2017-05-12 8:55 ` Mahesh Kumar
2017-05-08 11:48 ` [PATCH 03/11] drm/i915: Use fixed_16_16 wrapper for division operation Mahesh Kumar
2017-05-12 0:22 ` Matt Roper
2017-05-08 11:48 ` [PATCH 04/11] drm/i915/skl+: calculate pixel_rate & relative_data_rate in fixed point Mahesh Kumar
2017-05-12 0:22 ` Matt Roper
2017-05-08 11:48 ` [PATCH 05/11] drm/i915/skl: Fail the flip if no FB for WM calculation Mahesh Kumar
2017-05-08 11:48 ` Lankhorst, Maarten
2017-05-08 12:01 ` Mahesh Kumar
2017-05-12 0:22 ` Matt Roper
2017-05-08 11:48 ` [PATCH 06/11] drm/i915/skl+: no need to memset again Mahesh Kumar
2017-05-12 0:23 ` Matt Roper
2017-05-08 11:48 ` [PATCH 07/11] drm/i915/skl+: Fail the flip if ddb min requirement exceeds pipe allocation Mahesh Kumar
2017-05-08 14:12 ` Ander Conselvan De Oliveira
2017-05-09 7:50 ` Mahesh Kumar
2017-05-09 7:52 ` Mahesh Kumar
2017-05-12 0:23 ` Matt Roper
2017-05-12 13:44 ` Mahesh Kumar
2017-05-08 11:48 ` [PATCH 08/11] drm/i915/skl+: Watermark calculation cleanup Mahesh Kumar
2017-05-12 0:23 ` Matt Roper
2017-05-12 13:47 ` Mahesh Kumar
2017-05-08 11:49 ` [PATCH 09/11] drm/i915/skl+: use linetime latency if ddb size is not available Mahesh Kumar
2017-05-08 11:49 ` [PATCH 10/11] drm/i915/skl: New ddb allocation algorithm Mahesh Kumar
2017-05-12 22:24 ` Matt Roper
2017-05-15 8:15 ` Mahesh Kumar
2017-05-08 11:49 ` [PATCH 11/11] drm/i915/skl+: consider max supported plane pixel rate while scaling Mahesh Kumar
2017-05-10 13:22 ` Maarten Lankhorst
2017-05-11 8:36 ` Mahesh Kumar
2017-05-11 9:48 ` Maarten Lankhorst
2017-05-11 10:59 ` Mahesh Kumar
2017-05-11 13:05 ` [PATCH v4 " Mahesh Kumar
2017-05-11 9:18 ` [PATCH v2] " Mahesh Kumar
2017-05-08 12:37 ` ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev2) Patchwork
2017-05-09 8:12 ` ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev4) Patchwork
2017-05-11 9:35 ` ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev5) Patchwork
2017-05-11 14:11 ` ✓ Fi.CI.BAT: success for Implement DDB algorithm and WM cleanup (rev6) Patchwork
2017-05-12 0:21 ` [PATCH 00/11] Implement DDB algorithm and WM cleanup Matt Roper
2017-05-12 8:25 ` Mahesh Kumar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170508114902.18965-1-mahesh1.kumar@intel.com \
--to=mahesh1.kumar@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=maarten.lankhorst@intel.com \
--cc=paulo.r.zanoni@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.