From: David Gibson <david@gibson.dropbear.id.au>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>,
Richard Henderson <rth@twiddle.net>,
Alexander Graf <agraf@suse.de>,
qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v4 5/6] target/ppc: optimize various functions using extract op
Date: Mon, 15 May 2017 14:12:58 +1000 [thread overview]
Message-ID: <20170515041258.GA11105@umbus.fritz.box> (raw)
In-Reply-To: <20170512233843.27713-6-f4bug@amsat.org>
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On Fri, May 12, 2017 at 08:38:42PM -0300, Philippe Mathieu-Daudé wrote:
> Patch created mechanically using Coccinelle script via:
>
> $ spatch --macro-file scripts/cocci-macro-file.h --in-place \
> --sp-file scripts/coccinelle/tcg_gen_extract.cocci --dir target
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Do you want me to merge this via my ppc tree, or is the whole set
going in via some other path?
> ---
> target/ppc/translate.c | 21 +++++++--------------
> target/ppc/translate/vsx-impl.inc.c | 24 ++++++++----------------
> 2 files changed, 15 insertions(+), 30 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index f40b5a1abf..6521365bfa 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -868,8 +868,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
> }
> tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
> tcg_temp_free(t1);
> - tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
> - tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
> + tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
> if (is_isa300(ctx)) {
> tcg_gen_mov_tl(cpu_ca32, cpu_ca);
> }
> @@ -1399,8 +1398,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
> tcg_temp_free(inv1);
> tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
> tcg_temp_free(t1);
> - tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
> - tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
> + tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
> if (is_isa300(ctx)) {
> tcg_gen_mov_tl(cpu_ca32, cpu_ca);
> }
> @@ -4310,8 +4308,7 @@ static void gen_mfsrin(DisasContext *ctx)
>
> CHK_SV;
> t0 = tcg_temp_new();
> - tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
> - tcg_gen_andi_tl(t0, t0, 0xF);
> + tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
> gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
> tcg_temp_free(t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> @@ -4342,8 +4339,7 @@ static void gen_mtsrin(DisasContext *ctx)
> CHK_SV;
>
> t0 = tcg_temp_new();
> - tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
> - tcg_gen_andi_tl(t0, t0, 0xF);
> + tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
> gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
> tcg_temp_free(t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> @@ -4377,8 +4373,7 @@ static void gen_mfsrin_64b(DisasContext *ctx)
>
> CHK_SV;
> t0 = tcg_temp_new();
> - tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
> - tcg_gen_andi_tl(t0, t0, 0xF);
> + tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
> gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
> tcg_temp_free(t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> @@ -4409,8 +4404,7 @@ static void gen_mtsrin_64b(DisasContext *ctx)
>
> CHK_SV;
> t0 = tcg_temp_new();
> - tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
> - tcg_gen_andi_tl(t0, t0, 0xF);
> + tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
> gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
> tcg_temp_free(t0);
> #endif /* defined(CONFIG_USER_ONLY) */
> @@ -5383,8 +5377,7 @@ static void gen_mfsri(DisasContext *ctx)
> CHK_SV;
> t0 = tcg_temp_new();
> gen_addr_reg_index(ctx, t0);
> - tcg_gen_shri_tl(t0, t0, 28);
> - tcg_gen_andi_tl(t0, t0, 0xF);
> + tcg_gen_extract_tl(t0, t0, 28, 4);
> gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
> tcg_temp_free(t0);
> if (ra != 0 && ra != rd)
> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> index 7f12908029..85ed135d44 100644
> --- a/target/ppc/translate/vsx-impl.inc.c
> +++ b/target/ppc/translate/vsx-impl.inc.c
> @@ -1248,8 +1248,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
> gen_exception(ctx, POWERPC_EXCP_VSXU);
> return;
> }
> - tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
> - tcg_gen_andi_i64(rt, rt, 0x7FF);
> + tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11);
> }
>
> static void gen_xsxexpqp(DisasContext *ctx)
> @@ -1262,8 +1261,7 @@ static void gen_xsxexpqp(DisasContext *ctx)
> gen_exception(ctx, POWERPC_EXCP_VSXU);
> return;
> }
> - tcg_gen_shri_i64(xth, xbh, 48);
> - tcg_gen_andi_i64(xth, xth, 0x7FFF);
> + tcg_gen_extract_i64(xth, xbh, 48, 15);
> tcg_gen_movi_i64(xtl, 0);
> }
>
> @@ -1323,8 +1321,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
> zr = tcg_const_i64(0);
> nan = tcg_const_i64(2047);
>
> - tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
> - tcg_gen_andi_i64(exp, exp, 0x7FF);
> + tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11);
> tcg_gen_movi_i64(t0, 0x0010000000000000);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
> @@ -1352,8 +1349,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
> zr = tcg_const_i64(0);
> nan = tcg_const_i64(32767);
>
> - tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
> - tcg_gen_andi_i64(exp, exp, 0x7FFF);
> + tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15);
> tcg_gen_movi_i64(t0, 0x0001000000000000);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
> @@ -1448,10 +1444,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
> gen_exception(ctx, POWERPC_EXCP_VSXU);
> return;
> }
> - tcg_gen_shri_i64(xth, xbh, 52);
> - tcg_gen_andi_i64(xth, xth, 0x7FF);
> - tcg_gen_shri_i64(xtl, xbl, 52);
> - tcg_gen_andi_i64(xtl, xtl, 0x7FF);
> + tcg_gen_extract_i64(xth, xbh, 52, 11);
> + tcg_gen_extract_i64(xtl, xbl, 52, 11);
> }
>
> GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
> @@ -1474,16 +1468,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
> zr = tcg_const_i64(0);
> nan = tcg_const_i64(2047);
>
> - tcg_gen_shri_i64(exp, xbh, 52);
> - tcg_gen_andi_i64(exp, exp, 0x7FF);
> + tcg_gen_extract_i64(exp, xbh, 52, 11);
> tcg_gen_movi_i64(t0, 0x0010000000000000);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
> tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
> tcg_gen_or_i64(xth, xth, t0);
>
> - tcg_gen_shri_i64(exp, xbl, 52);
> - tcg_gen_andi_i64(exp, exp, 0x7FF);
> + tcg_gen_extract_i64(exp, xbl, 52, 11);
> tcg_gen_movi_i64(t0, 0x0010000000000000);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
> tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2017-05-15 4:51 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-12 23:38 [Qemu-devel] [RFC PATCH v4 0/6] optimize various tcg_gen() functions using extract op Philippe Mathieu-Daudé
2017-05-12 23:38 ` [Qemu-devel] [RFC PATCH v4 1/6] coccinelle: add a script to optimize tcg op using tcg_gen_extract() Philippe Mathieu-Daudé
2017-05-15 14:04 ` Eric Blake
2017-05-15 14:06 ` Paolo Bonzini
2017-05-15 14:10 ` Laurent Vivier
2017-05-12 23:38 ` [Qemu-devel] [PATCH v4 2/6] target/alpha: optimize cvtlq() using extract op Philippe Mathieu-Daudé
2017-05-13 0:04 ` Richard Henderson
2017-05-12 23:38 ` [Qemu-devel] [PATCH v4 3/6] target/arm: optimize rev16() " Philippe Mathieu-Daudé
2017-05-12 23:38 ` [Qemu-devel] [PATCH v4 4/6] target/m68k: optimize bcd_flags() " Philippe Mathieu-Daudé
2017-05-13 0:05 ` Richard Henderson
2017-05-12 23:38 ` [Qemu-devel] [PATCH v4 5/6] target/ppc: optimize various functions " Philippe Mathieu-Daudé
2017-05-13 0:05 ` Richard Henderson
2017-05-15 4:12 ` David Gibson [this message]
2017-05-16 0:02 ` Philippe Mathieu-Daudé
2017-05-12 23:38 ` [Qemu-devel] [PATCH v4 6/6] target/sparc: " Philippe Mathieu-Daudé
2017-05-13 0:08 ` Richard Henderson
2017-07-18 3:18 ` Philippe Mathieu-Daudé
2017-07-18 3:44 ` Richard Henderson
2017-05-13 1:16 ` [Qemu-devel] [RFC PATCH v4 0/6] optimize various tcg_gen() " Julia Lawall
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