From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755780AbdEQRN7 (ORCPT ); Wed, 17 May 2017 13:13:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:39966 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755152AbdEQRL5 (ORCPT ); Wed, 17 May 2017 13:11:57 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E078423960 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=helgaas@kernel.org Date: Wed, 17 May 2017 12:11:54 -0500 From: Bjorn Helgaas To: Oza Pawandeep Cc: Joerg Roedel , Robin Murphy , iommu@lists.linux-foundation.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, Oza Pawandeep Subject: Re: [PATCH v6 2/3] iommu/pci: reserve IOVA for PCI masters Message-ID: <20170517171154.GF31462@bhelgaas-glaptop.roam.corp.google.com> References: <1494912127-12890-1-git-send-email-oza.oza@broadcom.com> <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 16, 2017 at 10:52:06AM +0530, Oza Pawandeep wrote: > this patch reserves the IOVA for PCI masters. > ARM64 based SOCs may have scattered memory banks. > such as iproc based SOC has > > <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > <0x00000008 0x80000000 0x3 0x80000000>, /* 14G @ 34G */ > <0x00000090 0x00000000 0x4 0x00000000>, /* 16G @ 576G */ > <0x000000a0 0x00000000 0x4 0x00000000>; /* 16G @ 640G */ > > but incoming PCI transcation addressing capability is limited s/transcation/transaction/ > by host bridge, for example if max incoming window capability > is 512 GB, then 0x00000090 and 0x000000a0 will fall beyond it. > > to address this problem, iommu has to avoid allocating IOVA which s/iommu/IOMMU/ > are reserved. which inturn does not allocate IOVA if it falls into hole. s/inturn/in turn/ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Bjorn Helgaas Subject: Re: [PATCH v6 2/3] iommu/pci: reserve IOVA for PCI masters Date: Wed, 17 May 2017 12:11:54 -0500 Message-ID: <20170517171154.GF31462@bhelgaas-glaptop.roam.corp.google.com> References: <1494912127-12890-1-git-send-email-oza.oza@broadcom.com> <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1494912127-12890-3-git-send-email-oza.oza-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Oza Pawandeep Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Oza Pawandeep , linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Tue, May 16, 2017 at 10:52:06AM +0530, Oza Pawandeep wrote: > this patch reserves the IOVA for PCI masters. > ARM64 based SOCs may have scattered memory banks. > such as iproc based SOC has > > <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > <0x00000008 0x80000000 0x3 0x80000000>, /* 14G @ 34G */ > <0x00000090 0x00000000 0x4 0x00000000>, /* 16G @ 576G */ > <0x000000a0 0x00000000 0x4 0x00000000>; /* 16G @ 640G */ > > but incoming PCI transcation addressing capability is limited s/transcation/transaction/ > by host bridge, for example if max incoming window capability > is 512 GB, then 0x00000090 and 0x000000a0 will fall beyond it. > > to address this problem, iommu has to avoid allocating IOVA which s/iommu/IOMMU/ > are reserved. which inturn does not allocate IOVA if it falls into hole. s/inturn/in turn/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Date: Wed, 17 May 2017 12:11:54 -0500 From: Bjorn Helgaas To: Oza Pawandeep Subject: Re: [PATCH v6 2/3] iommu/pci: reserve IOVA for PCI masters Message-ID: <20170517171154.GF31462@bhelgaas-glaptop.roam.corp.google.com> References: <1494912127-12890-1-git-send-email-oza.oza@broadcom.com> <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> MIME-Version: 1.0 In-Reply-To: <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Oza Pawandeep , linux-pci@vger.kernel.org, Joerg Roedel , linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, bcm-kernel-feedback-list@broadcom.com, Robin Murphy , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: On Tue, May 16, 2017 at 10:52:06AM +0530, Oza Pawandeep wrote: > this patch reserves the IOVA for PCI masters. > ARM64 based SOCs may have scattered memory banks. > such as iproc based SOC has > > <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > <0x00000008 0x80000000 0x3 0x80000000>, /* 14G @ 34G */ > <0x00000090 0x00000000 0x4 0x00000000>, /* 16G @ 576G */ > <0x000000a0 0x00000000 0x4 0x00000000>; /* 16G @ 640G */ > > but incoming PCI transcation addressing capability is limited s/transcation/transaction/ > by host bridge, for example if max incoming window capability > is 512 GB, then 0x00000090 and 0x000000a0 will fall beyond it. > > to address this problem, iommu has to avoid allocating IOVA which s/iommu/IOMMU/ > are reserved. which inturn does not allocate IOVA if it falls into hole. s/inturn/in turn/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: helgaas@kernel.org (Bjorn Helgaas) Date: Wed, 17 May 2017 12:11:54 -0500 Subject: [PATCH v6 2/3] iommu/pci: reserve IOVA for PCI masters In-Reply-To: <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> References: <1494912127-12890-1-git-send-email-oza.oza@broadcom.com> <1494912127-12890-3-git-send-email-oza.oza@broadcom.com> Message-ID: <20170517171154.GF31462@bhelgaas-glaptop.roam.corp.google.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, May 16, 2017 at 10:52:06AM +0530, Oza Pawandeep wrote: > this patch reserves the IOVA for PCI masters. > ARM64 based SOCs may have scattered memory banks. > such as iproc based SOC has > > <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ > <0x00000008 0x80000000 0x3 0x80000000>, /* 14G @ 34G */ > <0x00000090 0x00000000 0x4 0x00000000>, /* 16G @ 576G */ > <0x000000a0 0x00000000 0x4 0x00000000>; /* 16G @ 640G */ > > but incoming PCI transcation addressing capability is limited s/transcation/transaction/ > by host bridge, for example if max incoming window capability > is 512 GB, then 0x00000090 and 0x000000a0 will fall beyond it. > > to address this problem, iommu has to avoid allocating IOVA which s/iommu/IOMMU/ > are reserved. which inturn does not allocate IOVA if it falls into hole. s/inturn/in turn/