From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932136AbdEQSKk (ORCPT ); Wed, 17 May 2017 14:10:40 -0400 Received: from mail.skyhub.de ([5.9.137.197]:41794 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752764AbdEQSKh (ORCPT ); Wed, 17 May 2017 14:10:37 -0400 Date: Wed, 17 May 2017 20:10:21 +0200 From: Borislav Petkov To: Chris Packham , linuxppc-dev@lists.ozlabs.org Cc: linux-edac@vger.kernel.org, mchehab@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/3] EDAC: mv64x60: replace in_le32/out_le32 with ioread32/iowrite32 Message-ID: <20170517181021.yfctrok7f25d5bu5@pd.tnic> References: <20170512042002.18524-1-chris.packham@alliedtelesis.co.nz> <20170512042002.18524-4-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20170512042002.18524-4-chris.packham@alliedtelesis.co.nz> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Top-posting so that the PPC list can see the whole patch below. Since I don't know PPC, let me add PPC ML to CC for a confirmation this change is correct. Which brings me to the tangential: this driver is from 2006-ish and is for some "Marvell MV64x60 Memory Controller kernel module for PPC platforms". If you're going to touch it, then you should test on the PPC hardware too, so that you don't break the driver there. Unless that hardware is obsolete now and we don't care and, and ..? Maybe someone has some insights... On Fri, May 12, 2017 at 04:20:02PM +1200, Chris Packham wrote: > To allow this driver to be used on non-powerpc platforms it needs to use > io accessors suitable for all platforms. > > Signed-off-by: Chris Packham > --- > drivers/edac/mv64x60_edac.c | 84 ++++++++++++++++++++++----------------------- > 1 file changed, 42 insertions(+), 42 deletions(-) > > diff --git a/drivers/edac/mv64x60_edac.c b/drivers/edac/mv64x60_edac.c > index ddc5082f7577..102ec29f864b 100644 > --- a/drivers/edac/mv64x60_edac.c > +++ b/drivers/edac/mv64x60_edac.c > @@ -32,21 +32,21 @@ static void mv64x60_pci_check(struct edac_pci_ctl_info *pci) > struct mv64x60_pci_pdata *pdata = pci->pvt_info; > u32 cause; > > - cause = in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); > + cause = ioread32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); > if (!cause) > return; > > printk(KERN_ERR "Error in PCI %d Interface\n", pdata->pci_hose); > printk(KERN_ERR "Cause register: 0x%08x\n", cause); > printk(KERN_ERR "Address Low: 0x%08x\n", > - in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_LO)); > + ioread32(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_LO)); > printk(KERN_ERR "Address High: 0x%08x\n", > - in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_HI)); > + ioread32(pdata->pci_vbase + MV64X60_PCI_ERROR_ADDR_HI)); > printk(KERN_ERR "Attribute: 0x%08x\n", > - in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_ATTR)); > + ioread32(pdata->pci_vbase + MV64X60_PCI_ERROR_ATTR)); > printk(KERN_ERR "Command: 0x%08x\n", > - in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CMD)); > - out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE, ~cause); > + ioread32(pdata->pci_vbase + MV64X60_PCI_ERROR_CMD)); > + iowrite32(~cause, pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); > > if (cause & MV64X60_PCI_PE_MASK) > edac_pci_handle_pe(pci, pci->ctl_name); > @@ -61,7 +61,7 @@ static irqreturn_t mv64x60_pci_isr(int irq, void *dev_id) > struct mv64x60_pci_pdata *pdata = pci->pvt_info; > u32 val; > > - val = in_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); > + val = ioread32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); > if (!val) > return IRQ_NONE; > > @@ -93,7 +93,7 @@ static int __init mv64x60_pci_fixup(struct platform_device *pdev) > if (!pci_serr) > return -ENOMEM; > > - out_le32(pci_serr, in_le32(pci_serr) & ~0x1); > + iowrite32(ioread32(pci_serr) & ~0x1, pci_serr); > iounmap(pci_serr); > > return 0; > @@ -161,10 +161,10 @@ static int mv64x60_pci_err_probe(struct platform_device *pdev) > goto err; > } > > - out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE, 0); > - out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_MASK, 0); > - out_le32(pdata->pci_vbase + MV64X60_PCI_ERROR_MASK, > - MV64X60_PCIx_ERR_MASK_VAL); > + iowrite32(0, pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); > + iowrite32(0, pdata->pci_vbase + MV64X60_PCI_ERROR_MASK); > + iowrite32(MV64X60_PCIx_ERR_MASK_VAL, > + pdata->pci_vbase + MV64X60_PCI_ERROR_MASK); > > if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { > edac_dbg(3, "failed edac_pci_add_device()\n"); > @@ -233,23 +233,23 @@ static void mv64x60_sram_check(struct edac_device_ctl_info *edac_dev) > struct mv64x60_sram_pdata *pdata = edac_dev->pvt_info; > u32 cause; > > - cause = in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); > + cause = ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); > if (!cause) > return; > > printk(KERN_ERR "Error in internal SRAM\n"); > printk(KERN_ERR "Cause register: 0x%08x\n", cause); > printk(KERN_ERR "Address Low: 0x%08x\n", > - in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_LO)); > + ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_LO)); > printk(KERN_ERR "Address High: 0x%08x\n", > - in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_HI)); > + ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_ADDR_HI)); > printk(KERN_ERR "Data Low: 0x%08x\n", > - in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_LO)); > + ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_LO)); > printk(KERN_ERR "Data High: 0x%08x\n", > - in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_HI)); > + ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_DATA_HI)); > printk(KERN_ERR "Parity: 0x%08x\n", > - in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_PARITY)); > - out_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE, 0); > + ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_PARITY)); > + iowrite32(0, pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); > > edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); > } > @@ -260,7 +260,7 @@ static irqreturn_t mv64x60_sram_isr(int irq, void *dev_id) > struct mv64x60_sram_pdata *pdata = edac_dev->pvt_info; > u32 cause; > > - cause = in_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); > + cause = ioread32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); > if (!cause) > return IRQ_NONE; > > @@ -322,7 +322,7 @@ static int mv64x60_sram_err_probe(struct platform_device *pdev) > } > > /* setup SRAM err registers */ > - out_le32(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE, 0); > + iowrite32(0, pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); > > edac_dev->mod_name = EDAC_MOD_STR; > edac_dev->ctl_name = pdata->name; > @@ -398,7 +398,7 @@ static void mv64x60_cpu_check(struct edac_device_ctl_info *edac_dev) > struct mv64x60_cpu_pdata *pdata = edac_dev->pvt_info; > u32 cause; > > - cause = in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) & > + cause = ioread32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) & > MV64x60_CPU_CAUSE_MASK; > if (!cause) > return; > @@ -406,16 +406,16 @@ static void mv64x60_cpu_check(struct edac_device_ctl_info *edac_dev) > printk(KERN_ERR "Error on CPU interface\n"); > printk(KERN_ERR "Cause register: 0x%08x\n", cause); > printk(KERN_ERR "Address Low: 0x%08x\n", > - in_le32(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_LO)); > + ioread32(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_LO)); > printk(KERN_ERR "Address High: 0x%08x\n", > - in_le32(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_HI)); > + ioread32(pdata->cpu_vbase[0] + MV64x60_CPU_ERR_ADDR_HI)); > printk(KERN_ERR "Data Low: 0x%08x\n", > - in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_LO)); > + ioread32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_LO)); > printk(KERN_ERR "Data High: 0x%08x\n", > - in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_HI)); > + ioread32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_DATA_HI)); > printk(KERN_ERR "Parity: 0x%08x\n", > - in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_PARITY)); > - out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE, 0); > + ioread32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_PARITY)); > + iowrite32(0, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE); > > edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); > } > @@ -426,7 +426,7 @@ static irqreturn_t mv64x60_cpu_isr(int irq, void *dev_id) > struct mv64x60_cpu_pdata *pdata = edac_dev->pvt_info; > u32 cause; > > - cause = in_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) & > + cause = ioread32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE) & > MV64x60_CPU_CAUSE_MASK; > if (!cause) > return IRQ_NONE; > @@ -515,9 +515,9 @@ static int mv64x60_cpu_err_probe(struct platform_device *pdev) > } > > /* setup CPU err registers */ > - out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE, 0); > - out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK, 0); > - out_le32(pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK, 0x000000ff); > + iowrite32(0, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_CAUSE); > + iowrite32(0, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK); > + iowrite32(0x000000ff, pdata->cpu_vbase[1] + MV64x60_CPU_ERR_MASK); > > edac_dev->mod_name = EDAC_MOD_STR; > edac_dev->ctl_name = pdata->name; > @@ -596,13 +596,13 @@ static void mv64x60_mc_check(struct mem_ctl_info *mci) > u32 comp_ecc; > u32 syndrome; > > - reg = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); > + reg = ioread32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); > if (!reg) > return; > > err_addr = reg & ~0x3; > - sdram_ecc = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_RCVD); > - comp_ecc = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CALC); > + sdram_ecc = ioread32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_RCVD); > + comp_ecc = ioread32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CALC); > syndrome = sdram_ecc ^ comp_ecc; > > /* first bit clear in ECC Err Reg, 1 bit error, correctable by HW */ > @@ -620,7 +620,7 @@ static void mv64x60_mc_check(struct mem_ctl_info *mci) > mci->ctl_name, ""); > > /* clear the error */ > - out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR, 0); > + iowrite32(0, pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); > } > > static irqreturn_t mv64x60_mc_isr(int irq, void *dev_id) > @@ -629,7 +629,7 @@ static irqreturn_t mv64x60_mc_isr(int irq, void *dev_id) > struct mv64x60_mc_pdata *pdata = mci->pvt_info; > u32 reg; > > - reg = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); > + reg = ioread32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); > if (!reg) > return IRQ_NONE; > > @@ -664,7 +664,7 @@ static void mv64x60_init_csrows(struct mem_ctl_info *mci, > > get_total_mem(pdata); > > - ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG); > + ctl = ioread32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG); > > csrow = mci->csrows[0]; > dimm = csrow->channels[0]->dimm; > @@ -753,7 +753,7 @@ static int mv64x60_mc_err_probe(struct platform_device *pdev) > goto err; > } > > - ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG); > + ctl = ioread32(pdata->mc_vbase + MV64X60_SDRAM_CONFIG); > if (!(ctl & MV64X60_SDRAM_ECC)) { > /* Non-ECC RAM? */ > printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); > @@ -779,10 +779,10 @@ static int mv64x60_mc_err_probe(struct platform_device *pdev) > mv64x60_init_csrows(mci, pdata); > > /* setup MC registers */ > - out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR, 0); > - ctl = in_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL); > + iowrite32(0, pdata->mc_vbase + MV64X60_SDRAM_ERR_ADDR); > + ctl = ioread32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL); > ctl = (ctl & 0xff00ffff) | 0x10000; > - out_le32(pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL, ctl); > + iowrite32(ctl, pdata->mc_vbase + MV64X60_SDRAM_ERR_ECC_CNTL); > > res = edac_mc_add_mc(mci); > if (res) { > -- > 2.11.0.24.ge6920cf > -- Regards/Gruss, Boris. Good mailing practices for 400: try to avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [3/3] EDAC: mv64x60: replace in_le32/out_le32 with ioread32/iowrite32 From: Borislav Petkov Message-Id: <20170517181021.yfctrok7f25d5bu5@pd.tnic> Date: Wed, 17 May 2017 20:10:21 +0200 To: Chris Packham , linuxppc-dev@lists.ozlabs.org Cc: linux-edac@vger.kernel.org, mchehab@kernel.org, linux-kernel@vger.kernel.org List-ID: VG9wLXBvc3Rpbmcgc28gdGhhdCB0aGUgUFBDIGxpc3QgY2FuIHNlZSB0aGUgd2hvbGUgcGF0Y2gg YmVsb3cuCgpTaW5jZSBJIGRvbid0IGtub3cgUFBDLCBsZXQgbWUgYWRkIFBQQyBNTCB0byBDQyBm b3IgYSBjb25maXJtYXRpb24gdGhpcwpjaGFuZ2UgaXMgY29ycmVjdC4KCldoaWNoIGJyaW5ncyBt ZSB0byB0aGUgdGFuZ2VudGlhbDogdGhpcyBkcml2ZXIgaXMgZnJvbSAyMDA2LWlzaCBhbmQKaXMg Zm9yIHNvbWUgIk1hcnZlbGwgTVY2NHg2MCBNZW1vcnkgQ29udHJvbGxlciBrZXJuZWwgbW9kdWxl IGZvciBQUEMKcGxhdGZvcm1zIi4gSWYgeW91J3JlIGdvaW5nIHRvIHRvdWNoIGl0LCB0aGVuIHlv dSBzaG91bGQgdGVzdCBvbiB0aGUgUFBDCmhhcmR3YXJlIHRvbywgc28gdGhhdCB5b3UgZG9uJ3Qg YnJlYWsgdGhlIGRyaXZlciB0aGVyZS4KClVubGVzcyB0aGF0IGhhcmR3YXJlIGlzIG9ic29sZXRl IG5vdyBhbmQgd2UgZG9uJ3QgY2FyZSBhbmQsIGFuZCAuLj8KCk1heWJlIHNvbWVvbmUgaGFzIHNv bWUgaW5zaWdodHMuLi4KCk9uIEZyaSwgTWF5IDEyLCAyMDE3IGF0IDA0OjIwOjAyUE0gKzEyMDAs IENocmlzIFBhY2toYW0gd3JvdGU6Cj4gVG8gYWxsb3cgdGhpcyBkcml2ZXIgdG8gYmUgdXNlZCBv biBub24tcG93ZXJwYyBwbGF0Zm9ybXMgaXQgbmVlZHMgdG8gdXNlCj4gaW8gYWNjZXNzb3JzIHN1 aXRhYmxlIGZvciBhbGwgcGxhdGZvcm1zLgo+IAo+IFNpZ25lZC1vZmYtYnk6IENocmlzIFBhY2to YW0gPGNocmlzLnBhY2toYW1AYWxsaWVkdGVsZXNpcy5jby5uej4KPiAtLS0KPiAgZHJpdmVycy9l ZGFjL212NjR4NjBfZWRhYy5jIHwgODQgKysrKysrKysrKysrKysrKysrKysrKy0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tCj4gIDEgZmlsZSBjaGFuZ2VkLCA0MiBpbnNlcnRpb25zKCspLCA0MiBkZWxl dGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9lZGFjL212NjR4NjBfZWRhYy5jIGIv ZHJpdmVycy9lZGFjL212NjR4NjBfZWRhYy5jCj4gaW5kZXggZGRjNTA4MmY3NTc3Li4xMDJlYzI5 Zjg2NGIgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9lZGFjL212NjR4NjBfZWRhYy5jCj4gKysrIGIv ZHJpdmVycy9lZGFjL212NjR4NjBfZWRhYy5jCj4gQEAgLTMyLDIxICszMiwyMSBAQCBzdGF0aWMg dm9pZCBtdjY0eDYwX3BjaV9jaGVjayhzdHJ1Y3QgZWRhY19wY2lfY3RsX2luZm8gKnBjaSkKPiAg CXN0cnVjdCBtdjY0eDYwX3BjaV9wZGF0YSAqcGRhdGEgPSBwY2ktPnB2dF9pbmZvOwo+ICAJdTMy IGNhdXNlOwo+ICAKPiAtCWNhdXNlID0gaW5fbGUzMihwZGF0YS0+cGNpX3ZiYXNlICsgTVY2NFg2 MF9QQ0lfRVJST1JfQ0FVU0UpOwo+ICsJY2F1c2UgPSBpb3JlYWQzMihwZGF0YS0+cGNpX3ZiYXNl ICsgTVY2NFg2MF9QQ0lfRVJST1JfQ0FVU0UpOwo+ICAJaWYgKCFjYXVzZSkKPiAgCQlyZXR1cm47 Cj4gIAo+ICAJcHJpbnRrKEtFUk5fRVJSICJFcnJvciBpbiBQQ0kgJWQgSW50ZXJmYWNlXG4iLCBw ZGF0YS0+cGNpX2hvc2UpOwo+ICAJcHJpbnRrKEtFUk5fRVJSICJDYXVzZSByZWdpc3RlcjogMHgl MDh4XG4iLCBjYXVzZSk7Cj4gIAlwcmludGsoS0VSTl9FUlIgIkFkZHJlc3MgTG93OiAweCUwOHhc biIsCj4gLQkgICAgICAgaW5fbGUzMihwZGF0YS0+cGNpX3ZiYXNlICsgTVY2NFg2MF9QQ0lfRVJS T1JfQUREUl9MTykpOwo+ICsJICAgICAgIGlvcmVhZDMyKHBkYXRhLT5wY2lfdmJhc2UgKyBNVjY0 WDYwX1BDSV9FUlJPUl9BRERSX0xPKSk7Cj4gIAlwcmludGsoS0VSTl9FUlIgIkFkZHJlc3MgSGln aDogMHglMDh4XG4iLAo+IC0JICAgICAgIGluX2xlMzIocGRhdGEtPnBjaV92YmFzZSArIE1WNjRY NjBfUENJX0VSUk9SX0FERFJfSEkpKTsKPiArCSAgICAgICBpb3JlYWQzMihwZGF0YS0+cGNpX3Zi YXNlICsgTVY2NFg2MF9QQ0lfRVJST1JfQUREUl9ISSkpOwo+ICAJcHJpbnRrKEtFUk5fRVJSICJB dHRyaWJ1dGU6IDB4JTA4eFxuIiwKPiAtCSAgICAgICBpbl9sZTMyKHBkYXRhLT5wY2lfdmJhc2Ug KyBNVjY0WDYwX1BDSV9FUlJPUl9BVFRSKSk7Cj4gKwkgICAgICAgaW9yZWFkMzIocGRhdGEtPnBj aV92YmFzZSArIE1WNjRYNjBfUENJX0VSUk9SX0FUVFIpKTsKPiAgCXByaW50ayhLRVJOX0VSUiAi Q29tbWFuZDogMHglMDh4XG4iLAo+IC0JICAgICAgIGluX2xlMzIocGRhdGEtPnBjaV92YmFzZSAr IE1WNjRYNjBfUENJX0VSUk9SX0NNRCkpOwo+IC0Jb3V0X2xlMzIocGRhdGEtPnBjaV92YmFzZSAr IE1WNjRYNjBfUENJX0VSUk9SX0NBVVNFLCB+Y2F1c2UpOwo+ICsJICAgICAgIGlvcmVhZDMyKHBk YXRhLT5wY2lfdmJhc2UgKyBNVjY0WDYwX1BDSV9FUlJPUl9DTUQpKTsKPiArCWlvd3JpdGUzMih+ Y2F1c2UsIHBkYXRhLT5wY2lfdmJhc2UgKyBNVjY0WDYwX1BDSV9FUlJPUl9DQVVTRSk7Cj4gIAo+ ICAJaWYgKGNhdXNlICYgTVY2NFg2MF9QQ0lfUEVfTUFTSykKPiAgCQllZGFjX3BjaV9oYW5kbGVf cGUocGNpLCBwY2ktPmN0bF9uYW1lKTsKPiBAQCAtNjEsNyArNjEsNyBAQCBzdGF0aWMgaXJxcmV0 dXJuX3QgbXY2NHg2MF9wY2lfaXNyKGludCBpcnEsIHZvaWQgKmRldl9pZCkKPiAgCXN0cnVjdCBt djY0eDYwX3BjaV9wZGF0YSAqcGRhdGEgPSBwY2ktPnB2dF9pbmZvOwo+ICAJdTMyIHZhbDsKPiAg Cj4gLQl2YWwgPSBpbl9sZTMyKHBkYXRhLT5wY2lfdmJhc2UgKyBNVjY0WDYwX1BDSV9FUlJPUl9D QVVTRSk7Cj4gKwl2YWwgPSBpb3JlYWQzMihwZGF0YS0+cGNpX3ZiYXNlICsgTVY2NFg2MF9QQ0lf RVJST1JfQ0FVU0UpOwo+ICAJaWYgKCF2YWwpCj4gIAkJcmV0dXJuIElSUV9OT05FOwo+ICAKPiBA QCAtOTMsNyArOTMsNyBAQCBzdGF0aWMgaW50IF9faW5pdCBtdjY0eDYwX3BjaV9maXh1cChzdHJ1 Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICAJaWYgKCFwY2lfc2VycikKPiAgCQlyZXR1cm4g LUVOT01FTTsKPiAgCj4gLQlvdXRfbGUzMihwY2lfc2VyciwgaW5fbGUzMihwY2lfc2VycikgJiB+ MHgxKTsKPiArCWlvd3JpdGUzMihpb3JlYWQzMihwY2lfc2VycikgJiB+MHgxLCBwY2lfc2Vycik7 Cj4gIAlpb3VubWFwKHBjaV9zZXJyKTsKPiAgCj4gIAlyZXR1cm4gMDsKPiBAQCAtMTYxLDEwICsx NjEsMTAgQEAgc3RhdGljIGludCBtdjY0eDYwX3BjaV9lcnJfcHJvYmUoc3RydWN0IHBsYXRmb3Jt X2RldmljZSAqcGRldikKPiAgCQlnb3RvIGVycjsKPiAgCX0KPiAgCj4gLQlvdXRfbGUzMihwZGF0 YS0+cGNpX3ZiYXNlICsgTVY2NFg2MF9QQ0lfRVJST1JfQ0FVU0UsIDApOwo+IC0Jb3V0X2xlMzIo cGRhdGEtPnBjaV92YmFzZSArIE1WNjRYNjBfUENJX0VSUk9SX01BU0ssIDApOwo+IC0Jb3V0X2xl MzIocGRhdGEtPnBjaV92YmFzZSArIE1WNjRYNjBfUENJX0VSUk9SX01BU0ssCj4gLQkJIE1WNjRY NjBfUENJeF9FUlJfTUFTS19WQUwpOwo+ICsJaW93cml0ZTMyKDAsIHBkYXRhLT5wY2lfdmJhc2Ug KyBNVjY0WDYwX1BDSV9FUlJPUl9DQVVTRSk7Cj4gKwlpb3dyaXRlMzIoMCwgcGRhdGEtPnBjaV92 YmFzZSArIE1WNjRYNjBfUENJX0VSUk9SX01BU0spOwo+ICsJaW93cml0ZTMyKE1WNjRYNjBfUENJ eF9FUlJfTUFTS19WQUwsCj4gKwkJICBwZGF0YS0+cGNpX3ZiYXNlICsgTVY2NFg2MF9QQ0lfRVJS T1JfTUFTSyk7Cj4gIAo+ICAJaWYgKGVkYWNfcGNpX2FkZF9kZXZpY2UocGNpLCBwZGF0YS0+ZWRh Y19pZHgpID4gMCkgewo+ICAJCWVkYWNfZGJnKDMsICJmYWlsZWQgZWRhY19wY2lfYWRkX2Rldmlj ZSgpXG4iKTsKPiBAQCAtMjMzLDIzICsyMzMsMjMgQEAgc3RhdGljIHZvaWQgbXY2NHg2MF9zcmFt X2NoZWNrKHN0cnVjdCBlZGFjX2RldmljZV9jdGxfaW5mbyAqZWRhY19kZXYpCj4gIAlzdHJ1Y3Qg bXY2NHg2MF9zcmFtX3BkYXRhICpwZGF0YSA9IGVkYWNfZGV2LT5wdnRfaW5mbzsKPiAgCXUzMiBj YXVzZTsKPiAgCj4gLQljYXVzZSA9IGluX2xlMzIocGRhdGEtPnNyYW1fdmJhc2UgKyBNVjY0WDYw X1NSQU1fRVJSX0NBVVNFKTsKPiArCWNhdXNlID0gaW9yZWFkMzIocGRhdGEtPnNyYW1fdmJhc2Ug KyBNVjY0WDYwX1NSQU1fRVJSX0NBVVNFKTsKPiAgCWlmICghY2F1c2UpCj4gIAkJcmV0dXJuOwo+ ICAKPiAgCXByaW50ayhLRVJOX0VSUiAiRXJyb3IgaW4gaW50ZXJuYWwgU1JBTVxuIik7Cj4gIAlw cmludGsoS0VSTl9FUlIgIkNhdXNlIHJlZ2lzdGVyOiAweCUwOHhcbiIsIGNhdXNlKTsKPiAgCXBy aW50ayhLRVJOX0VSUiAiQWRkcmVzcyBMb3c6IDB4JTA4eFxuIiwKPiAtCSAgICAgICBpbl9sZTMy KHBkYXRhLT5zcmFtX3ZiYXNlICsgTVY2NFg2MF9TUkFNX0VSUl9BRERSX0xPKSk7Cj4gKwkgICAg ICAgaW9yZWFkMzIocGRhdGEtPnNyYW1fdmJhc2UgKyBNVjY0WDYwX1NSQU1fRVJSX0FERFJfTE8p KTsKPiAgCXByaW50ayhLRVJOX0VSUiAiQWRkcmVzcyBIaWdoOiAweCUwOHhcbiIsCj4gLQkgICAg ICAgaW5fbGUzMihwZGF0YS0+c3JhbV92YmFzZSArIE1WNjRYNjBfU1JBTV9FUlJfQUREUl9ISSkp Owo+ICsJICAgICAgIGlvcmVhZDMyKHBkYXRhLT5zcmFtX3ZiYXNlICsgTVY2NFg2MF9TUkFNX0VS Ul9BRERSX0hJKSk7Cj4gIAlwcmludGsoS0VSTl9FUlIgIkRhdGEgTG93OiAweCUwOHhcbiIsCj4g LQkgICAgICAgaW5fbGUzMihwZGF0YS0+c3JhbV92YmFzZSArIE1WNjRYNjBfU1JBTV9FUlJfREFU QV9MTykpOwo+ICsJICAgICAgIGlvcmVhZDMyKHBkYXRhLT5zcmFtX3ZiYXNlICsgTVY2NFg2MF9T UkFNX0VSUl9EQVRBX0xPKSk7Cj4gIAlwcmludGsoS0VSTl9FUlIgIkRhdGEgSGlnaDogMHglMDh4 XG4iLAo+IC0JICAgICAgIGluX2xlMzIocGRhdGEtPnNyYW1fdmJhc2UgKyBNVjY0WDYwX1NSQU1f RVJSX0RBVEFfSEkpKTsKPiArCSAgICAgICBpb3JlYWQzMihwZGF0YS0+c3JhbV92YmFzZSArIE1W NjRYNjBfU1JBTV9FUlJfREFUQV9ISSkpOwo+ICAJcHJpbnRrKEtFUk5fRVJSICJQYXJpdHk6IDB4 JTA4eFxuIiwKPiAtCSAgICAgICBpbl9sZTMyKHBkYXRhLT5zcmFtX3ZiYXNlICsgTVY2NFg2MF9T UkFNX0VSUl9QQVJJVFkpKTsKPiAtCW91dF9sZTMyKHBkYXRhLT5zcmFtX3ZiYXNlICsgTVY2NFg2 MF9TUkFNX0VSUl9DQVVTRSwgMCk7Cj4gKwkgICAgICAgaW9yZWFkMzIocGRhdGEtPnNyYW1fdmJh c2UgKyBNVjY0WDYwX1NSQU1fRVJSX1BBUklUWSkpOwo+ICsJaW93cml0ZTMyKDAsIHBkYXRhLT5z cmFtX3ZiYXNlICsgTVY2NFg2MF9TUkFNX0VSUl9DQVVTRSk7Cj4gIAo+ICAJZWRhY19kZXZpY2Vf aGFuZGxlX3VlKGVkYWNfZGV2LCAwLCAwLCBlZGFjX2Rldi0+Y3RsX25hbWUpOwo+ICB9Cj4gQEAg LTI2MCw3ICsyNjAsNyBAQCBzdGF0aWMgaXJxcmV0dXJuX3QgbXY2NHg2MF9zcmFtX2lzcihpbnQg aXJxLCB2b2lkICpkZXZfaWQpCj4gIAlzdHJ1Y3QgbXY2NHg2MF9zcmFtX3BkYXRhICpwZGF0YSA9 IGVkYWNfZGV2LT5wdnRfaW5mbzsKPiAgCXUzMiBjYXVzZTsKPiAgCj4gLQljYXVzZSA9IGluX2xl MzIocGRhdGEtPnNyYW1fdmJhc2UgKyBNVjY0WDYwX1NSQU1fRVJSX0NBVVNFKTsKPiArCWNhdXNl ID0gaW9yZWFkMzIocGRhdGEtPnNyYW1fdmJhc2UgKyBNVjY0WDYwX1NSQU1fRVJSX0NBVVNFKTsK PiAgCWlmICghY2F1c2UpCj4gIAkJcmV0dXJuIElSUV9OT05FOwo+ICAKPiBAQCAtMzIyLDcgKzMy Miw3IEBAIHN0YXRpYyBpbnQgbXY2NHg2MF9zcmFtX2Vycl9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1f ZGV2aWNlICpwZGV2KQo+ICAJfQo+ICAKPiAgCS8qIHNldHVwIFNSQU0gZXJyIHJlZ2lzdGVycyAq Lwo+IC0Jb3V0X2xlMzIocGRhdGEtPnNyYW1fdmJhc2UgKyBNVjY0WDYwX1NSQU1fRVJSX0NBVVNF LCAwKTsKPiArCWlvd3JpdGUzMigwLCBwZGF0YS0+c3JhbV92YmFzZSArIE1WNjRYNjBfU1JBTV9F UlJfQ0FVU0UpOwo+ICAKPiAgCWVkYWNfZGV2LT5tb2RfbmFtZSA9IEVEQUNfTU9EX1NUUjsKPiAg CWVkYWNfZGV2LT5jdGxfbmFtZSA9IHBkYXRhLT5uYW1lOwo+IEBAIC0zOTgsNyArMzk4LDcgQEAg c3RhdGljIHZvaWQgbXY2NHg2MF9jcHVfY2hlY2soc3RydWN0IGVkYWNfZGV2aWNlX2N0bF9pbmZv ICplZGFjX2RldikKPiAgCXN0cnVjdCBtdjY0eDYwX2NwdV9wZGF0YSAqcGRhdGEgPSBlZGFjX2Rl di0+cHZ0X2luZm87Cj4gIAl1MzIgY2F1c2U7Cj4gIAo+IC0JY2F1c2UgPSBpbl9sZTMyKHBkYXRh LT5jcHVfdmJhc2VbMV0gKyBNVjY0eDYwX0NQVV9FUlJfQ0FVU0UpICYKPiArCWNhdXNlID0gaW9y ZWFkMzIocGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9DQVVTRSkgJgo+ICAJ ICAgIE1WNjR4NjBfQ1BVX0NBVVNFX01BU0s7Cj4gIAlpZiAoIWNhdXNlKQo+ICAJCXJldHVybjsK PiBAQCAtNDA2LDE2ICs0MDYsMTYgQEAgc3RhdGljIHZvaWQgbXY2NHg2MF9jcHVfY2hlY2soc3Ry dWN0IGVkYWNfZGV2aWNlX2N0bF9pbmZvICplZGFjX2RldikKPiAgCXByaW50ayhLRVJOX0VSUiAi RXJyb3Igb24gQ1BVIGludGVyZmFjZVxuIik7Cj4gIAlwcmludGsoS0VSTl9FUlIgIkNhdXNlIHJl Z2lzdGVyOiAweCUwOHhcbiIsIGNhdXNlKTsKPiAgCXByaW50ayhLRVJOX0VSUiAiQWRkcmVzcyBM b3c6IDB4JTA4eFxuIiwKPiAtCSAgICAgICBpbl9sZTMyKHBkYXRhLT5jcHVfdmJhc2VbMF0gKyBN VjY0eDYwX0NQVV9FUlJfQUREUl9MTykpOwo+ICsJICAgICAgIGlvcmVhZDMyKHBkYXRhLT5jcHVf dmJhc2VbMF0gKyBNVjY0eDYwX0NQVV9FUlJfQUREUl9MTykpOwo+ICAJcHJpbnRrKEtFUk5fRVJS ICJBZGRyZXNzIEhpZ2g6IDB4JTA4eFxuIiwKPiAtCSAgICAgICBpbl9sZTMyKHBkYXRhLT5jcHVf dmJhc2VbMF0gKyBNVjY0eDYwX0NQVV9FUlJfQUREUl9ISSkpOwo+ICsJICAgICAgIGlvcmVhZDMy KHBkYXRhLT5jcHVfdmJhc2VbMF0gKyBNVjY0eDYwX0NQVV9FUlJfQUREUl9ISSkpOwo+ICAJcHJp bnRrKEtFUk5fRVJSICJEYXRhIExvdzogMHglMDh4XG4iLAo+IC0JICAgICAgIGluX2xlMzIocGRh dGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9EQVRBX0xPKSk7Cj4gKwkgICAgICAg aW9yZWFkMzIocGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9EQVRBX0xPKSk7 Cj4gIAlwcmludGsoS0VSTl9FUlIgIkRhdGEgSGlnaDogMHglMDh4XG4iLAo+IC0JICAgICAgIGlu X2xlMzIocGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9EQVRBX0hJKSk7Cj4g KwkgICAgICAgaW9yZWFkMzIocGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9E QVRBX0hJKSk7Cj4gIAlwcmludGsoS0VSTl9FUlIgIlBhcml0eTogMHglMDh4XG4iLAo+IC0JICAg ICAgIGluX2xlMzIocGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9QQVJJVFkp KTsKPiAtCW91dF9sZTMyKHBkYXRhLT5jcHVfdmJhc2VbMV0gKyBNVjY0eDYwX0NQVV9FUlJfQ0FV U0UsIDApOwo+ICsJICAgICAgIGlvcmVhZDMyKHBkYXRhLT5jcHVfdmJhc2VbMV0gKyBNVjY0eDYw X0NQVV9FUlJfUEFSSVRZKSk7Cj4gKwlpb3dyaXRlMzIoMCwgcGRhdGEtPmNwdV92YmFzZVsxXSAr IE1WNjR4NjBfQ1BVX0VSUl9DQVVTRSk7Cj4gIAo+ICAJZWRhY19kZXZpY2VfaGFuZGxlX3VlKGVk YWNfZGV2LCAwLCAwLCBlZGFjX2Rldi0+Y3RsX25hbWUpOwo+ICB9Cj4gQEAgLTQyNiw3ICs0MjYs NyBAQCBzdGF0aWMgaXJxcmV0dXJuX3QgbXY2NHg2MF9jcHVfaXNyKGludCBpcnEsIHZvaWQgKmRl dl9pZCkKPiAgCXN0cnVjdCBtdjY0eDYwX2NwdV9wZGF0YSAqcGRhdGEgPSBlZGFjX2Rldi0+cHZ0 X2luZm87Cj4gIAl1MzIgY2F1c2U7Cj4gIAo+IC0JY2F1c2UgPSBpbl9sZTMyKHBkYXRhLT5jcHVf dmJhc2VbMV0gKyBNVjY0eDYwX0NQVV9FUlJfQ0FVU0UpICYKPiArCWNhdXNlID0gaW9yZWFkMzIo cGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9DQVVTRSkgJgo+ICAJICAgIE1W NjR4NjBfQ1BVX0NBVVNFX01BU0s7Cj4gIAlpZiAoIWNhdXNlKQo+ICAJCXJldHVybiBJUlFfTk9O RTsKPiBAQCAtNTE1LDkgKzUxNSw5IEBAIHN0YXRpYyBpbnQgbXY2NHg2MF9jcHVfZXJyX3Byb2Jl KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gIAl9Cj4gIAo+ICAJLyogc2V0dXAgQ1BV IGVyciByZWdpc3RlcnMgKi8KPiAtCW91dF9sZTMyKHBkYXRhLT5jcHVfdmJhc2VbMV0gKyBNVjY0 eDYwX0NQVV9FUlJfQ0FVU0UsIDApOwo+IC0Jb3V0X2xlMzIocGRhdGEtPmNwdV92YmFzZVsxXSAr IE1WNjR4NjBfQ1BVX0VSUl9NQVNLLCAwKTsKPiAtCW91dF9sZTMyKHBkYXRhLT5jcHVfdmJhc2Vb MV0gKyBNVjY0eDYwX0NQVV9FUlJfTUFTSywgMHgwMDAwMDBmZik7Cj4gKwlpb3dyaXRlMzIoMCwg cGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9DQVVTRSk7Cj4gKwlpb3dyaXRl MzIoMCwgcGRhdGEtPmNwdV92YmFzZVsxXSArIE1WNjR4NjBfQ1BVX0VSUl9NQVNLKTsKPiArCWlv d3JpdGUzMigweDAwMDAwMGZmLCBwZGF0YS0+Y3B1X3ZiYXNlWzFdICsgTVY2NHg2MF9DUFVfRVJS X01BU0spOwo+ICAKPiAgCWVkYWNfZGV2LT5tb2RfbmFtZSA9IEVEQUNfTU9EX1NUUjsKPiAgCWVk YWNfZGV2LT5jdGxfbmFtZSA9IHBkYXRhLT5uYW1lOwo+IEBAIC01OTYsMTMgKzU5NiwxMyBAQCBz dGF0aWMgdm9pZCBtdjY0eDYwX21jX2NoZWNrKHN0cnVjdCBtZW1fY3RsX2luZm8gKm1jaSkKPiAg CXUzMiBjb21wX2VjYzsKPiAgCXUzMiBzeW5kcm9tZTsKPiAgCj4gLQlyZWcgPSBpbl9sZTMyKHBk YXRhLT5tY192YmFzZSArIE1WNjRYNjBfU0RSQU1fRVJSX0FERFIpOwo+ICsJcmVnID0gaW9yZWFk MzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJBTV9FUlJfQUREUik7Cj4gIAlpZiAoIXJl ZykKPiAgCQlyZXR1cm47Cj4gIAo+ICAJZXJyX2FkZHIgPSByZWcgJiB+MHgzOwo+IC0Jc2RyYW1f ZWNjID0gaW5fbGUzMihwZGF0YS0+bWNfdmJhc2UgKyBNVjY0WDYwX1NEUkFNX0VSUl9FQ0NfUkNW RCk7Cj4gLQljb21wX2VjYyA9IGluX2xlMzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJB TV9FUlJfRUNDX0NBTEMpOwo+ICsJc2RyYW1fZWNjID0gaW9yZWFkMzIocGRhdGEtPm1jX3ZiYXNl ICsgTVY2NFg2MF9TRFJBTV9FUlJfRUNDX1JDVkQpOwo+ICsJY29tcF9lY2MgPSBpb3JlYWQzMihw ZGF0YS0+bWNfdmJhc2UgKyBNVjY0WDYwX1NEUkFNX0VSUl9FQ0NfQ0FMQyk7Cj4gIAlzeW5kcm9t ZSA9IHNkcmFtX2VjYyBeIGNvbXBfZWNjOwo+ICAKPiAgCS8qIGZpcnN0IGJpdCBjbGVhciBpbiBF Q0MgRXJyIFJlZywgMSBiaXQgZXJyb3IsIGNvcnJlY3RhYmxlIGJ5IEhXICovCj4gQEAgLTYyMCw3 ICs2MjAsNyBAQCBzdGF0aWMgdm9pZCBtdjY0eDYwX21jX2NoZWNrKHN0cnVjdCBtZW1fY3RsX2lu Zm8gKm1jaSkKPiAgCQkJCSAgICAgbWNpLT5jdGxfbmFtZSwgIiIpOwo+ICAKPiAgCS8qIGNsZWFy IHRoZSBlcnJvciAqLwo+IC0Jb3V0X2xlMzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJB TV9FUlJfQUREUiwgMCk7Cj4gKwlpb3dyaXRlMzIoMCwgcGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2 MF9TRFJBTV9FUlJfQUREUik7Cj4gIH0KPiAgCj4gIHN0YXRpYyBpcnFyZXR1cm5fdCBtdjY0eDYw X21jX2lzcihpbnQgaXJxLCB2b2lkICpkZXZfaWQpCj4gQEAgLTYyOSw3ICs2MjksNyBAQCBzdGF0 aWMgaXJxcmV0dXJuX3QgbXY2NHg2MF9tY19pc3IoaW50IGlycSwgdm9pZCAqZGV2X2lkKQo+ICAJ c3RydWN0IG12NjR4NjBfbWNfcGRhdGEgKnBkYXRhID0gbWNpLT5wdnRfaW5mbzsKPiAgCXUzMiBy ZWc7Cj4gIAo+IC0JcmVnID0gaW5fbGUzMihwZGF0YS0+bWNfdmJhc2UgKyBNVjY0WDYwX1NEUkFN X0VSUl9BRERSKTsKPiArCXJlZyA9IGlvcmVhZDMyKHBkYXRhLT5tY192YmFzZSArIE1WNjRYNjBf U0RSQU1fRVJSX0FERFIpOwo+ICAJaWYgKCFyZWcpCj4gIAkJcmV0dXJuIElSUV9OT05FOwo+ICAK PiBAQCAtNjY0LDcgKzY2NCw3IEBAIHN0YXRpYyB2b2lkIG12NjR4NjBfaW5pdF9jc3Jvd3Moc3Ry dWN0IG1lbV9jdGxfaW5mbyAqbWNpLAo+ICAKPiAgCWdldF90b3RhbF9tZW0ocGRhdGEpOwo+ICAK PiAtCWN0bCA9IGluX2xlMzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJBTV9DT05GSUcp Owo+ICsJY3RsID0gaW9yZWFkMzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJBTV9DT05G SUcpOwo+ICAKPiAgCWNzcm93ID0gbWNpLT5jc3Jvd3NbMF07Cj4gIAlkaW1tID0gY3Nyb3ctPmNo YW5uZWxzWzBdLT5kaW1tOwo+IEBAIC03NTMsNyArNzUzLDcgQEAgc3RhdGljIGludCBtdjY0eDYw X21jX2Vycl9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICAJCWdvdG8gZXJy Owo+ICAJfQo+ICAKPiAtCWN0bCA9IGluX2xlMzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2MF9T RFJBTV9DT05GSUcpOwo+ICsJY3RsID0gaW9yZWFkMzIocGRhdGEtPm1jX3ZiYXNlICsgTVY2NFg2 MF9TRFJBTV9DT05GSUcpOwo+ICAJaWYgKCEoY3RsICYgTVY2NFg2MF9TRFJBTV9FQ0MpKSB7Cj4g IAkJLyogTm9uLUVDQyBSQU0/ICovCj4gIAkJcHJpbnRrKEtFUk5fV0FSTklORyAiJXM6IE5vIEVD QyBESU1NcyBkaXNjb3ZlcmVkXG4iLCBfX2Z1bmNfXyk7Cj4gQEAgLTc3OSwxMCArNzc5LDEwIEBA IHN0YXRpYyBpbnQgbXY2NHg2MF9tY19lcnJfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAq cGRldikKPiAgCW12NjR4NjBfaW5pdF9jc3Jvd3MobWNpLCBwZGF0YSk7Cj4gIAo+ICAJLyogc2V0 dXAgTUMgcmVnaXN0ZXJzICovCj4gLQlvdXRfbGUzMihwZGF0YS0+bWNfdmJhc2UgKyBNVjY0WDYw X1NEUkFNX0VSUl9BRERSLCAwKTsKPiAtCWN0bCA9IGluX2xlMzIocGRhdGEtPm1jX3ZiYXNlICsg TVY2NFg2MF9TRFJBTV9FUlJfRUNDX0NOVEwpOwo+ICsJaW93cml0ZTMyKDAsIHBkYXRhLT5tY192 YmFzZSArIE1WNjRYNjBfU0RSQU1fRVJSX0FERFIpOwo+ICsJY3RsID0gaW9yZWFkMzIocGRhdGEt Pm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJBTV9FUlJfRUNDX0NOVEwpOwo+ICAJY3RsID0gKGN0bCAm IDB4ZmYwMGZmZmYpIHwgMHgxMDAwMDsKPiAtCW91dF9sZTMyKHBkYXRhLT5tY192YmFzZSArIE1W NjRYNjBfU0RSQU1fRVJSX0VDQ19DTlRMLCBjdGwpOwo+ICsJaW93cml0ZTMyKGN0bCwgcGRhdGEt Pm1jX3ZiYXNlICsgTVY2NFg2MF9TRFJBTV9FUlJfRUNDX0NOVEwpOwo+ICAKPiAgCXJlcyA9IGVk YWNfbWNfYWRkX21jKG1jaSk7Cj4gIAlpZiAocmVzKSB7Cj4gLS0gCj4gMi4xMS4wLjI0LmdlNjky MGNmCj4K