From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758468AbdEVKUQ (ORCPT ); Mon, 22 May 2017 06:20:16 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:33240 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751842AbdEVKUL (ORCPT ); Mon, 22 May 2017 06:20:11 -0400 Date: Mon, 22 May 2017 11:20:07 +0100 From: Lee Jones To: Andy Shevchenko Cc: linux-kernel@vger.kernel.org, Mika Westerberg Subject: Re: [PATCH v1] mfd: intel-lpss: Add Intel Cannonlake PCI IDs Message-ID: <20170522102007.2kqr4eivp2onzqqr@dell> References: <20170515082314.17010-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170515082314.17010-1-andriy.shevchenko@linux.intel.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 15 May 2017, Andy Shevchenko wrote: > Intel Cannonlake PCH has the same LPSS than Intel Kabylake. Add the new IDs > to the list of supported devices. > > Signed-off-by: Mika Westerberg > Signed-off-by: Andy Shevchenko > --- > drivers/mfd/intel-lpss-pci.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) Applied, thanks. > diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c > index 16ffeaeb1385..ad388bb056cd 100644 > --- a/drivers/mfd/intel-lpss-pci.c > +++ b/drivers/mfd/intel-lpss-pci.c > @@ -201,6 +201,19 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { > { PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_i2c_info }, > { PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_i2c_info }, > { PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info }, > + /* CNL-LP */ > + { PCI_VDEVICE(INTEL, 0x9da8), (kernel_ulong_t)&spt_uart_info }, > + { PCI_VDEVICE(INTEL, 0x9da9), (kernel_ulong_t)&spt_uart_info }, > + { PCI_VDEVICE(INTEL, 0x9daa), (kernel_ulong_t)&spt_info }, > + { PCI_VDEVICE(INTEL, 0x9dab), (kernel_ulong_t)&spt_info }, > + { PCI_VDEVICE(INTEL, 0x9dfb), (kernel_ulong_t)&spt_info }, > + { PCI_VDEVICE(INTEL, 0x9dc5), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0x9dc6), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0x9dc7), (kernel_ulong_t)&spt_uart_info }, > + { PCI_VDEVICE(INTEL, 0x9de8), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0x9de9), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0x9dea), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0x9deb), (kernel_ulong_t)&spt_i2c_info }, > /* SPT-H */ > { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info }, > { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info }, > @@ -219,6 +232,17 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { > { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info }, > { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info }, > { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info }, > + /* CNL-H */ > + { PCI_VDEVICE(INTEL, 0xa328), (kernel_ulong_t)&spt_uart_info }, > + { PCI_VDEVICE(INTEL, 0xa329), (kernel_ulong_t)&spt_uart_info }, > + { PCI_VDEVICE(INTEL, 0xa32a), (kernel_ulong_t)&spt_info }, > + { PCI_VDEVICE(INTEL, 0xa32b), (kernel_ulong_t)&spt_info }, > + { PCI_VDEVICE(INTEL, 0xa37b), (kernel_ulong_t)&spt_info }, > + { PCI_VDEVICE(INTEL, 0xa347), (kernel_ulong_t)&spt_uart_info }, > + { PCI_VDEVICE(INTEL, 0xa368), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0xa369), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0xa36a), (kernel_ulong_t)&spt_i2c_info }, > + { PCI_VDEVICE(INTEL, 0xa36b), (kernel_ulong_t)&spt_i2c_info }, > { } > }; > MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids); -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog