From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rob Clark Subject: [PATCH 1/3] ARM64: DT: add gpu for msm8916 Date: Thu, 25 May 2017 13:48:20 -0400 Message-ID: <20170525174822.27996-2-robdclark@gmail.com> References: <20170525174822.27996-1-robdclark@gmail.com> Return-path: Received: from mail-qk0-f193.google.com ([209.85.220.193]:34541 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S970030AbdEYRsd (ORCPT ); Thu, 25 May 2017 13:48:33 -0400 Received: by mail-qk0-f193.google.com with SMTP id u75so30932082qka.1 for ; Thu, 25 May 2017 10:48:33 -0700 (PDT) In-Reply-To: <20170525174822.27996-1-robdclark@gmail.com> Sender: linux-arm-msm-owner@vger.kernel.org List-Id: linux-arm-msm@vger.kernel.org To: linux-arm-msm@vger.kernel.org, Andy Gross Cc: Stanimir Varbanov , Rob Clark Signed-off-by: Rob Clark --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index ab30939..f9b8a28 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -698,6 +698,41 @@ #thermal-sensor-cells = <1>; }; + gpu_opp_table: opp_table { + compatible = "operating-points-v2"; + + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + opp@19200000 { + opp-hz = /bits/ 64 <19200000>; + }; + }; + + gpu@01c00000 { + compatible = "qcom,adreno-306.0", "qcom,adreno"; + reg = <0x01c00000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = <0 33 0>; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core", + "iface", + "mem", + "mem_iface", + "alt_mem_iface", + "gfx3d_clk"; + clocks = + <&gcc GCC_OXILI_GFX3D_CLK>, + <&gcc GCC_OXILI_AHB_CLK>, + <&gcc GCC_OXILI_GMEM_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_BIMC_GPU_CLK>, + <&gcc GFX3D_CLK_SRC>; + power-domains = <&gcc OXILI_GDSC>; + operating-points-v2 = <&gpu_opp_table>; + }; + mdss: mdss@1a00000 { compatible = "qcom,mdss"; reg = <0x1a00000 0x1000>, -- 2.9.4