From mboxrd@z Thu Jan  1 00:00:00 1970
From: Stephen Boyd <sboyd@codeaurora.org>
Subject: Re: [PATCH 1/3] ARM64: DT: add gpu for msm8916
Date: Tue, 30 May 2017 17:11:05 -0700
Message-ID: <20170531001105.GQ20170@codeaurora.org>
References: <20170525174822.27996-1-robdclark@gmail.com>
 <20170525174822.27996-2-robdclark@gmail.com>
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To: Rob Clark <robdclark@gmail.com>
Cc: linux-arm-msm@vger.kernel.org, Andy Gross <agross@codeaurora.org>, Stanimir Varbanov <stanimir.varbanov@linaro.org>

On 05/25, Rob Clark wrote:
> Signed-off-by: Rob Clark <robdclark@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/msm8916.dtsi | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index ab30939..f9b8a28 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -698,6 +698,41 @@
>  			#thermal-sensor-cells = <1>;
>  		};
>  
> +		gpu_opp_table: opp_table {
> +			compatible = "operating-points-v2";
> +
> +			opp@400000000 {

We recently changed the binding to have dash instead of at sign:

			opp-400000000 {

> +				opp-hz = /bits/ 64 <400000000>;
> +			};
> +			opp@19200000 {
> +				opp-hz = /bits/ 64 <19200000>;
> +			};
> +		};

This should be outside of soc node.

> +
> +		gpu@01c00000 {

Drop leading 0 on unit addresses please.

> +			compatible = "qcom,adreno-306.0", "qcom,adreno";
> +			reg = <0x01c00000 0x20000>;
> +			reg-names = "kgsl_3d0_reg_memory";
> +			interrupts = <0 33 0>;

Can we get an irq trigger type?

			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>

> +			interrupt-names = "kgsl_3d0_irq";
> +			clock-names =
> +			    "core",
> +			    "iface",
> +			    "mem",
> +			    "mem_iface",
> +			    "alt_mem_iface",
> +			    "gfx3d_clk";

It's still called gfx3d_clk? Too bad we couldn't get rid of that
last _clk one.

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