From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Burton Subject: [PATCH v4 3/7] dt-bindings: net: Document Intel pch_gbe binding Date: Mon, 5 Jun 2017 10:31:32 -0700 Message-ID: <20170605173136.10795-4-paul.burton@imgtec.com> References: <20170602234042.22782-1-paul.burton@imgtec.com> <20170605173136.10795-1-paul.burton@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain Cc: "David S . Miller" , , Eric Dumazet , Jarod Wilson , Tobias Klauser , Paul Burton , Mark Rutland , Rob Herring , To: Return-path: In-Reply-To: <20170605173136.10795-1-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: netdev.vger.kernel.org Introduce documentation for a device tree binding for the Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a PCIe device & thus largely auto-detectable, this binding will be used to provide the driver with the PHY reset GPIO. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Eric Dumazet Cc: Jarod Wilson Cc: Mark Rutland Cc: Rob Herring Cc: Tobias Klauser Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org Cc: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- Changes in v4: None Changes in v3: - New patch. Changes in v2: None Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt new file mode 100644 index 000000000000..5de479c26b04 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pch_gbe.txt @@ -0,0 +1,25 @@ +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) + +Required properties: +- compatible: Should be the PCI vendor & device ID, eg. "pci8086,8802". +- reg: Should be a PCI device number as specified by the PCI bus + binding to IEEE Std 1275-1994. +- phy-reset-gpios: Should be a GPIO list containing a single GPIO that + resets the attached PHY when active. + +Example: + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; -- 2.13.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Burton Subject: [PATCH v4 3/7] dt-bindings: net: Document Intel pch_gbe binding Date: Mon, 5 Jun 2017 10:31:32 -0700 Message-ID: <20170605173136.10795-4-paul.burton@imgtec.com> References: <20170602234042.22782-1-paul.burton@imgtec.com> <20170605173136.10795-1-paul.burton@imgtec.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: In-Reply-To: <20170605173136.10795-1-paul.burton-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: "David S . Miller" , linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org, Eric Dumazet , Jarod Wilson , Tobias Klauser , Paul Burton , Mark Rutland , Rob Herring , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Introduce documentation for a device tree binding for the Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a PCIe device & thus largely auto-detectable, this binding will be used to provide the driver with the PHY reset GPIO. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Eric Dumazet Cc: Jarod Wilson Cc: Mark Rutland Cc: Rob Herring Cc: Tobias Klauser Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org Cc: netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org --- Changes in v4: None Changes in v3: - New patch. Changes in v2: None Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt new file mode 100644 index 000000000000..5de479c26b04 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pch_gbe.txt @@ -0,0 +1,25 @@ +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) + +Required properties: +- compatible: Should be the PCI vendor & device ID, eg. "pci8086,8802". +- reg: Should be a PCI device number as specified by the PCI bus + binding to IEEE Std 1275-1994. +- phy-reset-gpios: Should be a GPIO list containing a single GPIO that + resets the attached PHY when active. + +Example: + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; -- 2.13.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jun 2017 19:33:39 +0200 (CEST) Received: from mailapp01.imgtec.com ([195.59.15.196]:59781 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23992078AbdFERdJNyOTR (ORCPT ); Mon, 5 Jun 2017 19:33:09 +0200 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 148C6CA4BB17E; Mon, 5 Jun 2017 18:32:56 +0100 (IST) Received: from localhost (10.20.1.33) by hhmail02.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 5 Jun 2017 18:32:59 +0100 From: Paul Burton To: CC: "David S . Miller" , , Eric Dumazet , Jarod Wilson , Tobias Klauser , Paul Burton , Mark Rutland , Rob Herring , Subject: [PATCH v4 3/7] dt-bindings: net: Document Intel pch_gbe binding Date: Mon, 5 Jun 2017 10:31:32 -0700 Message-ID: <20170605173136.10795-4-paul.burton@imgtec.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170605173136.10795-1-paul.burton@imgtec.com> References: <20170602234042.22782-1-paul.burton@imgtec.com> <20170605173136.10795-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.20.1.33] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 58217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.burton@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips Introduce documentation for a device tree binding for the Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a PCIe device & thus largely auto-detectable, this binding will be used to provide the driver with the PHY reset GPIO. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Eric Dumazet Cc: Jarod Wilson Cc: Mark Rutland Cc: Rob Herring Cc: Tobias Klauser Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in v4: None Changes in v3: - New patch. Changes in v2: None Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt new file mode 100644 index 000000000000..5de479c26b04 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pch_gbe.txt @@ -0,0 +1,25 @@ +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) + +Required properties: +- compatible: Should be the PCI vendor & device ID, eg. "pci8086,8802". +- reg: Should be a PCI device number as specified by the PCI bus + binding to IEEE Std 1275-1994. +- phy-reset-gpios: Should be a GPIO list containing a single GPIO that + resets the attached PHY when active. + +Example: + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; -- 2.13.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:59781 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23992078AbdFERdJNyOTR (ORCPT ); Mon, 5 Jun 2017 19:33:09 +0200 From: Paul Burton Subject: [PATCH v4 3/7] dt-bindings: net: Document Intel pch_gbe binding Date: Mon, 5 Jun 2017 10:31:32 -0700 Message-ID: <20170605173136.10795-4-paul.burton@imgtec.com> In-Reply-To: <20170605173136.10795-1-paul.burton@imgtec.com> References: <20170602234042.22782-1-paul.burton@imgtec.com> <20170605173136.10795-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: netdev@vger.kernel.org Cc: "David S . Miller" , linux-mips@linux-mips.org, Eric Dumazet , Jarod Wilson , Tobias Klauser , Paul Burton , Mark Rutland , Rob Herring , devicetree@vger.kernel.org Message-ID: <20170605173132.enxu1FH5TaD19IBCNx2nZt7COubWsGC-xOAxwLj3qfU@z> Introduce documentation for a device tree binding for the Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) device. Although this is a PCIe device & thus largely auto-detectable, this binding will be used to provide the driver with the PHY reset GPIO. Signed-off-by: Paul Burton Cc: David S. Miller Cc: Eric Dumazet Cc: Jarod Wilson Cc: Mark Rutland Cc: Rob Herring Cc: Tobias Klauser Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org --- Changes in v4: None Changes in v3: - New patch. Changes in v2: None Documentation/devicetree/bindings/net/pch_gbe.txt | 25 +++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pch_gbe.txt diff --git a/Documentation/devicetree/bindings/net/pch_gbe.txt b/Documentation/devicetree/bindings/net/pch_gbe.txt new file mode 100644 index 000000000000..5de479c26b04 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pch_gbe.txt @@ -0,0 +1,25 @@ +Intel Platform Controller Hub (PCH) GigaBit Ethernet (GBE) + +Required properties: +- compatible: Should be the PCI vendor & device ID, eg. "pci8086,8802". +- reg: Should be a PCI device number as specified by the PCI bus + binding to IEEE Std 1275-1994. +- phy-reset-gpios: Should be a GPIO list containing a single GPIO that + resets the attached PHY when active. + +Example: + + eg20t_mac@2,0,1 { + compatible = "pci8086,8802"; + reg = <0x00020100 0 0 0 0>; + phy-reset-gpios = <&eg20t_gpio 6 + GPIO_ACTIVE_LOW>; + }; + + eg20t_gpio: eg20t_gpio@2,0,2 { + compatible = "pci8086,8803"; + reg = <0x00020200 0 0 0 0>; + + gpio-controller; + #gpio-cells = <2>; + }; -- 2.13.0