From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751801AbdFFQCn (ORCPT ); Tue, 6 Jun 2017 12:02:43 -0400 Received: from bombadil.infradead.org ([65.50.211.133]:57939 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751388AbdFFQCk (ORCPT ); Tue, 6 Jun 2017 12:02:40 -0400 Date: Tue, 6 Jun 2017 18:02:28 +0200 From: Peter Zijlstra To: Paolo Bonzini Cc: "Paul E. McKenney" , linux-kernel@vger.kernel.org, mingo@kernel.org, jiangshanlai@gmail.com, dipankar@in.ibm.com, akpm@linux-foundation.org, mathieu.desnoyers@efficios.com, josh@joshtriplett.org, tglx@linutronix.de, rostedt@goodmis.org, dhowells@redhat.com, edumazet@google.com, fweisbec@gmail.com, oleg@redhat.com, kvm@vger.kernel.org, Linus Torvalds Subject: Re: [PATCH RFC tip/core/rcu 1/2] srcu: Allow use of Tiny/Tree SRCU from both process and interrupt context Message-ID: <20170606160228.6y5eag64sk4u43cg@hirez.programming.kicks-ass.net> References: <20170605220919.GA27820@linux.vnet.ibm.com> <1496700591-30177-1-git-send-email-paulmck@linux.vnet.ibm.com> <20170606105343.ibhzrk6jwhmoja5t@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 06, 2017 at 03:08:50PM +0200, Paolo Bonzini wrote: > > > On 06/06/2017 12:53, Peter Zijlstra wrote: > > On Mon, Jun 05, 2017 at 03:09:50PM -0700, Paul E. McKenney wrote: > >> There would be a slowdown if 1) fast this_cpu_inc is not available and > >> cannot be implemented (this usually means that atomic_inc has implicit > >> memory barriers), > > > > I don't get this. > > > > How is per-cpu crud related to being strongly ordered? > > > > this_cpu_ has 3 forms: > > > > x86: single instruction > > arm64,s390: preempt_disable()+atomic_op > > generic: local_irq_save()+normal_op > > > > Only s390 is TSO, arm64 is very much a weak arch. > > Right, and thus arm64 can implement a fast this_cpu_inc using LL/SC. > s390 cannot because its atomic_inc has implicit memory barriers. I'm not sure the ordering makes a useful differentiator between a fast and non-fast this_cpu implementation. For TSO archs making their atomic primitives fully ordered isn't _that_ much of a burden over their normal ordering requirements. And LL/SC archs can have very slow (weak) atomics (PPC for example). (Now theoretically a TSO arch could have weak(er) atomics, but I'm not aware of any that do this). I realize we're splitting hairs and slightly off topic :-)