From mboxrd@z Thu Jan 1 00:00:00 1970 From: Icenowy Zheng Date: Wed, 7 Jun 2017 08:47:19 +0800 Subject: [U-Boot] [RFC PATCH 6/8] sunxi: add multi-cluster CPU PRCM register definition In-Reply-To: <20170607004721.24194-1-icenowy@aosc.io> References: <20170607004721.24194-1-icenowy@aosc.io> Message-ID: <20170607004721.24194-7-icenowy@aosc.io> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de A83T come with two clusters of CPU, for each cluster 1 the new registers are in the reserved spaces after the original cluster 0. Make the registers to have an array with length 2 (2 clusters), and change the current code to reference only cluster 0 registers. Signed-off-by: Icenowy Zheng --- arch/arm/cpu/armv7/sunxi/psci.c | 2 +- arch/arm/include/asm/arch-sunxi/prcm.h | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index b3a34de1aa..8caef6a85f 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -144,7 +144,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) struct sunxi_prcm_reg *prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; - sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, + sunxi_power_switch(&prcm->cpu_pwr_clamp[0][cpu], &prcm->cpu_pwroff[0], on, cpu); } #endif /* CONFIG_MACH_SUN7I */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index ae3880b13b..c2a6e39ffc 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -220,16 +220,16 @@ struct __packed sunxi_prcm_reg { u8 res5[0x3c]; /* 0x0b4 */ u32 clk_outd; /* 0x0f0 */ u8 res6[0xc]; /* 0x0f4 */ - u32 cpu_pwroff; /* 0x100 */ - u8 res7[0xc]; /* 0x104 */ + u32 cpu_pwroff[2]; /* 0x100 */ + u8 res7[0x8]; /* 0x108 */ u32 vdd_sys_pwroff; /* 0x110 */ u8 res8[0x4]; /* 0x114 */ u32 gpu_pwroff; /* 0x118 */ u8 res9[0x4]; /* 0x11c */ u32 vdd_pwr_reset; /* 0x120 */ u8 res10[0x1c]; /* 0x124 */ - u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */ - u8 res11[0x30]; /* 0x150 */ + u32 cpu_pwr_clamp[2][4];/* 0x140 but first one is actually unused */ + u8 res11[0x20]; /* 0x160 */ u32 dram_pwr; /* 0x180 */ u8 res12[0xc]; /* 0x184 */ u32 dram_tst; /* 0x190 */ -- 2.12.2