All of lore.kernel.org
 help / color / mirror / Atom feed
From: kbuild test robot <lkp@intel.com>
Cc: Ander Conselvan De Oliveira
	<ander.conselvan.de.oliveira@intel.com>,
	intel-gfx@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	kbuild-all@01.org, Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH] drm/i915/cnl: Introduce initial Cannonlake Workarounds.
Date: Thu, 8 Jun 2017 04:47:05 +0800	[thread overview]
Message-ID: <201706080413.odQ9G5CD%fengguang.wu@intel.com> (raw)
In-Reply-To: <1496782407-27273-1-git-send-email-rodrigo.vivi@intel.com>

[-- Attachment #1: Type: text/plain, Size: 3884 bytes --]

Hi Rodrigo,

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.12-rc4 next-20170607]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Rodrigo-Vivi/drm-i915-cnl-Introduce-initial-Cannonlake-Workarounds/20170608-041443
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-x014-201723 (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/gpu//drm/i915/intel_pm.c: In function 'cannonlake_init_clock_gating':
>> drivers/gpu//drm/i915/intel_pm.c:8298:6: error: implicit declaration of function 'IS_CNL_REVID' [-Werror=implicit-function-declaration]
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
         ^~~~~~~~~~~~
>> drivers/gpu//drm/i915/intel_pm.c:8298:29: error: 'CNL_REVID_A0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                ^~~~~~~~~~~~
   drivers/gpu//drm/i915/intel_pm.c:8298:29: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu//drm/i915/intel_pm.c:8298:43: error: 'CNL_REVID_B0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
                                              ^~~~~~~~~~~~
   drivers/gpu//drm/i915/intel_pm.c: In function 'intel_init_clock_gating_hooks':
>> drivers/gpu//drm/i915/intel_pm.c:8783:6: error: implicit declaration of function 'IS_CANNONLAKE' [-Werror=implicit-function-declaration]
     if (IS_CANNONLAKE(dev_priv))
         ^~~~~~~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu//drm/i915/i915_gem_gtt.c: In function 'gtt_write_workarounds':
>> drivers/gpu//drm/i915/i915_gem_gtt.c:1892:35: error: implicit declaration of function 'IS_GEN10' [-Werror=implicit-function-declaration]
     else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
                                      ^~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu//drm/i915/intel_engine_cs.c: In function 'cnl_init_workarounds':
>> drivers/gpu//drm/i915/intel_engine_cs.c:1094:6: error: implicit declaration of function 'IS_CNL_REVID' [-Werror=implicit-function-declaration]
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
         ^~~~~~~~~~~~
>> drivers/gpu//drm/i915/intel_engine_cs.c:1094:29: error: 'CNL_REVID_A0' undeclared (first use in this function)
     if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) {
                                ^~~~~~~~~~~~
   drivers/gpu//drm/i915/intel_engine_cs.c:1094:29: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu//drm/i915/intel_engine_cs.c: In function 'init_workarounds_ring':
>> drivers/gpu//drm/i915/intel_engine_cs.c:1189:11: error: implicit declaration of function 'IS_CANNONLAKE' [-Werror=implicit-function-declaration]
     else if (IS_CANNONLAKE(dev_priv))
              ^~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +/IS_CNL_REVID +8298 drivers/gpu//drm/i915/intel_pm.c

  8292	
  8293		/* WaFbcNukeOnHostModify:cnl */
  8294		I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
  8295			   ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
  8296	
  8297		/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
> 8298		if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
  8299			I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
  8300				   SARBUNIT_CLKGATE_DIS);
  8301	}

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 23065 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2017-06-07 20:47 UTC|newest]

Thread overview: 182+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-06 19:14 [PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH Rodrigo Vivi
2017-04-06 19:14 ` [PATCH 02/67] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH Rodrigo Vivi
2017-04-12 17:41   ` Srivatsa, Anusha
2017-04-06 19:14 ` [PATCH 03/67] drm/i915/cnp: Get/set proper Raw clock frequency on CNP Rodrigo Vivi
2017-04-07 13:45   ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 04/67] drm/i915/cnp: Add Backlight support to CNP PCH Rodrigo Vivi
2017-04-07 14:16   ` Ville Syrjälä
2017-04-11  8:33     ` Jani Nikula
2017-04-06 19:15 ` [PATCH 05/67] drm/i915/cnp: add CNP gmbus support Rodrigo Vivi
2017-04-07  0:54   ` [PATCH] " Rodrigo Vivi
2017-04-07 18:46     ` kbuild test robot
2017-04-17 21:13   ` [PATCH 05/67] " Srivatsa, Anusha
2017-04-06 19:15 ` [PATCH 06/67] drm/i915/cnp: Panel Power sequence changes for CNP PCH Rodrigo Vivi
2017-04-07 14:48   ` Ville Syrjälä
2017-04-13 23:48     ` Vivi, Rodrigo
2017-05-23 22:16       ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 07/67] drm/i915/cnl: Introduce Cannonlake platform defition Rodrigo Vivi
2017-05-04  8:55   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 08/67] drm/i915/cnl: Cannonlake uses CNP PCH Rodrigo Vivi
2017-05-03 23:46   ` Srivatsa, Anusha
2017-04-06 19:15 ` [PATCH 09/67] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus Rodrigo Vivi
2017-06-02 16:07   ` Clint Taylor
2017-04-06 19:15 ` [PATCH 10/67] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 11/67] drm/i915/cnl: add IS_CNL_REVID macro Rodrigo Vivi
2017-05-11 15:37   ` Jim Bride
2017-04-06 19:15 ` [PATCH 12/67] drm/i915/cnl: Introduce initial Cannonlake Workarounds Rodrigo Vivi
2017-04-28 17:11   ` Oscar Mateo
2017-05-10 11:17   ` Ander Conselvan De Oliveira
2017-06-06 20:53     ` [PATCH] " Rodrigo Vivi
2017-06-07 20:47       ` kbuild test robot [this message]
2017-06-07 21:09       ` kbuild test robot
2017-04-06 19:15 ` [PATCH 13/67] drm/i915/cnl: Add WaDisableReplayBufferBankArbitrationOptimization Rodrigo Vivi
2017-06-08 16:54   ` Mika Kuoppala
2017-06-08 17:09     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 14/67] drm/i915/cnl: WaDisableEnhancedSBEVertexCaching Rodrigo Vivi
2017-06-08 17:07   ` Mika Kuoppala
2017-04-06 19:15 ` [PATCH 15/67] drm/i915/cnl: Apply large line width optimization Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 16/67] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe Rodrigo Vivi
2017-05-04  9:10   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 17/67] drm/i915/cnl: CNL has an increased DDB size Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 18/67] drm/i915/cnl: Add initial gen10 golden states Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 19/67] drm/i915/cnl: Configure EU slice power gating Rodrigo Vivi
2017-06-02 11:27   ` Joonas Lahtinen
2017-04-06 19:15 ` [PATCH 20/67] drm/i915/cnl: Cannonlake has same MOCS table than Skylake Rodrigo Vivi
2017-06-02 11:20   ` Joonas Lahtinen
2017-04-06 19:15 ` [PATCH 21/67] drm/i915/cnl: Update the context size Rodrigo Vivi
2017-04-06 19:46   ` Chris Wilson
2017-04-06 21:53   ` Daniele Ceraolo Spurio
2017-04-06 21:56     ` Ben Widawsky
2017-04-06 19:15 ` [PATCH 22/67] drm/i915/cnl: Add RT cache flush pipe control w/a Rodrigo Vivi
2017-06-02 10:01   ` Tvrtko Ursulin
2017-06-05 17:17     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 23/67] drm/i915/gen10: Set value of Indirect Context Offset for gen10 Rodrigo Vivi
2017-06-02  9:50   ` Tvrtko Ursulin
2017-06-05 17:11     ` Vivi, Rodrigo
2017-06-06  6:48       ` Tvrtko Ursulin
2017-06-06 15:18         ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 24/67] drm/i915/cnl: Add force wake " Rodrigo Vivi
2017-06-08 14:58   ` Joonas Lahtinen
2017-04-06 19:15 ` [PATCH 25/67] drm/i915/cnl: Inherit RPS stuff from previous platforms Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 26/67] drm/i915/cnl: Add power wells for CNL Rodrigo Vivi
2017-06-05 15:55   ` Imre Deak
2017-06-05 16:42     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 27/67] drm/i915/cnl: Also need power well sanitize Rodrigo Vivi
2017-04-13 14:44   ` Imre Deak
2017-04-13 16:03     ` Vivi, Rodrigo
2017-06-05 15:56   ` Imre Deak
2017-04-06 19:15 ` [PATCH 28/67] drm/i915/cnl: Implement .get_display_clock_speed() for CNL Rodrigo Vivi
2017-06-02 18:06   ` Imre Deak
2017-06-05 17:59     ` Vivi, Rodrigo
2017-06-05 18:04       ` Ville Syrjälä
2017-06-05 18:21         ` Imre Deak
2017-06-05 18:28           ` Vivi, Rodrigo
2017-06-05 20:07             ` Imre Deak
2017-06-06 21:56               ` Rodrigo Vivi
2017-06-07 10:59                 ` Ville Syrjälä
2017-06-07 11:09                   ` Ville Syrjälä
2017-06-07 14:22                     ` Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 29/67] drm/i915/cnl: Implement .set_cdclk() " Rodrigo Vivi
2017-06-05 13:11   ` Imre Deak
2017-04-06 19:15 ` [PATCH 30/67] drm/i915/cnl: Implement CNL display init/unit sequence Rodrigo Vivi
2017-04-13 16:13   ` [PATCH] " Rodrigo Vivi
2017-06-05 15:07     ` Imre Deak
2017-06-05 16:38       ` Vivi, Rodrigo
2017-06-05 16:58         ` Imre Deak
2017-04-06 19:15 ` [PATCH 31/67] drm/i915/cnl: Allow dynamic cdclk changes on CNL Rodrigo Vivi
2017-06-05 15:22   ` Imre Deak
2017-06-05 16:41     ` Vivi, Rodrigo
2017-06-05 16:55       ` Ville Syrjälä
2017-06-05 17:04         ` Pandiyan, Dhinakaran
2017-06-06 15:24           ` Rodrigo Vivi
2017-06-06 17:39             ` Pandiyan, Dhinakaran
2017-06-06 18:09               ` Rodrigo Vivi
2017-06-06 18:12                 ` Rodrigo Vivi
2017-06-06 21:48                   ` Pandiyan, Dhinakaran
2017-06-06 21:57                     ` Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 32/67] drm/i915/cnl: DDI - PLL mapping Rodrigo Vivi
2017-04-07 21:12   ` Paulo Zanoni
2017-05-04 12:35     ` Ander Conselvan De Oliveira
2017-05-04 12:44       ` Ville Syrjälä
2017-05-04 13:02         ` Maarten Lankhorst
2017-05-04 13:11           ` Ville Syrjälä
2017-05-23 19:42             ` Vivi, Rodrigo
2017-05-04 12:55   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 33/67] drm/i915: Configure DPLL's for Cannonlake Rodrigo Vivi
2017-05-04 13:16   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 34/67] drm/i915/cnl: Initialize PLLs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 35/67] drm/i915/cnl: Enable wrpll computation for CNL Rodrigo Vivi
2017-06-08 23:03   ` [PATCH] " Rodrigo Vivi
2017-06-08 23:24     ` Clint Taylor
2017-04-06 19:15 ` [PATCH 36/67] drm/i915: Add MMIO helper for 6 ports with different offsets Rodrigo Vivi
2017-05-17 19:20   ` Manasi Navare
2017-05-23 19:16     ` Rodrigo Vivi
2017-06-05 18:45     ` Manasi Navare
2017-04-06 19:15 ` [PATCH 37/67] drm/i915/cnl: Add registers related to voltage swing sequences Rodrigo Vivi
2017-05-18  0:59   ` Manasi Navare
2017-05-23 19:18     ` Vivi, Rodrigo
2017-06-05 18:47     ` Manasi Navare
2017-06-05 20:45       ` [PATCH] " Rodrigo Vivi
2017-06-05 20:46       ` Rodrigo Vivi
2017-06-06  0:03         ` Manasi Navare
2017-06-05 20:51       ` [PATCH] drm/i915/cnl: Implement voltage swing sequence Rodrigo Vivi
2017-06-05 20:53       ` Rodrigo Vivi
2017-06-06  0:00         ` Manasi Navare
2017-04-06 19:15 ` [PATCH 38/67] drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake Rodrigo Vivi
2017-05-18  1:01   ` Manasi Navare
2017-04-06 19:15 ` [PATCH 39/67] drm/i915/cnl: Implement voltage swing sequence Rodrigo Vivi
2017-05-18  1:13   ` Manasi Navare
2017-05-23 19:19     ` Vivi, Rodrigo
2017-04-06 19:15 ` [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence Rodrigo Vivi
2017-04-24 18:53   ` Ville Syrjälä
2017-05-18  1:17   ` Manasi Navare
2017-04-06 19:15 ` [PATCH 41/67] drm/i915/cnl: Add slice and subslice information to debugfs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 42/67] drm/i915/DMC/CNL: Load DMC on CNL Rodrigo Vivi
2017-05-22 10:43   ` Animesh Manna
2017-04-06 19:15 ` [PATCH 43/67] drm/i915: Use HAS_CSR instead of gen number on DMC load Rodrigo Vivi
2017-05-22 10:46   ` Animesh Manna
2017-04-06 19:15 ` [PATCH 44/67] drm/i915/cnl: DC3 to DC5 counters available on CNL Rodrigo Vivi
2017-05-22 12:55   ` Animesh Manna
2017-04-06 19:15 ` [PATCH 45/67] drm/i915/cnl: Add max allowed Cannonlake DC Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 46/67] drm/i915/cnl: Add allowed DP rates for Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 47/67] drm/i915/cnl: Dump the right pll registers when dumping pipe config Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 48/67] drm/i915/cnl: Get DDI clock based on PLLs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 49/67] drm/i915/cnl: Avoid old DDI translation functions on Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 50/67] drm/i915/gen10+: use the SKL code for reading WM latencies Rodrigo Vivi
2017-04-24 18:22   ` Ville Syrjälä
2017-04-24 19:10     ` Paulo Zanoni
2017-04-24 20:04       ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 51/67] drm/i915/cnl: Enable SAGV for Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 52/67] drm/i915/gen10: fix the gen 10 SAGV block time Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 53/67] drm/i915/cnl: don't apply the GEN9/CNL:A WM WAs to CNL:B+ Rodrigo Vivi
2017-05-24  8:40   ` Mahesh Kumar
2017-04-06 19:15 ` [PATCH 54/67] drm/i915/gen10: fix WM latency printing Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 55/67] drm/i915/gen10: implement gen 10 watermarks calculations Rodrigo Vivi
2017-05-29  8:25   ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 56/67] drm/i915/cnl: Reuse skl_wm_get_hw_state on Cannonlake Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 57/67] x86/gpu: CNL uses the same GMS values as SKL Rodrigo Vivi
2017-04-06 19:39   ` [PATCH] " Rodrigo Vivi
2017-04-07 19:21     ` kbuild test robot
2017-04-07 19:21       ` Paulo Zanoni
2017-04-13  1:33         ` [kbuild-all] " Ye Xiaolong
2017-04-07 22:07     ` Thomas Gleixner
2017-04-06 19:15 ` [PATCH 58/67] drm/i915/cnl: Cannonlake color init Rodrigo Vivi
2017-04-24 17:57   ` Ville Syrjälä
2017-04-25  5:29     ` Vivi, Rodrigo
2017-04-25  7:08       ` Ander Conselvan De Oliveira
2017-04-06 19:15 ` [PATCH 59/67] drm/i915/cnl: Fix Cannonlake scaler mode programing Rodrigo Vivi
2017-04-24 18:11   ` Ville Syrjälä
2017-04-06 19:15 ` [PATCH 60/67] drm/i915/cnl: Enable fifo underrun for Cannonlake Rodrigo Vivi
2017-04-07  8:16   ` Mika Kahola
2017-04-06 19:15 ` [PATCH 61/67] drm/i915/cnl: Setup PAT Index Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 62/67] drm/i915/cnl: Add support slice/subslice/eu configs Rodrigo Vivi
2017-04-06 19:15 ` [PATCH 63/67] drm/i915/cnl: Avoid ioremap_wc on Cannonlake as well Rodrigo Vivi
2017-04-06 19:16 ` [PATCH 64/67] drm/i915/cnl: WaThrottleEUPerfToAvoidTDBackPressure:cnl(pre-prod) Rodrigo Vivi
2017-09-06 21:55   ` Oscar Mateo
2017-04-06 19:16 ` [PATCH 65/67] drm/i915/cnl: Enable Audio Pin Buffer Rodrigo Vivi
2017-04-06 19:16 ` [PATCH 66/67] drm/i915/cnl: LSPCON support is gen9+ Rodrigo Vivi
2017-04-07  5:54   ` Sharma, Shashank
2017-04-06 19:16 ` [PATCH 67/67] drm/i915/cnl: Adjust min pixel rate Rodrigo Vivi
2017-04-06 20:12 ` ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev2) Patchwork
2017-04-07  1:13 ` ✗ Fi.CI.BAT: warning for series starting with [01/67] drm/i915/cnp: Introduce Cannonpoint PCH. (rev3) Patchwork
2017-04-13 17:53 ` [PATCH 01/67] drm/i915/cnp: Introduce Cannonpoint PCH Srivatsa, Anusha

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=201706080413.odQ9G5CD%fengguang.wu@intel.com \
    --to=lkp@intel.com \
    --cc=ander.conselvan.de.oliveira@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=kbuild-all@01.org \
    --cc=mika.kuoppala@intel.com \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.