From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751927AbdF1QJ1 (ORCPT ); Wed, 28 Jun 2017 12:09:27 -0400 Received: from mail.skyhub.de ([5.9.137.197]:38650 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751512AbdF1QJU (ORCPT ); Wed, 28 Jun 2017 12:09:20 -0400 Date: Wed, 28 Jun 2017 18:08:51 +0200 From: Borislav Petkov To: =?utf-8?B?SsOpcsOpbXk=?= Lefaure Cc: Mauro Carvalho Chehab , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] edac, i5000, i5400: fix definition of nrecmemb register Message-ID: <20170628160851.5iuba4olrogfajwl@pd.tnic> References: <20170612174759.7649-1-jeremy.lefaure@lse.epita.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170612174759.7649-1-jeremy.lefaure@lse.epita.fr> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jun 12, 2017 at 01:47:58PM -0400, Jérémy Lefaure wrote: > In i5000 and i5400 edac drivers, the register nrecmemb is defined as a > 16 bits value which result in wrong shifts in the code: > CHECK drivers/edac/i5000_edac.c > drivers/edac/i5000_edac.c:485:15: warning: right shift by bigger than > source value > drivers/edac/i5000_edac.c:580:23: warning: right shift by bigger than > source value > CC drivers/edac/i5000_edac.o > CHECK drivers/edac/i5400_edac.c > drivers/edac/i5400_edac.c:391:36: warning: right shift by bigger than > source value > drivers/edac/i5400_edac.c:401:37: warning: right shift by bigger than > source value > CC drivers/edac/i5400_edac.o > > In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21), > this register is a 32 bits register. A u32 value for the register fixes > the wrong shifts warnings and matches the datasheet. > > This patch also fixes the mask to access to the CAS bits [16 to 28] in > the i5000 edac driver. > > [1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf Well, the CAS field length here is [27:16], see below. > [2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf Here it is [28:16]. > Signed-off-by: Jérémy Lefaure > --- > > I have found this error thanks to the sparse tool. Please note that this patch > hasn't been tested on real hardware. > > > drivers/edac/i5000_edac.c | 6 +++--- > drivers/edac/i5400_edac.c | 4 ++-- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c > index f683919981b0..c79016ade51e 100644 > --- a/drivers/edac/i5000_edac.c > +++ b/drivers/edac/i5000_edac.c > @@ -227,7 +227,7 @@ > #define NREC_RDWR(x) (((x)>>11) & 1) > #define NREC_RANK(x) (((x)>>8) & 0x7) > #define NRECMEMB 0xC0 > -#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF) > +#define NREC_CAS(x) (((x)>>16) & 0x1FFF) That is still incorrect. According to the 5000? datasheet above, NRECMEMB has the CAS field in bits [27:16]. That's 12 bits, so the mask should be 0xFFF. IOW, #define NREC_CAS(x) (((x)>>16) & 0xFFF) The 0x1FFF mask is correct for the 5400 driver because the CAS field there is [28:16]. The fact that no one caught this by now goes to show how many people are actually using this thing. :-\ -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: edac, i5000, i5400: fix definition of nrecmemb register From: Borislav Petkov Message-Id: <20170628160851.5iuba4olrogfajwl@pd.tnic> Date: Wed, 28 Jun 2017 18:08:51 +0200 To: =?utf-8?B?SsOpcsOpbXk=?= Lefaure Cc: Mauro Carvalho Chehab , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: T24gTW9uLCBKdW4gMTIsIDIwMTcgYXQgMDE6NDc6NThQTSAtMDQwMCwgSsOpcsOpbXkgTGVmYXVy ZSB3cm90ZToKPiBJbiBpNTAwMCBhbmQgaTU0MDAgZWRhYyBkcml2ZXJzLCB0aGUgcmVnaXN0ZXIg bnJlY21lbWIgaXMgZGVmaW5lZCBhcyBhCj4gMTYgYml0cyB2YWx1ZSB3aGljaCByZXN1bHQgaW4g d3Jvbmcgc2hpZnRzIGluIHRoZSBjb2RlOgo+ICAgQ0hFQ0sgICBkcml2ZXJzL2VkYWMvaTUwMDBf ZWRhYy5jCj4gZHJpdmVycy9lZGFjL2k1MDAwX2VkYWMuYzo0ODU6MTU6IHdhcm5pbmc6IHJpZ2h0 IHNoaWZ0IGJ5IGJpZ2dlciB0aGFuCj4gc291cmNlIHZhbHVlCj4gZHJpdmVycy9lZGFjL2k1MDAw X2VkYWMuYzo1ODA6MjM6IHdhcm5pbmc6IHJpZ2h0IHNoaWZ0IGJ5IGJpZ2dlciB0aGFuCj4gc291 cmNlIHZhbHVlCj4gICBDQyAgICAgIGRyaXZlcnMvZWRhYy9pNTAwMF9lZGFjLm8KPiAgIENIRUNL ICAgZHJpdmVycy9lZGFjL2k1NDAwX2VkYWMuYwo+IGRyaXZlcnMvZWRhYy9pNTQwMF9lZGFjLmM6 MzkxOjM2OiB3YXJuaW5nOiByaWdodCBzaGlmdCBieSBiaWdnZXIgdGhhbgo+IHNvdXJjZSB2YWx1 ZQo+IGRyaXZlcnMvZWRhYy9pNTQwMF9lZGFjLmM6NDAxOjM3OiB3YXJuaW5nOiByaWdodCBzaGlm dCBieSBiaWdnZXIgdGhhbgo+IHNvdXJjZSB2YWx1ZQo+ICAgQ0MgICAgICBkcml2ZXJzL2VkYWMv aTU0MDBfZWRhYy5vCj4gCj4gSW4gdGhlIGRhdGFzaGVldHMgKFsxXSwgc2VjdGlvbiAzLjkuMjIu MjAgYW5kIFsyXSwgc2VjdGlvbiAzLjkuMjIuMjEpLAo+IHRoaXMgcmVnaXN0ZXIgaXMgYSAzMiBi aXRzIHJlZ2lzdGVyLiBBIHUzMiB2YWx1ZSBmb3IgdGhlIHJlZ2lzdGVyIGZpeGVzCj4gdGhlIHdy b25nIHNoaWZ0cyB3YXJuaW5ncyBhbmQgbWF0Y2hlcyB0aGUgZGF0YXNoZWV0Lgo+IAo+IFRoaXMg cGF0Y2ggYWxzbyBmaXhlcyB0aGUgbWFzayB0byBhY2Nlc3MgdG8gdGhlIENBUyBiaXRzIFsxNiB0 byAyOF0gaW4KPiB0aGUgaTUwMDAgZWRhYyBkcml2ZXIuCj4gCj4gWzFdOiBodHRwczovL3d3dy5p bnRlbC5jb20vY29udGVudC9kYW0vZG9jL2RhdGFzaGVldC81MDAwcC01MDAwdi01MDAwei1jaGlw c2V0LW1lbW9yeS1jb250cm9sbGVyLWh1Yi1kYXRhc2hlZXQucGRmCgpXZWxsLCB0aGUgQ0FTIGZp ZWxkIGxlbmd0aCBoZXJlIGlzIFsyNzoxNl0sIHNlZSBiZWxvdy4KCj4gWzJdOiBodHRwczovL3d3 dy5pbnRlbC5zZS9jb250ZW50L2RhbS9kb2MvZGF0YXNoZWV0LzU0MDAtY2hpcHNldC1tZW1vcnkt Y29udHJvbGxlci1odWItZGF0YXNoZWV0LnBkZgoKSGVyZSBpdCBpcyBbMjg6MTZdLgoKPiBTaWdu ZWQtb2ZmLWJ5OiBKw6lyw6lteSBMZWZhdXJlIDxqZXJlbXkubGVmYXVyZUBsc2UuZXBpdGEuZnI+ Cj4gLS0tCj4gCj4gSSBoYXZlIGZvdW5kIHRoaXMgZXJyb3IgdGhhbmtzIHRvIHRoZSBzcGFyc2Ug dG9vbC4gUGxlYXNlIG5vdGUgdGhhdCB0aGlzIHBhdGNoCj4gaGFzbid0IGJlZW4gdGVzdGVkIG9u IHJlYWwgaGFyZHdhcmUuCj4gCj4gCj4gIGRyaXZlcnMvZWRhYy9pNTAwMF9lZGFjLmMgfCA2ICsr Ky0tLQo+ICBkcml2ZXJzL2VkYWMvaTU0MDBfZWRhYy5jIHwgNCArKy0tCj4gIDIgZmlsZXMgY2hh bmdlZCwgNSBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2VkYWMvaTUwMDBfZWRhYy5jIGIvZHJpdmVycy9lZGFjL2k1MDAwX2VkYWMuYwo+IGlu ZGV4IGY2ODM5MTk5ODFiMC4uYzc5MDE2YWRlNTFlIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZWRh Yy9pNTAwMF9lZGFjLmMKPiArKysgYi9kcml2ZXJzL2VkYWMvaTUwMDBfZWRhYy5jCj4gQEAgLTIy Nyw3ICsyMjcsNyBAQAo+ICAjZGVmaW5lCQkJTlJFQ19SRFdSKHgpCQkoKCh4KT4+MTEpICYgMSkK PiAgI2RlZmluZQkJCU5SRUNfUkFOSyh4KQkJKCgoeCk+PjgpICYgMHg3KQo+ICAjZGVmaW5lCQlO UkVDTUVNQgkJMHhDMAo+IC0jZGVmaW5lCQkJTlJFQ19DQVMoeCkJCSgoKHgpPj4xNikgJiAweEZG RkZGRikKPiArI2RlZmluZQkJCU5SRUNfQ0FTKHgpCQkoKCh4KT4+MTYpICYgMHgxRkZGKQoKVGhh dCBpcyBzdGlsbCBpbmNvcnJlY3QuIEFjY29yZGluZyB0byB0aGUgNTAwMD8gZGF0YXNoZWV0IGFi b3ZlLApOUkVDTUVNQiBoYXMgdGhlIENBUyBmaWVsZCBpbiBiaXRzIFsyNzoxNl0uIFRoYXQncyAx MiBiaXRzLCBzbyB0aGUgbWFzawpzaG91bGQgYmUgMHhGRkYuIElPVywKCiNkZWZpbmUJCQlOUkVD X0NBUyh4KQkJKCgoeCk+PjE2KSAmIDB4RkZGKQoKVGhlIDB4MUZGRiBtYXNrIGlzIGNvcnJlY3Qg Zm9yIHRoZSA1NDAwIGRyaXZlciBiZWNhdXNlIHRoZSBDQVMgZmllbGQKdGhlcmUgaXMgWzI4OjE2 XS4KClRoZSBmYWN0IHRoYXQgbm8gb25lIGNhdWdodCB0aGlzIGJ5IG5vdyBnb2VzIHRvIHNob3cg aG93IG1hbnkgcGVvcGxlIGFyZQphY3R1YWxseSB1c2luZyB0aGlzIHRoaW5nLiA6LVwK