From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Wang Subject: Re: [PATCH 05/20] drm/i915: introduce page_size members Date: Thu, 29 Jun 2017 14:36:52 +0800 Message-ID: <20170629063652.7zp5jtgoayeg3gje@zhen-hp.sh.intel.com> References: <20170627145444.20491-1-matthew.auld@intel.com> <20170627145444.20491-6-matthew.auld@intel.com> Reply-To: Zhenyu Wang Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0698956972==" Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E00D6E11E for ; Thu, 29 Jun 2017 06:41:34 +0000 (UTC) In-Reply-To: <20170627145444.20491-6-matthew.auld@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Matthew Auld Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0698956972== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="qpxhn5ifdpt2r72o" Content-Disposition: inline --qpxhn5ifdpt2r72o Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 2017.06.27 15:54:29 +0100, Matthew Auld wrote: > In preparation for supporting huge gtt pages for the ppgtt, we introduce > page size members for gem objects. We fill in the page sizes by > scanning the sg table. >=20 > v2: pass the sg_mask to set_pages >=20 > v3: calculate the sg_mask inline with populating the sg_table where > possible, and pass to set_pages along with the pages. >=20 > Signed-off-by: Matthew Auld > Cc: Joonas Lahtinen > Cc: Chris Wilson > Cc: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_drv.h | 5 ++- > drivers/gpu/drm/i915/i915_gem.c | 43 ++++++++++++++++++= ++---- > drivers/gpu/drm/i915/i915_gem_dmabuf.c | 17 ++++++++-- > drivers/gpu/drm/i915/i915_gem_internal.c | 5 ++- > drivers/gpu/drm/i915/i915_gem_object.h | 20 ++++++++++- > drivers/gpu/drm/i915/i915_gem_stolen.c | 13 ++++--- > drivers/gpu/drm/i915/i915_gem_userptr.c | 26 ++++++++++---- > drivers/gpu/drm/i915/selftests/huge_gem_object.c | 4 ++- > drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 3 +- > 9 files changed, 110 insertions(+), 26 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index fe225cb9b622..0539f210622f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2951,6 +2951,8 @@ intel_info(const struct drm_i915_private *dev_priv) > #define USES_PPGTT(dev_priv) (i915.enable_ppgtt) > #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >=3D 2) > #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt =3D=3D 3) > +#define HAS_PAGE_SIZE(dev_priv, page_size) \ > + ((dev_priv)->info.page_size_mask & (page_size)) > =20 > #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) > #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ > @@ -3335,7 +3337,8 @@ i915_gem_object_get_dma_address(struct drm_i915_gem= _object *obj, > unsigned long n); > =20 > void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, > - struct sg_table *pages); > + struct sg_table *pages, > + unsigned int sg_mask); > int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); > =20 > static inline int __must_check > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_= gem.c > index 80539a821004..4d29a5cfa0c4 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -163,7 +163,8 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, v= oid *data, > } > =20 > static struct sg_table * > -i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) > +i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj, > + unsigned int *sg_mask) > { > struct address_space *mapping =3D obj->base.filp->f_mapping; > drm_dma_handle_t *phys; > @@ -223,6 +224,8 @@ i915_gem_object_get_pages_phys(struct drm_i915_gem_ob= ject *obj) > sg->offset =3D 0; > sg->length =3D obj->base.size; > =20 > + *sg_mask =3D sg->length; > + > sg_dma_address(sg) =3D phys->busaddr; > sg_dma_len(sg) =3D obj->base.size; > =20 > @@ -2314,6 +2317,8 @@ void __i915_gem_object_put_pages(struct drm_i915_ge= m_object *obj, > if (!IS_ERR(pages)) > obj->ops->put_pages(obj, pages); > =20 > + obj->mm.page_sizes.phys =3D obj->mm.page_sizes.sg =3D 0; > + > unlock: > mutex_unlock(&obj->mm.lock); > } > @@ -2345,7 +2350,8 @@ static bool i915_sg_trim(struct sg_table *orig_st) > } > =20 > static struct sg_table * > -i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) > +i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, > + unsigned int *sg_mask) > { > struct drm_i915_private *dev_priv =3D to_i915(obj->base.dev); > const unsigned long page_count =3D obj->base.size / PAGE_SIZE; > @@ -2392,6 +2398,7 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_o= bject *obj) > =20 > sg =3D st->sgl; > st->nents =3D 0; > + *sg_mask =3D 0; > for (i =3D 0; i < page_count; i++) { > const unsigned int shrink[] =3D { > I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE, > @@ -2443,8 +2450,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_= object *obj) > if (!i || > sg->length >=3D max_segment || > page_to_pfn(page) !=3D last_pfn + 1) { > - if (i) > + if (i) { > + *sg_mask |=3D sg->length; > sg =3D sg_next(sg); > + } > st->nents++; > sg_set_page(sg, page, PAGE_SIZE, 0); > } else { > @@ -2455,8 +2464,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_= object *obj) > /* Check that the i965g/gm workaround works. */ > WARN_ON((gfp & __GFP_DMA32) && (last_pfn >=3D 0x00100000UL)); > } > - if (sg) /* loop terminated early; short sg table */ > + if (sg) { /* loop terminated early; short sg table */ > + *sg_mask |=3D sg->length; > sg_mark_end(sg); > + } > =20 > /* Trim unused sg entries to avoid wasting memory. */ > i915_sg_trim(st); > @@ -2510,8 +2521,13 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_= object *obj) > } > =20 > void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, > - struct sg_table *pages) > + struct sg_table *pages, > + unsigned int sg_mask) > { > + struct drm_i915_private *i915 =3D to_i915(obj->base.dev); > + unsigned long supported_page_sizes =3D INTEL_INFO(i915)->page_size_mask; > + unsigned int bit; > + > lockdep_assert_held(&obj->mm.lock); > =20 > obj->mm.get_page.sg_pos =3D pages->sgl; > @@ -2525,11 +2541,24 @@ void __i915_gem_object_set_pages(struct drm_i915_= gem_object *obj, > __i915_gem_object_pin_pages(obj); > obj->mm.quirked =3D true; > } > + > + GEM_BUG_ON(!sg_mask); > + > + obj->mm.page_sizes.phys =3D sg_mask; > + > + obj->mm.page_sizes.sg =3D 0; > + for_each_set_bit(bit, &supported_page_sizes, BITS_PER_LONG) { > + if (obj->mm.page_sizes.phys & ~0u << bit) > + obj->mm.page_sizes.sg |=3D BIT(bit); > + } > + > + GEM_BUG_ON(!HAS_PAGE_SIZE(i915, obj->mm.page_sizes.sg)); We need to fallback to default supported page size when vGPU is active (int= el_vgpu_active() is true). Currently gvt gtt handling can't support huge page entry yet, we need to ch= eck either hypervisor mm can support huge guest page or just do emulation in gvt. --=20 Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 --qpxhn5ifdpt2r72o Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQTXuabgHDW6LPt9CICxBBozTXgYJwUCWVSgBAAKCRCxBBozTXgY J/ZZAJ4s01BFZPQuZbHRzRsw+bH/1ZV9TwCeO3sfCp9C/MJ7++BMU95KqFBxN6E= =HkD4 -----END PGP SIGNATURE----- --qpxhn5ifdpt2r72o-- --===============0698956972== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0698956972==--