From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752455AbdF2IhH (ORCPT ); Thu, 29 Jun 2017 04:37:07 -0400 Received: from mail.skyhub.de ([5.9.137.197]:39826 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752090AbdF2Ig4 (ORCPT ); Thu, 29 Jun 2017 04:36:56 -0400 Date: Thu, 29 Jun 2017 10:36:26 +0200 From: Borislav Petkov To: =?utf-8?B?SsOpcsOpbXk=?= Lefaure Cc: Mauro Carvalho Chehab , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] edac, i5000, i5400: fix definition of nrecmemb register Message-ID: <20170629083626.6xve6bfddyx7xajs@pd.tnic> References: <20170612174759.7649-1-jeremy.lefaure@lse.epita.fr> <20170629005729.8478-1-jeremy.lefaure@lse.epita.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170629005729.8478-1-jeremy.lefaure@lse.epita.fr> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 28, 2017 at 08:57:29PM -0400, Jérémy Lefaure wrote: > In i5000 and i5400 edac drivers, the register nrecmemb is defined as a > 16 bits value which result in wrong shifts in the code: > CHECK drivers/edac/i5000_edac.c > drivers/edac/i5000_edac.c:485:15: warning: right shift by bigger than > source value > drivers/edac/i5000_edac.c:580:23: warning: right shift by bigger than > source value > CC drivers/edac/i5000_edac.o > CHECK drivers/edac/i5400_edac.c > drivers/edac/i5400_edac.c:391:36: warning: right shift by bigger than > source value > drivers/edac/i5400_edac.c:401:37: warning: right shift by bigger than > source value > CC drivers/edac/i5400_edac.o > > In the datasheets ([1], section 3.9.22.20 and [2], section 3.9.22.21), > this register is a 32 bits register. A u32 value for the register fixes > the wrong shifts warnings and matches the datasheet. > > This patch also fixes the mask to access to the CAS bits [27:16] in > the i5000 edac driver. > > [1]: https://www.intel.com/content/dam/doc/datasheet/5000p-5000v-5000z-chipset-memory-controller-hub-datasheet.pdf > [2]: https://www.intel.se/content/dam/doc/datasheet/5400-chipset-memory-controller-hub-datasheet.pdf > > Signed-off-by: Jérémy Lefaure > --- > > I have found this error thanks to the sparse tool. Please note that this patch > hasn't been tested on real hardware. > > v2: > * fix mask in NREC_CAS macro (0xFFF instead of 0x1FFF) > * fix bits description ("[27:16] instead of "[16 to 28]") in commit message > > > drivers/edac/i5000_edac.c | 6 +++--- > drivers/edac/i5400_edac.c | 4 ++-- > 2 files changed, 5 insertions(+), 5 deletions(-) Applied, thanks. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v2] edac, i5000, i5400: fix definition of nrecmemb register From: Borislav Petkov Message-Id: <20170629083626.6xve6bfddyx7xajs@pd.tnic> Date: Thu, 29 Jun 2017 10:36:26 +0200 To: =?utf-8?B?SsOpcsOpbXk=?= Lefaure Cc: Mauro Carvalho Chehab , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: T24gV2VkLCBKdW4gMjgsIDIwMTcgYXQgMDg6NTc6MjlQTSAtMDQwMCwgSsOpcsOpbXkgTGVmYXVy ZSB3cm90ZToKPiBJbiBpNTAwMCBhbmQgaTU0MDAgZWRhYyBkcml2ZXJzLCB0aGUgcmVnaXN0ZXIg bnJlY21lbWIgaXMgZGVmaW5lZCBhcyBhCj4gMTYgYml0cyB2YWx1ZSB3aGljaCByZXN1bHQgaW4g d3Jvbmcgc2hpZnRzIGluIHRoZSBjb2RlOgo+ICAgQ0hFQ0sgICBkcml2ZXJzL2VkYWMvaTUwMDBf ZWRhYy5jCj4gZHJpdmVycy9lZGFjL2k1MDAwX2VkYWMuYzo0ODU6MTU6IHdhcm5pbmc6IHJpZ2h0 IHNoaWZ0IGJ5IGJpZ2dlciB0aGFuCj4gc291cmNlIHZhbHVlCj4gZHJpdmVycy9lZGFjL2k1MDAw X2VkYWMuYzo1ODA6MjM6IHdhcm5pbmc6IHJpZ2h0IHNoaWZ0IGJ5IGJpZ2dlciB0aGFuCj4gc291 cmNlIHZhbHVlCj4gICBDQyAgICAgIGRyaXZlcnMvZWRhYy9pNTAwMF9lZGFjLm8KPiAgIENIRUNL ICAgZHJpdmVycy9lZGFjL2k1NDAwX2VkYWMuYwo+IGRyaXZlcnMvZWRhYy9pNTQwMF9lZGFjLmM6 MzkxOjM2OiB3YXJuaW5nOiByaWdodCBzaGlmdCBieSBiaWdnZXIgdGhhbgo+IHNvdXJjZSB2YWx1 ZQo+IGRyaXZlcnMvZWRhYy9pNTQwMF9lZGFjLmM6NDAxOjM3OiB3YXJuaW5nOiByaWdodCBzaGlm dCBieSBiaWdnZXIgdGhhbgo+IHNvdXJjZSB2YWx1ZQo+ICAgQ0MgICAgICBkcml2ZXJzL2VkYWMv aTU0MDBfZWRhYy5vCj4gCj4gSW4gdGhlIGRhdGFzaGVldHMgKFsxXSwgc2VjdGlvbiAzLjkuMjIu MjAgYW5kIFsyXSwgc2VjdGlvbiAzLjkuMjIuMjEpLAo+IHRoaXMgcmVnaXN0ZXIgaXMgYSAzMiBi aXRzIHJlZ2lzdGVyLiBBIHUzMiB2YWx1ZSBmb3IgdGhlIHJlZ2lzdGVyIGZpeGVzCj4gdGhlIHdy b25nIHNoaWZ0cyB3YXJuaW5ncyBhbmQgbWF0Y2hlcyB0aGUgZGF0YXNoZWV0Lgo+IAo+IFRoaXMg cGF0Y2ggYWxzbyBmaXhlcyB0aGUgbWFzayB0byBhY2Nlc3MgdG8gdGhlIENBUyBiaXRzIFsyNzox Nl0gaW4KPiB0aGUgaTUwMDAgZWRhYyBkcml2ZXIuCj4gCj4gWzFdOiBodHRwczovL3d3dy5pbnRl bC5jb20vY29udGVudC9kYW0vZG9jL2RhdGFzaGVldC81MDAwcC01MDAwdi01MDAwei1jaGlwc2V0 LW1lbW9yeS1jb250cm9sbGVyLWh1Yi1kYXRhc2hlZXQucGRmCj4gWzJdOiBodHRwczovL3d3dy5p bnRlbC5zZS9jb250ZW50L2RhbS9kb2MvZGF0YXNoZWV0LzU0MDAtY2hpcHNldC1tZW1vcnktY29u dHJvbGxlci1odWItZGF0YXNoZWV0LnBkZgo+IAo+IFNpZ25lZC1vZmYtYnk6IErDqXLDqW15IExl ZmF1cmUgPGplcmVteS5sZWZhdXJlQGxzZS5lcGl0YS5mcj4KPiAtLS0KPiAKPiBJIGhhdmUgZm91 bmQgdGhpcyBlcnJvciB0aGFua3MgdG8gdGhlIHNwYXJzZSB0b29sLiBQbGVhc2Ugbm90ZSB0aGF0 IHRoaXMgcGF0Y2gKPiBoYXNuJ3QgYmVlbiB0ZXN0ZWQgb24gcmVhbCBoYXJkd2FyZS4KPiAKPiB2 MjoKPiAqIGZpeCBtYXNrIGluIE5SRUNfQ0FTIG1hY3JvICgweEZGRiBpbnN0ZWFkIG9mIDB4MUZG RikKPiAqIGZpeCBiaXRzIGRlc2NyaXB0aW9uICgiWzI3OjE2XSBpbnN0ZWFkIG9mICJbMTYgdG8g MjhdIikgaW4gY29tbWl0IG1lc3NhZ2UKPiAKPiAKPiAgZHJpdmVycy9lZGFjL2k1MDAwX2VkYWMu YyB8IDYgKysrLS0tCj4gIGRyaXZlcnMvZWRhYy9pNTQwMF9lZGFjLmMgfCA0ICsrLS0KPiAgMiBm aWxlcyBjaGFuZ2VkLCA1IGluc2VydGlvbnMoKyksIDUgZGVsZXRpb25zKC0pCgpBcHBsaWVkLCB0 aGFua3MuCg==