From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Wang Subject: Re: [PATCH 05/20] drm/i915: introduce page_size members Date: Thu, 29 Jun 2017 23:33:41 +0800 Message-ID: <20170629153341.glf7z5gbwzdce2hl@zhen-hp.sh.intel.com> References: <20170627145444.20491-1-matthew.auld@intel.com> <20170627145444.20491-6-matthew.auld@intel.com> <20170629063652.7zp5jtgoayeg3gje@zhen-hp.sh.intel.com> <149873754890.23475.9361227449585524587@mail.alporthouse.com> Reply-To: Zhenyu Wang Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1612270398==" Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7479F6E65D for ; Thu, 29 Jun 2017 15:38:24 +0000 (UTC) In-Reply-To: <149873754890.23475.9361227449585524587@mail.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: Intel Graphics Development , Matthew Auld List-Id: intel-gfx@lists.freedesktop.org --===============1612270398== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="4d32gfel7ws53itj" Content-Disposition: inline --4d32gfel7ws53itj Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On 2017.06.29 12:59:08 +0100, Chris Wilson wrote: > Quoting Matthew Auld (2017-06-29 12:54:51) > > On 29 June 2017 at 07:36, Zhenyu Wang wrote: > > > We need to fallback to default supported page size when vGPU is activ= e (intel_vgpu_active() is true). > > > Currently gvt gtt handling can't support huge page entry yet, we need= to check either hypervisor > > > mm can support huge guest page or just do emulation in gvt. > > That should already be the case, since the guest doesn't support the > > 48b PPGTT. But it looks you are working to change that, so I guess we > > should just do this anyway? > yes, 48b ppgtt guest will be supported. > Fwiw, I think it makes sense just to sanitize the > mkwrite_intel_info()->page_sizes under virtualisation. Primarily to > document what we know does not work at the moment and so different > features can be enabled individually. I just thought the minimal code change to take that into account, as long as it's after vgpu active/feature detect, that's fine too. > Or just disable gvt :-p That reason is not strong enough I believe. ;) --=20 Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 --4d32gfel7ws53itj Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQTXuabgHDW6LPt9CICxBBozTXgYJwUCWVUd1QAKCRCxBBozTXgY JyBsAJ9ij2j3Dgn1RrydcbT1A/osmUvfSgCeJ6C3WGQQZOeG+XpQjMKSO/VsKMM= =d5OI -----END PGP SIGNATURE----- --4d32gfel7ws53itj-- --===============1612270398== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1612270398==--