[Qemu-devel] [RISU PATCH 00/11] Misc fixes, documentation and patterns

[Qemu-devel] [RISU PATCH 00/11] Misc fixes, documentation and patterns

[Alex Bennée]

Hi Peter,

A bit of a mixed set of patches here for you to pick from as you
will. The first 2 are additional tracing fixes including a fix for
segfaulting when generating a trace.

The next two are documentation patches as requested.

Then two minor tweaks, one to risu.el and a indent failure of risugen.

While I've been working through the half-precision stuff I've been
finding the --pattern approach a bit inflexible as you basically end
up eyeballing the risu file to build up the regexs. I've added a
little syntactic suger to the risu file to enable grouping. This makes
slicing a subset a lot easier, e.g.:

  ./risugen --group AdvSIMDAcrossVector --not-pattern ".*_RES" aarch64.risu

You can specify multiple groups in the risu file as the matching is
string based, e.g.:

  @Integer,Logic,Immediate

And then:

  ./risugen --group Logic aarch64.risu foo.bin

What do you think?

Alex Bennée (11):
  risu: make match status take tracing into account
  reginfo.c: always return 1 on OP_TESTEND
  README: document --static builds
  README: document record/replay support
  risu.el: derive from text-mode
  risugen: fix bad indent
  risugen: support @GroupName in risu files
  aarch64.risu: document naming conventions
  aarch64.risu: remove duplicate AdvSIMD Scalar 3 same block
  aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc block
  aarch64.risu: update AdvancedSIMD across lanes

 README         |  40 ++++++++--
 aarch64.risu   | 241 ++++++++++++++++++++++++---------------------------------
 reginfo.c      |  19 +++--
 risu.c         |   4 +-
 risu.el        |   2 +-
 risu.h         |   2 +-
 risugen        |  17 +++-
 risugen_arm.pm |   7 ++
 8 files changed, 175 insertions(+), 157 deletions(-)

-- 
2.13.0

[Qemu-devel] [RISU PATCH 01/11] risu: make match status take tracing into account

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 reginfo.c | 14 +++++++++-----
 risu.c    |  4 ++--
 risu.h    |  2 +-
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/reginfo.c b/reginfo.c
index 13879d5..d9d37b3 100644
--- a/reginfo.c
+++ b/reginfo.c
@@ -138,7 +138,7 @@ int recv_and_compare_register_info(read_fn read_fn,
  * Should return 0 if it was a good match (ie end of test)
  * and 1 for a mismatch.
  */
-int report_match_status(void)
+int report_match_status(int trace)
 {
     int resp = 0;
     fprintf(stderr, "match status...\n");
@@ -148,7 +148,7 @@ int report_match_status(void)
         /* We don't have valid reginfo from the apprentice side
          * so stop now rather than printing anything about it.
          */
-        fprintf(stderr, "master reginfo:\n");
+        fprintf(stderr, "%s reginfo:\n", trace ? "this":"master");
         reginfo_dump(&master_ri, stderr);
         return 1;
     }
@@ -166,11 +166,15 @@ int report_match_status(void)
         return 0;
     }
 
-    fprintf(stderr, "master reginfo:\n");
+    fprintf(stderr, "%s reginfo:\n", trace ? "this":"master");
     reginfo_dump(&master_ri, stderr);
-    fprintf(stderr, "apprentice reginfo:\n");
+    fprintf(stderr, "%s reginfo:\n", trace ? "trace":"apprentice");
     reginfo_dump(&apprentice_ri, stderr);
 
-    reginfo_dump_mismatch(&master_ri, &apprentice_ri, stderr);
+    if (trace) {
+        reginfo_dump_mismatch(&apprentice_ri, &master_ri, stderr);
+    } else {
+        reginfo_dump_mismatch(&master_ri, &apprentice_ri, stderr);
+    }
     return resp;
 }
diff --git a/risu.c b/risu.c
index 6f213dc..47471c6 100644
--- a/risu.c
+++ b/risu.c
@@ -228,7 +228,7 @@ int master(void)
                     signal_count);
             return 0;
         } else {
-            return report_match_status();
+            return report_match_status(0);
         }
     }
     set_sigill_handler(&master_sigill);
@@ -250,7 +250,7 @@ int apprentice(void)
 #endif
         close(apprentice_fd);
         fprintf(stderr, "finished early after %zd checkpoints\n", signal_count);
-        return report_match_status();
+        return report_match_status(1);
     }
     set_sigill_handler(&apprentice_sigill);
     fprintf(stderr, "starting apprentice image at 0x%"PRIxPTR"\n",
diff --git a/risu.h b/risu.h
index 9f15662..1c8ecee 100644
--- a/risu.h
+++ b/risu.h
@@ -91,7 +91,7 @@ int recv_and_compare_register_info(read_fn read_fn,
  * Should return 0 if it was a good match (ie end of test)
  * and 1 for a mismatch.
  */
-int report_match_status(void);
+int report_match_status(int trace);
 
 /* Interface provided by CPU-specific code: */
 
-- 
2.13.0

[Qemu-devel] [RISU PATCH 02/11] reginfo.c: always return 1 on OP_TESTEND

[Alex Bennée]

In the master/apprentice setup the response byte of 1 is returned by
write_fn. However when tracing it will happily report 0 as it
successfully writes the last bytes. To avoid running of the end when
tracing we just always return 1 at this point.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 reginfo.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/reginfo.c b/reginfo.c
index d9d37b3..76f24f9 100644
--- a/reginfo.c
+++ b/reginfo.c
@@ -39,7 +39,10 @@ int send_register_info(write_fn write_fn, void *uc)
 
     switch (op) {
     case OP_TESTEND:
-        return write_fn(&ri, sizeof(ri));
+        write_fn(&ri, sizeof(ri));
+        /* if we are tracing write_fn will return 0 unlike a remote
+           end, hence we force return of 1 here */
+        return 1;
     case OP_SETMEMBLOCK:
         memblock = (void *)(uintptr_t)get_reginfo_paramreg(&ri);
         break;
-- 
2.13.0

[Qemu-devel] [RISU PATCH 03/11] README: document --static builds

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 README | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/README b/README
index 858a349..e0bf5c5 100644
--- a/README
+++ b/README
@@ -17,7 +17,7 @@ test blobs (which can be run anywhere), and a Linux executable
 'risu' which runs on the target architecture (ie ARM). To
 build the executable part:
 
-    [VAR=VALUE] ... ./configure
+    [VAR=VALUE] ... ./configure [--static]
     make
 
 where [VAR=VALUE] ... allows you to specify any options.
@@ -25,6 +25,10 @@ Most useful is
  CROSS_PREFIX= which specifies the cross compiler prefix; you'll
    need this if you're not building on the target system
    (Example: CROSS_PREFIX=arm-linux-gnueabihf- )
+
+Passing --static will build a statically linked binary which is useful
+if you don't want to mess around with chroot's to run the binary.
+
 For other possibilities run 'configure --help'.
 
 Building into a separate build tree from the source code is supported:
@@ -86,8 +90,14 @@ as simple as:
 
 However since you actually need to run it under qemu or similar
 you probably need an ARM chroot to run it in, and to do something
-like
- sudo chroot /srv/chroot/arm-mav /risu --host ipaddr vqshlimm.out
+like:
+
+  sudo chroot /srv/chroot/arm-mav /risu --host ipaddr vqshlimm.out
+
+If you built the binary statically you can simply run:
+
+  /path/to/qemu ./risu --host ipaddr vqshlimm.out
+
 
 When the apprentice connects to the master, they will both start
 running the binary and checking results with each other. When the
-- 
2.13.0

[Qemu-devel] [RISU PATCH 04/11] README: document record/replay support

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 README | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

diff --git a/README b/README
index e0bf5c5..5f16f60 100644
--- a/README
+++ b/README
@@ -107,6 +107,26 @@ mismatch status to its standard output.
 NB that in the register dump the r15 (pc) value will be given
 as an offset from the start of the binary, not an absolute value.
 
+While the master/slave setup works well it is a bit fiddly for running
+regression tests and other sorts of automation. For this reason risu
+supports recording a trace of its execution to a file. For example:
+
+  risu --master FxxV_across_lanes.risu.bin -t FxxV_across_lanes.risu.trace
+
+And then playback with:
+
+  risu FxxV_across_lanes.risu.bin -t FxxV_across_lanes.risu.trace
+
+Ideally it should be built with zlib to compress the trace files which
+would otherwise be huge. If building with zlib proves too tricky you
+can pipe to stdout and an external compression binary using "-t -".
+
+  risu --master FxxV_across_lanes.risu.bin -t - | gzip --best > trace.file
+
+and:
+
+  gunzip -c trace.file | risu -t - FxxV_across_lanes.risu.bin
+
 File format
 -----------
 
@@ -203,10 +223,6 @@ implementation, for example) but only ARM is tested.
  * we don't actually compare FP status flags, simply because
 I'm pretty sure qemu doesn't get them right yet and I'm more
 interested in fixing gross bugs first.
- * there isn't currently any support for a "record and replay
-results" mode. This would allow you to record the correct
-results from the ARM host once and then test a model implementation
-even if you didn't have the corresponding native hardware.
  * You can compile statically to avoid the requirement for the ARM
 chroot for qemu testing but you can no longer use gethostbyname() and need
 to specify your hosts by IP address.
-- 
2.13.0

[Qemu-devel] [RISU PATCH 05/11] risu.el: derive from text-mode

[Alex Bennée]

As RISU files have copious commentary it seems better to derive from
text-mode so we can access things like spell-checker short cuts ;-)

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 risu.el | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/risu.el b/risu.el
index dff9337..1875d02 100644
--- a/risu.el
+++ b/risu.el
@@ -39,7 +39,7 @@
 
 ;;; Code
 
-(define-derived-mode risu-mode fundamental-mode "RISU"
+(define-derived-mode risu-mode text-mode "RISU"
   "Major mode for editing RISU control files."
   (set (make-local-variable 'font-lock-defaults) '(risu-font-lock-keywords)))
 
-- 
2.13.0

[Qemu-devel] [RISU PATCH 06/11] risugen: fix bad indent

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 risugen | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/risugen b/risugen
index 8b20425..347cf12 100755
--- a/risugen
+++ b/risugen
@@ -262,7 +262,7 @@ Valid options:
                    These REs are applied after the matching pattern which
                    is useful if you want to exclude a specific instruction from
                    a general set you have excluded.
-     --no-fp      : disable floating point: no fp init, randomization etc.
+    --no-fp      : disable floating point: no fp init, randomization etc.
                    Useful to test before support for FP is available.
     --be         : generate instructions in Big-Endian byte order (ppc64 only).
     --help       : print this message
-- 
2.13.0

[Qemu-devel] [RISU PATCH 07/11] risugen: support @GroupName in risu files

[Alex Bennée]

The existing pattern support is useful but it does get a little
tedious when faced with large groups of instructions. This introduces
the concept of a @GroupName which can be sprinkled in the risu
definition and is attached to all instructions following its
definition until the next group or an empty group "@" is specified.

It can be combined with the existing pattern support to do things
like:

  ./risugen --group AdvSIMDAcrossVector --not-pattern ".*_RES" aarch64.risu foo.bin

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 risugen        | 15 +++++++++++++++
 risugen_arm.pm |  7 +++++++
 2 files changed, 22 insertions(+)

diff --git a/risugen b/risugen
index 347cf12..97ffa83 100755
--- a/risugen
+++ b/risugen
@@ -30,7 +30,10 @@ my %insn_details;
 
 # The arch will be selected based on .mode directive defined in risu file.
 my $arch = "";
+# Current group, updated by @GroupName
+my $insn_group = "";
 
+my @group = ();                 # include groups
 my @pattern_re = ();            # include pattern
 my @not_pattern_re = ();        # exclude pattern
 
@@ -118,6 +121,11 @@ sub parse_config_file($)
             exit(1);
         }
 
+        if ($tokens[0] =~ /^@(.*)/ ) {
+            $insn_group = $1;
+            next;
+        }
+
         if ($tokens[0] =~ /^\./) {
             parse_risu_directive($file, $seen_pattern, @tokens);
             next;
@@ -235,6 +243,9 @@ sub parse_config_file($)
         $insnrec->{fixedbits} = $fixedbits;
         $insnrec->{fixedbitmask} = $fixedbitmask;
         $insnrec->{fields} = [ @fields ];
+        if (length $insn_group) {
+            $insnrec->{group} = $insn_group;
+        }
         $insn_details{$insnname} = $insnrec;
     }
     close(CFILE) or die "can't close $file: $!";
@@ -253,6 +264,7 @@ Valid options:
     --fpscr n    : set initial FPSCR (arm) or FPCR (aarch64) value (default is 0)
     --condprob p : [ARM only] make instructions conditional with probability p
                    (default is 0, ie all instructions are always executed)
+    --group name[,name..]: only use instructions in defined groups
     --pattern re[,re...] : only use instructions matching regular expression
                    Each re must match a full word (that is, we match on
                    the perl regex '\\b((re)|(re))\\b'). This means that
@@ -281,6 +293,7 @@ sub main()
     GetOptions( "help" => sub { usage(); exit(0); },
                 "numinsns=i" => \$numinsns,
                 "fpscr=o" => \$fpscr,
+                "group=s" => \@group,
                 "pattern=s" => \@pattern_re,
                 "not-pattern=s" => \@not_pattern_re,
                 "condprob=f" => sub {
@@ -295,6 +308,7 @@ sub main()
     # allow "--pattern re,re" and "--pattern re --pattern re"
     @pattern_re = split(/,/,join(',',@pattern_re));
     @not_pattern_re = split(/,/,join(',',@not_pattern_re));
+    @group = split(/,/,join(',',@group));
 
     if ($#ARGV != 1) {
         usage();
@@ -316,6 +330,7 @@ sub main()
         'numinsns' => $numinsns,
         'fp_enabled' => $fp_enabled,
         'outfile' => $outfile,
+        'group' => \@group,
         'pattern_re' => \@pattern_re,
         'not_pattern_re' => \@not_pattern_re,
         'details' => \%insn_details,
diff --git a/risugen_arm.pm b/risugen_arm.pm
index 1024660..8ad208a 100644
--- a/risugen_arm.pm
+++ b/risugen_arm.pm
@@ -895,6 +895,7 @@ sub write_test_code($$$$$$$$)
     my $fp_enabled = $params->{ 'fp_enabled' };
     my $outfile = $params->{ 'outfile' };
 
+    my @group = @{ $params->{ 'group' } };
     my @pattern_re = @{ $params->{ 'pattern_re' } };
     my @not_pattern_re = @{ $params->{ 'not_pattern_re' } };
     my %insn_details = %{ $params->{ 'details' } };
@@ -910,6 +911,12 @@ sub write_test_code($$$$$$$$)
 
     # Get a list of the insn keys which are permitted by the re patterns
     my @keys = sort keys %insn_details;
+    if (@group) {
+        my $re = join("|",@group);
+        @keys = grep {
+            defined($insn_details{$_}->{group}) &&
+                grep /$re/, $insn_details{$_}->{group}} @keys
+    }
     if (@pattern_re) {
         my $re = '\b((' . join(')|(',@pattern_re) . '))\b';
         @keys = grep /$re/, @keys;
-- 
2.13.0

[Qemu-devel] [RISU PATCH 08/11] aarch64.risu: document naming conventions

[Alex Bennée]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 aarch64.risu | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/aarch64.risu b/aarch64.risu
index 2f3341c..bfca45f 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -7,6 +7,7 @@
 #
 # Contributors:
 #     Claudio Fontana - initial implementation
+#     Alex Bennée - a number of additions including v8.2 FP16
 #     based on arm.risu by Peter Maydell
 ###############################################################################
 
@@ -19,6 +20,15 @@
 # XXX NIY: SP-related instructions
 # XXX NIY: floating point and SIMD specific insns
 
+# Instruction suffixes to identify variants
+#   m - memory (loads/stores)
+#   s - scalar
+#   v - vector
+#   z - zero (e.g. compare to zero)
+#   f - fixed point
+#
+# _FP16 for ARMv8.2 half-precision extensions
+
 # - - - - 1 - 0 - - - - - - - - - - - - - - - Loads and stores
 # C3.3 Loads and stores
 
-- 
2.13.0

[Qemu-devel] [RISU PATCH 09/11] aarch64.risu: remove duplicate AdvSIMD Scalar 3 same block

[Alex Bennée]

A chunk of the AArch64 definitions repeat themselves. Clean that up.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 aarch64.risu | 25 +++----------------------
 1 file changed, 3 insertions(+), 22 deletions(-)

diff --git a/aarch64.risu b/aarch64.risu
index bfca45f..609021a 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2130,6 +2130,8 @@ SQDMULL_S3D A64_V 0 1 U 11110 size:2 1 rm:5 1101 00 rn:5 rd:5
 # 31 30 29 28 27 26 25 24 23 22 21 20    16 15      11 10  9    5   4    0
 #  0  1 U   1  1  1  1  0  size  1 [  Rm  ] [ opcode ]  1 [  Rn  ] [  Rd  ]
 #
+@AdvSIMDScalar3Same
+
 SQADD    A64_V   01 0 11110 size:2 1 rm:5 00001 1 rn:5 rd:5
 SQSUB    A64_V   01 0 11110 size:2 1 rm:5 00101 1 rn:5 rd:5
 CMGT     A64_V   01 0 11110 size:2 1 rm:5 00110 1 rn:5 rd:5
@@ -2167,28 +2169,7 @@ FCMGT    A64_V   01 1 11110 1 size:1 1 rm:5 11100 1 rn:5 rd:5
 FACGT    A64_V   01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 \
 !constraints { $size != 11; }
 
-CMTST    A64_v   01 0 11110 size:2 1 rm:5 10001 1 rn:5 rd:5
-SQDMULH  A64_v   01 0 11110 size:2 1 rm:5 10110 1 rn:5 rd:5
-FMULX    A64_v   01 0 11110 0 size:1 1 rm:5 11011 1 rn:5 rd:5
-FCMEQ    A64_v   01 0 11110 0 size:1 1 rm:5 11100 1 rn:5 rd:5
-FRECPS   A64_v   01 0 11110 0 size:1 1 rm:5 11111 1 rn:5 rd:5
-FRSQRTS  A64_v   01 0 11110 1 size:1 1 rm:5 11111 1 rn:5 rd:5
-UQADD    A64_v   01 1 11110 size:2 1 rm:5 00001 1 rn:5 rd:5
-UQSUB    A64_v   01 1 11110 size:2 1 rm:5 00101 1 rn:5 rd:5
-CMHI     A64_v   01 1 11110 size:2 1 rm:5 00110 1 rn:5 rd:5
-CMHS     A64_v   01 1 11110 size:2 1 rm:5 00111 1 rn:5 rd:5
-USHL     A64_v   01 1 11110 size:2 1 rm:5 01000 1 rn:5 rd:5
-UQSHL    A64_v   01 1 11110 size:2 1 rm:5 01001 1 rn:5 rd:5
-URSHL    A64_v   01 1 11110 size:2 1 rm:5 01010 1 rn:5 rd:5
-UQRSHL   A64_v   01 1 11110 size:2 1 rm:5 01011 1 rn:5 rd:5
-SUBv     A64_v   01 1 11110 size:2 1 rm:5 10000 1 rn:5 rd:5
-CMEQ     A64_v   01 1 11110 size:2 1 rm:5 10001 1 rn:5 rd:5
-SQRDMULH A64_v   01 1 11110 size:2 1 rm:5 10110 1 rn:5 rd:5
-FCMGE    A64_v   01 1 11110 0 size:1 1 rm:5 11100 1 rn:5 rd:5
-FACGE    A64_v   01 1 11110 0 size:1 1 rm:5 11101 1 rn:5 rd:5
-FABD     A64_v   01 1 11110 1 size:1 1 rm:5 11010 1 rn:5 rd:5
-FCMGT    A64_v   01 1 11110 1 size:1 1 rm:5 11100 1 rn:5 rd:5
-FACGT    A64_v   01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5
+@
 
 # C3.6.12 AdvSIMD scalar 2reg misc
 CMGTzero A64_V      01 0 11110 size:2 10000 01000 10 rn:5 rd:5
-- 
2.13.0

[Qemu-devel] [RISU PATCH 10/11] aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc block

[Alex Bennée]

While at that also:
  - sort alphabetically
  - add to @AdvSIMDScalar2RegMisc group

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 aarch64.risu | 114 ++++++++++++++++++++---------------------------------------
 1 file changed, 39 insertions(+), 75 deletions(-)

diff --git a/aarch64.risu b/aarch64.risu
index 609021a..5450cd3 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2171,85 +2171,49 @@ FACGT    A64_V   01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 \
 
 @
 
-# C3.6.12 AdvSIMD scalar 2reg misc
-CMGTzero A64_V      01 0 11110 size:2 10000 01000 10 rn:5 rd:5
-CMGEzero A64_V      01 1 11110 size:2 10000 01000 10 rn:5 rd:5
-CMEQzero A64_V      01 0 11110 size:2 10000 01001 10 rn:5 rd:5
-CMLEzero A64_V      01 1 11110 size:2 10000 01001 10 rn:5 rd:5
-CMLTzero A64_V      01 0 11110 size:2 10000 01010 10 rn:5 rd:5
-ABS A64_V           01 0 11110 size:2 10000 01011 10 rn:5 rd:5
-NEG A64_V           01 1 11110 size:2 10000 01011 10 rn:5 rd:5
-
-FCMGT_S2MISC A64_V  01 0 11110 size:2 10000 01100 10 rn:5 rd:5
-FCMEQ_S2MISC A64_V  01 0 11110 size:2 10000 01101 10 rn:5 rd:5
-FCMLT_S2MISC A64_V  01 0 11110 size:2 10000 01110 10 rn:5 rd:5
-FCMGE_S2MISC A64_V  01 1 11110 size:2 10000 01100 10 rn:5 rd:5
-FCMLE_S2MISC A64_V  01 1 11110 size:2 10000 01101 10 rn:5 rd:5
-
-SCVTF_S2MISC A64_V 01 0 11110 0 sz 10000 11101 10 rn:5 rd:5
-UCVTF_S2MISC A64_V 01 1 11110 0 sz 10000 11101 10 rn:5 rd:5
-
-FCVTNS_S2MISC A64_V 01 0 11110 0 sz 10000 11010 10 rn:5 rd:5
-FCVTMS_S2MISC A64_V 01 0 11110 0 sz 10000 11011 10 rn:5 rd:5
-FCVTAS_S2MISC A64_V 01 0 11110 0 sz 10000 11100 10 rn:5 rd:5
-FCVTPS_S2MISC A64_V 01 0 11110 1 sz 10000 11010 10 rn:5 rd:5
-FCVTZS_S2MISC A64_V 01 0 11110 1 sz 10000 11011 10 rn:5 rd:5
-
-FCVTNU_S2MISC A64_V 01 1 11110 0 sz 10000 11010 10 rn:5 rd:5
-FCVTMU_S2MISC A64_V 01 1 11110 0 sz 10000 11011 10 rn:5 rd:5
-FCVTAU_S2MISC A64_V 01 1 11110 0 sz 10000 11100 10 rn:5 rd:5
-FCVTPU_S2MISC A64_V 01 1 11110 1 sz 10000 11010 10 rn:5 rd:5
-FCVTZU_S2MISC A64_V 01 1 11110 1 sz 10000 11011 10 rn:5 rd:5
-
-FCVTXN_S2MISC A64_V 01 1 11110 0 sz 10000 10110 10 rn:5 rd:5
-
-SUQADD_S2MISC A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5
-USQADD_S2MISC A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5
-SQABS_S2MISC A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5
-SQNEG_S2MISC A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5
-
-# XXX lots of others in this group
-
 # C3.6.12 AdvSIMD scalar two-reg misc
 # 31 30 29 28 27 26 25 24 23 22 21 20      16     12 11 10 9     5  4    0
 #  0  1 U   1  1  1  1  0  size  1 0 0 0 0 [ opcode ] 1 0 [  Rn  ] [  Rd  ]
 # U size opcode
-SUQADDs  A64_V          01 0 11110   size:2 10000 00011 10 rn:5 rd:5 
-SQABSs  A64_V           01 0 11110   size:2 10000 00111 10 rn:5 rd:5 
-CMGTzs  A64_V           01 0 11110   size:2 10000 01000 10 rn:5 rd:5 
-CMEQzs  A64_V           01 0 11110   size:2 10000 01001 10 rn:5 rd:5 
-CMLTzs  A64_V           01 0 11110   size:2 10000 01010 10 rn:5 rd:5 
-ABSs  A64_V             01 0 11110   size:2 10000 01011 10 rn:5 rd:5 
-SQXTN_SQXTN2s  A64_V    01 0 11110   size:2 10000 10100 10 rn:5 rd:5 
-FCVTNSvs  A64_V         01 0 11110 0 size:1 10000 11010 10 rn:5 rd:5 
-FCVTMSvs  A64_V         01 0 11110 0 size:1 10000 11011 10 rn:5 rd:5 
-FCVTASvs  A64_V         01 0 11110 0 size:1 10000 11100 10 rn:5 rd:5 
-SCVTFvis  A64_V         01 0 11110 0 size:1 10000 11101 10 rn:5 rd:5 
-FCMGTzs  A64_V          01 0 11110 1 size:1 10000 01100 10 rn:5 rd:5 
-FCMEQzs  A64_V          01 0 11110 1 size:1 10000 01101 10 rn:5 rd:5 
-FCMLTzs  A64_V          01 0 11110 1 size:1 10000 01110 10 rn:5 rd:5 
-FCVTPSvs  A64_V         01 0 11110 1 size:1 10000 11010 10 rn:5 rd:5 
-FCVTZSvis  A64_V        01 0 11110 1 size:1 10000 11011 10 rn:5 rd:5 
-FRECPEs  A64_V          01 0 11110 1 size:1 10000 11101 10 rn:5 rd:5 
-FRECPX  A64_V           01 0 11110 1 size:1 10000 11111 10 rn:5 rd:5 
-USQADDs  A64_V          01 1 11110   size:2 10000 00011 10 rn:5 rd:5 
-SQNEGs  A64_V           01 1 11110   size:2 10000 00111 10 rn:5 rd:5 
-CMGzs  A64_V            01 1 11110   size:2 10000 01000 10 rn:5 rd:5 
-CMLEzs  A64_V           01 1 11110   size:2 10000 01001 10 rn:5 rd:5 
-NEGvs  A64_V            01 1 11110   size:2 10000 01011 10 rn:5 rd:5 
-SQXTUN_SQXTUN2s  A64_V  01 1 11110   size:2 10000 10010 10 rn:5 rd:5 
-UQXTN_UQXTN2s  A64_V    01 1 11110   size:2 10000 10100 10 rn:5 rd:5 
-FCVTXN_FCVTXN2s  A64_V  01 1 11110 0 size:1 10000 10110 10 rn:5 rd:5 
-FCVTNUvs  A64_V         01 1 11110 0 size:1 10000 11010 10 rn:5 rd:5 
-FCVTMUvs  A64_V         01 1 11110 0 size:1 10000 11011 10 rn:5 rd:5 
-FCVTAUvs  A64_V         01 1 11110 0 size:1 10000 11100 10 rn:5 rd:5 
-UCVTFvis  A64_V         01 1 11110 0 size:1 10000 11101 10 rn:5 rd:5 
-FCMGEzs  A64_V          01 1 11110 1 size:1 10000 01100 10 rn:5 rd:5 
-FCMLEzs  A64_V          01 1 11110 1 size:1 10000 01101 10 rn:5 rd:5 
-FCVTPUvs  A64_V         01 1 11110 1 size:1 10000 11010 10 rn:5 rd:5 
-FCVTZUvis  A64_V        01 1 11110 1 size:1 10000 11011 10 rn:5 rd:5 
-FRSQRTEs  A64_V         01 1 11110 1 size:1 10000 11101 10 rn:5 rd:5 
- 
+@AdvSIMDScalar2RegMisc
+
+ABSs  A64_V             01 0 11110   size:2 10000 01011 10 rn:5 rd:5
+CMEQzs  A64_V           01 0 11110   size:2 10000 01001 10 rn:5 rd:5
+CMGTzs  A64_V           01 0 11110   size:2 10000 01000 10 rn:5 rd:5
+CMGzs  A64_V            01 1 11110   size:2 10000 01000 10 rn:5 rd:5
+CMLEzs  A64_V           01 1 11110   size:2 10000 01001 10 rn:5 rd:5
+CMLTzs  A64_V           01 0 11110   size:2 10000 01010 10 rn:5 rd:5
+FCMEQzs  A64_V          01 0 11110 1 size:1 10000 01101 10 rn:5 rd:5
+FCMGEzs  A64_V          01 1 11110 1 size:1 10000 01100 10 rn:5 rd:5
+FCMGTzs  A64_V          01 0 11110 1 size:1 10000 01100 10 rn:5 rd:5
+FCMLEzs  A64_V          01 1 11110 1 size:1 10000 01101 10 rn:5 rd:5
+FCMLTzs  A64_V          01 0 11110 1 size:1 10000 01110 10 rn:5 rd:5
+FCVTASvs  A64_V         01 0 11110 0 size:1 10000 11100 10 rn:5 rd:5
+FCVTAUvs  A64_V         01 1 11110 0 size:1 10000 11100 10 rn:5 rd:5
+FCVTMSvs  A64_V         01 0 11110 0 size:1 10000 11011 10 rn:5 rd:5
+FCVTMUvs  A64_V         01 1 11110 0 size:1 10000 11011 10 rn:5 rd:5
+FCVTNSvs  A64_V         01 0 11110 0 size:1 10000 11010 10 rn:5 rd:5
+FCVTNUvs  A64_V         01 1 11110 0 size:1 10000 11010 10 rn:5 rd:5
+FCVTPSvs  A64_V         01 0 11110 1 size:1 10000 11010 10 rn:5 rd:5
+FCVTPUvs  A64_V         01 1 11110 1 size:1 10000 11010 10 rn:5 rd:5
+FCVTXN_FCVTXN2s  A64_V  01 1 11110 0 size:1 10000 10110 10 rn:5 rd:5
+FCVTZSvis  A64_V        01 0 11110 1 size:1 10000 11011 10 rn:5 rd:5
+FCVTZUvis  A64_V        01 1 11110 1 size:1 10000 11011 10 rn:5 rd:5
+FRECPEs  A64_V          01 0 11110 1 size:1 10000 11101 10 rn:5 rd:5
+FRECPX  A64_V           01 0 11110 1 size:1 10000 11111 10 rn:5 rd:5
+FRSQRTEs  A64_V         01 1 11110 1 size:1 10000 11101 10 rn:5 rd:5
+NEGvs  A64_V            01 1 11110   size:2 10000 01011 10 rn:5 rd:5
+SCVTFvis  A64_V         01 0 11110 0 size:1 10000 11101 10 rn:5 rd:5
+SQABSs  A64_V           01 0 11110   size:2 10000 00111 10 rn:5 rd:5
+SQNEGs  A64_V           01 1 11110   size:2 10000 00111 10 rn:5 rd:5
+SQXTN_SQXTN2s  A64_V    01 0 11110   size:2 10000 10100 10 rn:5 rd:5
+SQXTUN_SQXTUN2s  A64_V  01 1 11110   size:2 10000 10010 10 rn:5 rd:5
+SUQADDs  A64_V          01 0 11110   size:2 10000 00011 10 rn:5 rd:5
+UCVTFvis  A64_V         01 1 11110 0 size:1 10000 11101 10 rn:5 rd:5
+UQXTN_UQXTN2s  A64_V    01 1 11110   size:2 10000 10100 10 rn:5 rd:5
+USQADDs  A64_V          01 1 11110   size:2 10000 00011 10 rn:5 rd:5
+
+@
 # C3.6.13 AdvSIMD scalar x indexed element
 # Complete coverage.
 
-- 
2.13.0

[Qemu-devel] [RISU PATCH 11/11] aarch64.risu: update AdvancedSIMD across lanes

[Alex Bennée]

 - sorted alphabetically
 - aligned the instructions patterns
 - adding half-precision F[MAX|MIN][NMV|V]
 - add @AdvSIMDAcrossVector group

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 aarch64.risu | 90 +++++++++++++++++++++++++++++++++---------------------------
 1 file changed, 49 insertions(+), 41 deletions(-)

diff --git a/aarch64.risu b/aarch64.risu
index 5450cd3..215882e 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -1955,50 +1955,58 @@ ZIP2 A64_V 0 Q:1 001110 size:2 0 rm:5 0 111 10 rn:5 rd:5 \
 # ReservedValue: break the !($size == 3 && $Q == 0) constraint
 ZIP2_RES A64_V 0 0 001110 11 0 rm:5 0 111 10 rn:5 rd:5
 
-# C3.6.4 AdvSIMD across lanes
+# C4-286 AdvSIMD across vector lanes
 # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16  12 11 10 9  5 4  0
 #  0  Q  U  0  1  1  1  0  size  1  1  0  0  0 opcode  1  0  Rn   Rd
+@AdvSIMDAcrossVector
+
+ADDV         A64_V 0 Q:1 0 01110 s:2 11000 11011 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+ADDV_RES     A64_V 0  0  0 01110  10 11000 11011 10 rn:5 rd:5
+
+FMAXNMV      A64_V 0  1  1 01110  00 11000 01100 10 rn:5 rd:5
+FMAXV        A64_V 0  1  1 01110  00 11000 01111 10 rn:5 rd:5
+FMINNMV      A64_V 0  1  1 01110  10 11000 01100 10 rn:5 rd:5
+FMINV        A64_V 0  1  1 01110  10 11000 01111 10 rn:5 rd:5
+
+# ARMv8.2 Half-precision variants
+FMAXNMV_FP16 A64_V 0 q:1 0 01110  00 11000 01100 10 rn:5 rd:5
+FMAXV_FP16   A64_V 0 q:1 0 01110  00 11000 01111 10 rn:5 rd:5
+FMINNMV_FP16 A64_V 0 q:1 0 01110  10 11000 01100 10 rn:5 rd:5
+FMINV_FP16   A64_V 0 q:1 0 01110  10 11000 01111 10 rn:5 rd:5
+
+SADDLV       A64_V 0 Q:1 0 01110 s:2 11000 00011 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+SADDLV_RES   A64_V 0   0 0 01110  10 11000 00011 10 rn:5 rd:5
+
+SMAXV        A64_V 0 Q:1 0 01110 s:2 11000 01010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+SMAXV_RES    A64_V 0   0 0 01110  10 11000 01010 10 rn:5 rd:5
+
+SMINV        A64_V 0 Q:1 0 01110 s:2 11000 11010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+SMINV_RES    A64_V 0   0 0 01110  10 11000 11010 10 rn:5 rd:5
+
+UADDLV       A64_V 0 Q:1 1 01110 s:2 11000 00011 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+UADDLV_RES   A64_V 0   0 1 01110  10 11000 00011 10 rn:5 rd:5
+
+UMAXV        A64_V 0 Q:1 1 01110 s:2 11000 01010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+UMAXV_RES    A64_V 0   0 1 01110  10 11000 01010 10 rn:5 rd:5
+
+UMINV        A64_V 0 Q:1 1 01110 s:2 11000 11010 10 rn:5 rd:5 \
+!constraints { $s < 2 || ($s == 2 && $Q == 1); }
+# ReservedValue: break the constraint (s==2) => (Q=1)
+UMINV_RES    A64_V 0   0 1 01110  10 11000 11010 10 rn:5 rd:5
 
-SADDLV A64_V 0 Q:1 0 01110 size:2 11000 00011 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-SADDLV_RES A64_V 0 0 0 01110 10 11000 00011 10 rn:5 rd:5
-
-SMAXV A64_V 0 Q:1 0 01110 size:2 11000 01010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-SMAXV_RES A64_V 0 0 0 01110 10 11000 01010 10 rn:5 rd:5
-
-SMINV A64_V 0 Q:1 0 01110 size:2 11000 11010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-SMINV_RES A64_V 0 0 0 01110 10 11000 11010 10 rn:5 rd:5
-
-ADDV A64_V 0 Q:1 0 01110 size:2 11000 11011 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-ADDV_RES A64_V 0 0 0 01110 10 11000 11011 10 rn:5 rd:5
-
-UADDLV A64_V 0 Q:1 1 01110 size:2 11000 00011 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-UADDLV_RES A64_V 0 0 1 01110 10 11000 00011 10 rn:5 rd:5
-
-UMAXV A64_V 0 Q:1 1 01110 size:2 11000 01010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-UMAXV_RES A64_V 0 0 1 01110 10 11000 01010 10 rn:5 rd:5
-
-UMINV A64_V 0 Q:1 1 01110 size:2 11000 11010 10 rn:5 rd:5 \
-!constraints { $size < 2 || ($size == 2 && $Q == 1); }
-# ReservedValue: break the constraint (size==2) => (Q=1)
-UMINV_RES A64_V 0 0 1 01110 10 11000 11010 10 rn:5 rd:5
-
-FMAXNMV A64_V 0 1 1 01110 00 11000 01100 10 rn:5 rd:5
-FMAXV A64_V 0 1 1 01110 00 11000 01111 10 rn:5 rd:5
-
-FMINNMV A64_V 0 1 1 01110 10 11000 01100 10 rn:5 rd:5
-FMINV A64_V 0 1 1 01110 10 11000 01111 10 rn:5 rd:5
+@
 
 # C3.6.5 AdvSIMD copy
 # 31 30 29 28 27 26 25 24 23 22 21 20    16 15 14    11 10 9  5 4  0
-- 
2.13.0

Re: [Qemu-devel] [RISU PATCH 00/11] Misc fixes, documentation and patterns

[Peter Maydell]

On 4 July 2017 at 15:48, Alex Bennée <alex.bennee@linaro.org> wrote:
> Hi Peter,
>
> A bit of a mixed set of patches here for you to pick from as you
> will. The first 2 are additional tracing fixes including a fix for
> segfaulting when generating a trace.
>
> The next two are documentation patches as requested.
>
> Then two minor tweaks, one to risu.el and a indent failure of risugen.
>
> While I've been working through the half-precision stuff I've been
> finding the --pattern approach a bit inflexible as you basically end
> up eyeballing the risu file to build up the regexs. I've added a
> little syntactic suger to the risu file to enable grouping. This makes
> slicing a subset a lot easier, e.g.:
>
>   ./risugen --group AdvSIMDAcrossVector --not-pattern ".*_RES" aarch64.risu
>
> You can specify multiple groups in the risu file as the matching is
> string based, e.g.:
>
>   @Integer,Logic,Immediate
>
> And then:
>
>   ./risugen --group Logic aarch64.risu foo.bin
>
> What do you think?
>
> Alex Bennée (11):
>   risu: make match status take tracing into account
>   reginfo.c: always return 1 on OP_TESTEND
>   README: document --static builds
>   README: document record/replay support
>   risu.el: derive from text-mode
>   risugen: fix bad indent

I've pushed these first six to risu master.

>   risugen: support @GroupName in risu files

I think this is OK, but can we document the change in
risu file syntax in the readme, please?

>   aarch64.risu: document naming conventions
>   aarch64.risu: remove duplicate AdvSIMD Scalar 3 same block
>   aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc block
>   aarch64.risu: update AdvancedSIMD across lanes

Some of these seem to be doing multiple things at once,
which in some cases makes them a bit confusing (eg the
first one says it's removing a duplicate block, but it's
also adding a group name.)

thanks
-- PMM