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From: Peter Zijlstra <peterz@infradead.org>
To: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Borislav Petkov <bp@alien8.de>,
	x86@kernel.org, linux-kernel@vger.kernel.org, leo.duran@amd.com,
	yazen.ghannam@amd.com
Subject: Re: [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket
Date: Wed, 5 Jul 2017 17:50:53 +0200	[thread overview]
Message-ID: <20170705155053.jucdvggtxxczzkba@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <bb167d94-828b-2d5b-642a-d56e8db392d0@amd.com>

On Tue, Jun 27, 2017 at 08:07:10PM +0700, Suravee Suthikulpanit wrote:

> As I have described in the cover letter, this patch series changes how

Which you didn't send to me... thanks for that.

> kernel derives cpu "package" from package-as-socket to package-as-die in
> order to fix following issues on AMD family17h multi-die processor
> platforms:

> These issues are fixed when properly intepretes package as DIE.
> 
> For MCM Magny-Cours (family15h), we do not have this issue because the MC
> sched-domain has the same cpumask as the DIE sched-domain. This is not the
> same as for Zen cores (family17h) where the MC sched-domain is the CCX (2
> CCX per die)

Are you saying that your LLCs are smaller than your NUMA nodes ? You do
not in fact have a cache level that spans the memory controller?

Because that is indeed the assumption we have for Intel CoD/SnC and AMD
Magny-Cours.

  parent reply	other threads:[~2017-07-05 15:51 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-27  6:40 [PATCH 0/2] x86/CPU/AMD: Fix multi-die processor topology info Suravee Suthikulpanit
2017-06-27  6:40 ` [PATCH 1/2] x86/CPU/AMD: Present package as die instead of socket Suravee Suthikulpanit
2017-06-27 10:48   ` Borislav Petkov
2017-06-27 13:07     ` Suravee Suthikulpanit
2017-06-27 13:42       ` Borislav Petkov
2017-06-27 16:54         ` Suravee Suthikulpanit
2017-06-27 17:44           ` Borislav Petkov
2017-06-27 18:32             ` Ghannam, Yazen
2017-06-27 18:44               ` Borislav Petkov
2017-06-27 20:26             ` Suravee Suthikulpanit
2017-06-28  9:12               ` Borislav Petkov
2017-06-27 14:21       ` Thomas Gleixner
2017-06-27 14:54         ` Brice Goglin
2017-06-27 15:48         ` Duran, Leo
2017-06-27 16:11           ` Borislav Petkov
2017-06-27 16:23             ` Duran, Leo
2017-06-27 16:31               ` Borislav Petkov
2017-06-27 16:42                 ` Duran, Leo
2017-06-27 16:45                   ` Borislav Petkov
2017-06-27 17:04                     ` Duran, Leo
2017-06-27 16:19           ` Thomas Gleixner
2017-06-27 16:34             ` Duran, Leo
2017-06-27 15:55         ` Suravee Suthikulpanit
2017-06-27 16:16           ` Borislav Petkov
2017-07-05 15:50       ` Peter Zijlstra [this message]
2017-06-27  6:40 ` [PATCH 2/2] x86/CPU/AMD: Use L3 Cache info from CPUID to determine LLC ID Suravee Suthikulpanit

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