From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com ([209.132.183.28]:56464 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753040AbdGHUC7 (ORCPT ); Sat, 8 Jul 2017 16:02:59 -0400 Date: Sat, 8 Jul 2017 14:02:57 -0600 From: Alex Williamson To: valmiki Cc: iommu@lists.linux-foundation.org, kvm@vger.kernel.org, linux-pci@vger.kernel.org, jean-Philippe Brucker , tianyu.lan@intel.com, kevin.tian@intel.com, jacob.jun.pan@intel.com Subject: Re: Support SVM without PASID Message-ID: <20170708140257.2de02d63@w520.home> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-pci-owner@vger.kernel.org List-ID: On Sat, 8 Jul 2017 22:33:01 +0530 valmiki wrote: > Hi, > > In SMMUv3 architecture document i see "PASIDs are optional, > configurable, and of a size determined by the minimum > of the endpoint". > > So if PASID's are optional and not supported by PCIe end point, how SVM > can be achieved ? It cannot be inferred from that statement that PASID support is not required for SVM. AIUI, SVM is a software feature enabled by numerous "optional" hardware features, including PASID. Features that are optional per the hardware specification may be required for specific software features. Thanks, Alex From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex Williamson Subject: Re: Support SVM without PASID Date: Sat, 8 Jul 2017 14:02:57 -0600 Message-ID: <20170708140257.2de02d63@w520.home> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: tianyu.lan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, jacob.jun.pan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org To: valmiki Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org List-Id: kvm.vger.kernel.org On Sat, 8 Jul 2017 22:33:01 +0530 valmiki wrote: > Hi, > > In SMMUv3 architecture document i see "PASIDs are optional, > configurable, and of a size determined by the minimum > of the endpoint". > > So if PASID's are optional and not supported by PCIe end point, how SVM > can be achieved ? It cannot be inferred from that statement that PASID support is not required for SVM. AIUI, SVM is a software feature enabled by numerous "optional" hardware features, including PASID. Features that are optional per the hardware specification may be required for specific software features. Thanks, Alex