All of lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Axtens <dja@axtens.net>
To: linux-pci@vger.kernel.org
Cc: Daniel Axtens <dja@axtens.net>,
	Xinliang Liu <z.liuxinliang@hisilicon.com>,
	Rongrong Zou <zourongrong@gmail.com>
Subject: [PATCH v4] PCI: Support hibmc VGA cards behind a misbehaving HiSilicon bridge
Date: Wed, 12 Jul 2017 15:08:11 +1000	[thread overview]
Message-ID: <20170712050811.3620-1-dja@axtens.net> (raw)

The HiSilicon D05 board has some PCI bridges (PCI ID 19e5:1610) that
are not spec-compliant: the VGA Enable bit is hardwired to 0 and
writes do not change it.

The HiSilicon engineers report that the bridge does not forward the
0xa0000-0xbffff mem range and the 0x3b0-0x3bb and 0x3c0-0x3df I/O
ranges.

Because the VGA Enable bit is hardwired to 0, the VGA arbiter refuses
to mark any card behind it as the boot device. This breaks Xorg
auto-detection.

However, the hibmc VGA card (PCI ID 19e5:1711) has been tested and is
known to work when behind these bridges. (It does not require the
legacy resources to operate.)

Provide a quirk so that this combination of bridge and card is eligible
to be the default VGA card. This fixes Xorg auto-detection on the D05.

Cc: Xinliang Liu <z.liuxinliang@hisilicon.com>
Cc: Rongrong Zou <zourongrong@gmail.com>
Signed-off-by: Daniel Axtens <dja@axtens.net>
---

v3: fix commit message
v4: fix comment (forgot to git add/git commit, sorry for the noise)

---
 drivers/pci/quirks.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 16e6cd86ad71..b42324cba29e 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -25,6 +25,7 @@
 #include <linux/sched.h>
 #include <linux/ktime.h>
 #include <linux/mm.h>
+#include <linux/vgaarb.h>
 #include <asm/dma.h>	/* isa_dma_bridge_buggy */
 #include "pci.h"
 
@@ -4664,3 +4665,52 @@ static void quirk_intel_no_flr(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
+
+/*
+ * The HiSilicon D05 board has some PCI bridges (PCI ID 19e5:1610)
+ * that are not spec-compliant: the VGA Enable bit is hardwired to 0
+ * and writes do not change it. The bridge does not forward legacy
+ * memory or I/O resources.
+ *
+ * Because the VGA Enable bit is hardwired to 0, the VGA arbiter
+ * refuses to mark any card behind it as the boot device. However, the
+ * hibmc VGA card (PCI ID 19e5:1711) has been tested and is known to
+ * work when behind these bridges.
+ *
+ * If we have this bridge, this card, and no default card already,
+ * mark the card as default.
+ */
+static void hibmc_fixup_vgaarb(struct pci_dev *pdev)
+{
+	struct pci_dev *bridge;
+	struct pci_bus *bus;
+	u16 config;
+
+	bus = pdev->bus;
+	bridge = bus->self;
+	if (!bridge)
+		return;
+
+	if (!pci_is_bridge(bridge))
+		return;
+
+	if (bridge->vendor != PCI_VENDOR_ID_HUAWEI ||
+	    bridge->device != 0x1610)
+		return;
+
+	pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
+			     &config);
+	if (config & PCI_BRIDGE_CTL_VGA) {
+		/*
+		 * Weirdly, this bridge *is* spec compliant, so bail
+		 * and let vgaarb do its job
+		 */
+		return;
+	}
+
+	if (vga_default_device())
+		return;
+
+	vga_set_default_device(pdev);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1711, hibmc_fixup_vgaarb);
-- 
2.11.0

             reply	other threads:[~2017-07-12  5:11 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-12  5:08 Daniel Axtens [this message]
2017-07-12 20:04 ` [PATCH v4] PCI: Support hibmc VGA cards behind a misbehaving HiSilicon bridge Bjorn Helgaas
2017-07-12 20:04   ` Bjorn Helgaas
2017-07-13 10:29   ` Gabriele Paoloni
2017-07-13 10:29     ` Gabriele Paoloni
2017-07-13 11:29     ` Bjorn Helgaas
2017-07-13 11:29       ` Bjorn Helgaas
2017-07-13 20:45       ` Benjamin Herrenschmidt
2017-07-13 20:45         ` Benjamin Herrenschmidt
2017-07-14 12:14         ` Gabriele Paoloni
2017-07-14 12:14           ` Gabriele Paoloni
2017-07-13 21:11       ` Alex Williamson
2017-07-13 21:11         ` Alex Williamson
2017-07-13 21:21         ` Benjamin Herrenschmidt
2017-07-13 21:21           ` Benjamin Herrenschmidt
2017-07-14 12:26           ` Gabriele Paoloni
2017-07-14 12:26             ` Gabriele Paoloni
2017-07-14 13:50             ` Benjamin Herrenschmidt
2017-07-14 13:50               ` Benjamin Herrenschmidt
2017-07-14 17:03               ` Gabriele Paoloni
2017-07-14 17:03                 ` Gabriele Paoloni
2017-07-14 23:54                 ` Benjamin Herrenschmidt
2017-07-14 23:54                   ` Benjamin Herrenschmidt
2017-07-14 14:43             ` Alex Williamson
2017-07-14 14:43               ` Alex Williamson
2017-07-14  1:35   ` Will Deacon
2017-07-14  1:35     ` Will Deacon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170712050811.3620-1-dja@axtens.net \
    --to=dja@axtens.net \
    --cc=linux-pci@vger.kernel.org \
    --cc=z.liuxinliang@hisilicon.com \
    --cc=zourongrong@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.