From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753768AbdGSJas (ORCPT ); Wed, 19 Jul 2017 05:30:48 -0400 Received: from mx1.redhat.com ([209.132.183.28]:34546 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753571AbdGSJao (ORCPT ); Wed, 19 Jul 2017 05:30:44 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 923915D686 Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx10.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=rkrcmar@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 923915D686 Date: Wed, 19 Jul 2017 11:30:37 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Bandan Das Cc: David Hildenbrand , kvm@vger.kernel.org, pbonzini@redhat.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 3/3] KVM: nVMX: Emulate EPTP switching for the L1 hypervisor Message-ID: <20170719093036.GA13079@potion> References: <20170710204936.4001-1-bsd@redhat.com> <20170710204936.4001-4-bsd@redhat.com> <2d50ebc4-9328-ce08-b55b-6a331ee13cc3@redhat.com> <20170711193235.GE3326@potion> <20170711202118.GC28875@potion> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Wed, 19 Jul 2017 09:30:44 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-07-17 13:58-0400, Bandan Das: > Radim Krčmář writes: > ... >>> > and no other mentions of a VM exit, so I think that the VM exit happens >>> > only under these conditions: >>> > >>> > — The EPT memory type (bits 2:0) must be a value supported by the >>> > processor as indicated in the IA32_VMX_EPT_VPID_CAP MSR (see >>> > Appendix A.10). >>> > — Bits 5:3 (1 less than the EPT page-walk length) must be 3, indicating >>> > an EPT page-walk length of 4; see Section 28.2.2. >>> > — Bit 6 (enable bit for accessed and dirty flags for EPT) must be 0 if >>> > bit 21 of the IA32_VMX_EPT_VPID_CAP MSR (see Appendix A.10) is read >>> > as 0, indicating that the processor does not support accessed and >>> > dirty flags for EPT. >>> > — Reserved bits 11:7 and 63:N (where N is the processor’s >>> > physical-address width) must all be 0. >>> > >>> > And it looks like we need parts of nested_ept_init_mmu_context() to >>> > properly handle VMX_EPT_AD_ENABLE_BIT. >>> >>> I completely ignored AD and the #VE sections. I will add a TODO item >>> in the comment section. >> >> AFAIK, we don't support #VE, but AD would be nice to handle from the >> beginning. (I think that caling nested_ept_init_mmu_context() as-is >> isn't that bad.) > > I went back to the spec to take a look at the AD handling. It doesn't look > like anything needs to be done since nested_ept_init_mmu_context() is already > being called with the correct eptp in prepare_vmcs02 ? Anything else that > needs to be done for AD handling in vmfunc context ? AD is decided by EPTP bit 6, so it can be toggled by EPTP switching and we don't call prepare_vmcs02() after emulating VMFUNC vm exit. We want to forward the new AD configuration to KVM's MMU.