From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933485AbdGSPb5 (ORCPT ); Wed, 19 Jul 2017 11:31:57 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:40393 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933360AbdGSPbv (ORCPT ); Wed, 19 Jul 2017 11:31:51 -0400 From: Gregory CLEMENT To: Boris Brezillon , Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT Cc: Richard Weinberger , David Woodhouse , Brian Norris , Marek Vasut , Cyrille Pitchen , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Antoine Tenart , =?UTF-8?q?Miqu=C3=A8l=20Raynal?= , Nadav Haklai , Shadi Ammouri , Yehuda Yitschak , Omri Itach , Hanna Hawa , Igal Liberman , Marcin Wojtas Subject: [PATCH 2/2] ARM64: dts: marvell: add NAND support on the CP110 master Date: Wed, 19 Jul 2017 17:31:26 +0200 Message-Id: <20170719153126.16905-3-gregory.clement@free-electrons.com> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170719153126.16905-1-gregory.clement@free-electrons.com> References: <20170719153126.16905-1-gregory.clement@free-electrons.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The NAND controller used in A7K/A8K is present on the CP110 master part. It is compatible with the pxa-nand driver. Unlike most of the controller on the CP110 this one is only present on the master for the Armada 8K SoCs. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 726528ce54e9..9be4a442ded5 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -240,6 +240,20 @@ status = "disabled"; }; + cpm_nand: nand@720000 { + /* + * For A7K/A8K this controller is only + * present on the CPM and not on the CPS + */ + compatible = "marvell,armada370-nand"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&cpm_clk 1 2>; + status = "disabled"; + }; + cpm_trng: trng@760000 { compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; -- 2.13.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: gregory.clement@free-electrons.com (Gregory CLEMENT) Date: Wed, 19 Jul 2017 17:31:26 +0200 Subject: [PATCH 2/2] ARM64: dts: marvell: add NAND support on the CP110 master In-Reply-To: <20170719153126.16905-1-gregory.clement@free-electrons.com> References: <20170719153126.16905-1-gregory.clement@free-electrons.com> Message-ID: <20170719153126.16905-3-gregory.clement@free-electrons.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org The NAND controller used in A7K/A8K is present on the CP110 master part. It is compatible with the pxa-nand driver. Unlike most of the controller on the CP110 this one is only present on the master for the Armada 8K SoCs. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 726528ce54e9..9be4a442ded5 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -240,6 +240,20 @@ status = "disabled"; }; + cpm_nand: nand at 720000 { + /* + * For A7K/A8K this controller is only + * present on the CPM and not on the CPS + */ + compatible = "marvell,armada370-nand"; + reg = <0x720000 0x54>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + clocks = <&cpm_clk 1 2>; + status = "disabled"; + }; + cpm_trng: trng at 760000 { compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; -- 2.13.2