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Date: Fri, 21 Jul 2017 19:43:03 +0200
From: Aurelien Jarno <aurelien@aurel32.net>
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Subject: Re: [Qemu-devel] [RFC PATCH for 2.11 12/23]
 target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alex =?iso-8859-15?Q?Benn=E9e?= <alex.bennee@linaro.org>, Richard Henderson <rth@twiddle.net>, qemu-arm <qemu-arm@nongnu.org>, QEMU Developers <qemu-devel@nongnu.org>

On 2017-07-21 14:58, Peter Maydell wrote:
> On 21 July 2017 at 14:50, Alex Benn=E9e <alex.bennee@linaro.org> wrote:
> > Aurelien Jarno <aurelien@aurel32.net> writes:
> >> As said in another email, some architectures actually use more than one
> >> float_status. We therefore need to implement a solution like the one
> >> proposed by Richard.
> >
> > Ahh you mean more than one float_status for a given vCPU context?
>=20
> Yep. ARM's cpu state struct has
>         float_status fp_status;
>         float_status standard_fp_status;
>=20
> which we use to handle (1) operations which use the state
> controlled by the FPSCR value and (2) operations which
> ignore the FPSCR and use the "Standard FPSCR Value" (generally
> Neon ops). More info in the comment in cpu.h...

Indeed. This is also the case on:
- i386: one float_status for the x87 FPU, one for MMX and one for SSE.
- mips: one for the FPU and one for the MSA FP (SIMD operations).
- ppc: one for the FPU instructions and one for the VEC instructions.

Aurelien

--=20
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net