From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Sun, 30 Jul 2017 14:13:45 +0200 Subject: [U-Boot] [PATCH v5 08/10] mips: bmips: add bcm63xx-spi driver support for BCM63268 In-Reply-To: <20170730121347.30494-1-noltari@gmail.com> References: <1495135788-9152-1-git-send-email-noltari@gmail.com> <20170730121347.30494-1-noltari@gmail.com> Message-ID: <20170730121347.30494-9-noltari@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de This driver manages the low speed SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas Reviewed-by: Daniel Schwierzeck --- v5: no changes v4: no changes v3: no changes v2: add spi alias arch/mips/dts/brcm,bcm63268.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 113a96bef8..6e3d9c3820 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -13,6 +13,10 @@ / { compatible = "brcm,bcm63268"; + aliases { + spi0 = &lsspi; + }; + cpus { reg = <0x10000000 0x4>; #address-cells = <1>; @@ -136,6 +140,19 @@ #power-domain-cells = <1>; }; + lsspi: spi at 10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_SPI>; + resets = <&periph_rst BCM63268_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + leds: led-controller at 10001900 { compatible = "brcm,bcm6328-leds"; reg = <0x10001900 0x24>; -- 2.11.0