From mboxrd@z Thu Jan 1 00:00:00 1970 From: jmondi Subject: Re: [PATCH 3/4] arm: dts: gr-peach: Add ETHER pin group Date: Thu, 24 Aug 2017 13:46:56 +0200 Message-ID: <20170824114656.GA3905@w540> References: <1503564523-31899-1-git-send-email-jacopo+renesas@jmondi.org> <1503564523-31899-4-git-send-email-jacopo+renesas@jmondi.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-renesas-soc-owner@vger.kernel.org To: Geert Uytterhoeven Cc: Jacopo Mondi , Simon Horman , Magnus Damm , Rob Herring , Mark Rutland , Russell King , Linux-Renesas , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: devicetree@vger.kernel.org Hi Geert, On Thu, Aug 24, 2017 at 11:48:14AM +0200, Geert Uytterhoeven wrote: > Hi Jacopo, > > On Thu, Aug 24, 2017 at 10:48 AM, Jacopo Mondi > wrote: > > Add pin configuration subnode for ETHER pin group. > > The interface can be configured and probed, but no traffic can be > > transmitted or received. > > > > Signed-off-by: Jacopo Mondi > > > > --- > > When in u-boot console I can ping a connected host, after the > > system has booted I can configure an ip address on the interface but > > cannot exchange any traffic. > > I have compared the pin configuration procedure with the u-boot > > implemented one and some sketches from mbed operating system libraries, > > the configured pins are correct and registers values seems to match. > > Not sure if this patch should be sent for inclusion but sending it out > > anyway for you to judge this. > > > > Thanks > > j > > --- > > arch/arm/boot/dts/r7s72100-gr-peach.dts | 35 +++++++++++++++++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > > > diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts > > index bcfa644..5ce558f 100644 > > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts > > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts > > @@ -58,6 +58,28 @@ > > /* P6_2 as RxD2; P6_3 as TxD2 */ > > pinmux = , ; > > }; > > + > > + ether_pins: ether { > > + /* Ethernet on Ports 1,3,5,10 */ > > + pinmux = , /* P1_14 = ET_COL */ > > + , /* P3_0 = ET_TXCLK */ > > + , /* P3_3 = ET_MDIO */ > > + , /* P3_4 = ET_RXCLK */ > > + , /* P3_5 = ET_RXER */ > > + , /* P3_6 = ET_RXDV */ > > + , /* P5_9 = ET_MDC */ > > + , /* P10_1 = ET_TXER */ > > + , /* P10_2 = ET_TXEN */ > > + , /* P10_3 = ET_CRS */ > > + , /* P10_4 = ET_TXD0 */ > > + , /* P10_5 = ET_TXD1 */ > > + , /* P10_6 = ET_TXD2 */ > > + , /* P10_7 = ET_TXD3 */ > > + , /* P10_8 = ET_RXD0 */ > > + , /* P10_9 = ET_RXD1 */ > > + ,/* P10_10 = ET_RXD2 */ > > + ;/* P10_11 = ET_RXD3 */ > > All OK, but do you need P4_2, which is used for ET_nRST? I tried requesting the GPIO in the "ether" subnode and define it as "active low", so that it is kept high during regular operations. I have verified through register writes dump it is cycled just after the gpio is requested, and this should reset the interface before the actual sh_eth driver kicks in. I haven't find any mention in device tree bindings documentation of a "reset-gpio" property for sh_eth, in the code examples I've seen in u-boot and mbed, the interface is reset before any actual configuration is performed. I feel like that should be the place where that gpio is requested and cycled... Thanks j > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds From mboxrd@z Thu Jan 1 00:00:00 1970 From: jacopo@jmondi.org (jmondi) Date: Thu, 24 Aug 2017 13:46:56 +0200 Subject: [PATCH 3/4] arm: dts: gr-peach: Add ETHER pin group In-Reply-To: References: <1503564523-31899-1-git-send-email-jacopo+renesas@jmondi.org> <1503564523-31899-4-git-send-email-jacopo+renesas@jmondi.org> Message-ID: <20170824114656.GA3905@w540> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Geert, On Thu, Aug 24, 2017 at 11:48:14AM +0200, Geert Uytterhoeven wrote: > Hi Jacopo, > > On Thu, Aug 24, 2017 at 10:48 AM, Jacopo Mondi > wrote: > > Add pin configuration subnode for ETHER pin group. > > The interface can be configured and probed, but no traffic can be > > transmitted or received. > > > > Signed-off-by: Jacopo Mondi > > > > --- > > When in u-boot console I can ping a connected host, after the > > system has booted I can configure an ip address on the interface but > > cannot exchange any traffic. > > I have compared the pin configuration procedure with the u-boot > > implemented one and some sketches from mbed operating system libraries, > > the configured pins are correct and registers values seems to match. > > Not sure if this patch should be sent for inclusion but sending it out > > anyway for you to judge this. > > > > Thanks > > j > > --- > > arch/arm/boot/dts/r7s72100-gr-peach.dts | 35 +++++++++++++++++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > > > diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts > > index bcfa644..5ce558f 100644 > > --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts > > +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts > > @@ -58,6 +58,28 @@ > > /* P6_2 as RxD2; P6_3 as TxD2 */ > > pinmux = , ; > > }; > > + > > + ether_pins: ether { > > + /* Ethernet on Ports 1,3,5,10 */ > > + pinmux = , /* P1_14 = ET_COL */ > > + , /* P3_0 = ET_TXCLK */ > > + , /* P3_3 = ET_MDIO */ > > + , /* P3_4 = ET_RXCLK */ > > + , /* P3_5 = ET_RXER */ > > + , /* P3_6 = ET_RXDV */ > > + , /* P5_9 = ET_MDC */ > > + , /* P10_1 = ET_TXER */ > > + , /* P10_2 = ET_TXEN */ > > + , /* P10_3 = ET_CRS */ > > + , /* P10_4 = ET_TXD0 */ > > + , /* P10_5 = ET_TXD1 */ > > + , /* P10_6 = ET_TXD2 */ > > + , /* P10_7 = ET_TXD3 */ > > + , /* P10_8 = ET_RXD0 */ > > + , /* P10_9 = ET_RXD1 */ > > + ,/* P10_10 = ET_RXD2 */ > > + ;/* P10_11 = ET_RXD3 */ > > All OK, but do you need P4_2, which is used for ET_nRST? I tried requesting the GPIO in the "ether" subnode and define it as "active low", so that it is kept high during regular operations. I have verified through register writes dump it is cycled just after the gpio is requested, and this should reset the interface before the actual sh_eth driver kicks in. I haven't find any mention in device tree bindings documentation of a "reset-gpio" property for sh_eth, in the code examples I've seen in u-boot and mbed, the interface is reset before any actual configuration is performed. I feel like that should be the place where that gpio is requested and cycled... Thanks j > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds