* [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU
@ 2017-08-28 1:56 Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script Sergio Andres Gomez Del Real
` (16 more replies)
0 siblings, 17 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
The following patchset adds to QEMU the supporting for macOS's native
hypervisor, Hypervisor.framework (hvf). The code base is taken from
Google's Android emulator at
https://android.googlesource.com/platform/external/qemu/+/emu-master-dev.
Apart from general code refactoring, some additional features were implemented:
retrieve the set of features supported by host cpu and hvf (cpuid);
dirty page tracking for VGA memory area; reimplementation of the event
injection mechanism to allow injection of exceptions during vmexits, which is
exemplified by the injection of a GP fault when the guest vmexits due to
execution of the vmcall instruction; changing the emulator's use of CPUState
structure in favor of CPUX86State, so as to in the future remove data structures
that are uselessly specific to hvf and unified some of the state between kvm/tcg
and hvf.
Some features initially planned to implement that didn't make it include:
page fault handling in the emulator and implementing the dummy_signal to handle
the SIG_IPI signal without race conditions. Hopefully these can be implemented
in the near future.
Sergio Andres Gomez Del Real (14):
hvf: add support for Hypervisor.framework in the configure script
hvf: add code base from Google's QEMU repository
hvf: add conditional macros around hvf code in cpus.c
hvf: add fields to CPUState and CPUX86State; add definitions
hvf: use new helper functions for put/get xsave
hvf: add compilation rules to Makefile.objs
hvf: run hvf code through checkpatch.pl and fix style issues
apic: add function to apic that will be used by hvf
hvf: implement hvf_get_supported_cpuid
hvf: refactor cpuid code
hvf: implement vga dirty page tracking
hvf: move fields from CPUState to CPUX86State
hvf: refactor event injection code for hvf
hvf: inject General Protection Fault when vmexit through vmcall
configure | 32 +
cpus.c | 107 +-
hw/intc/apic.c | 11 +
include/hw/i386/apic.h | 1 +
include/qom/cpu.h | 2 +
include/sysemu/hvf.h | 106 ++
qemu-options.hx | 20 +-
target/i386/Makefile.objs | 1 +
target/i386/cpu-qom.h | 4 +-
target/i386/cpu.c | 111 +-
target/i386/cpu.h | 30 +
target/i386/hvf-all.c | 1123 ++++++++++++++++++
target/i386/hvf-i386.h | 48 +
target/i386/hvf-utils/Makefile.objs | 1 +
target/i386/hvf-utils/README.md | 7 +
target/i386/hvf-utils/vmcs.h | 371 ++++++
target/i386/hvf-utils/vmx.h | 222 ++++
target/i386/hvf-utils/x86.c | 184 +++
target/i386/hvf-utils/x86.h | 476 ++++++++
target/i386/hvf-utils/x86_cpuid.c | 417 +++++++
target/i386/hvf-utils/x86_cpuid.h | 52 +
target/i386/hvf-utils/x86_decode.c | 2186 +++++++++++++++++++++++++++++++++++
target/i386/hvf-utils/x86_decode.h | 325 ++++++
target/i386/hvf-utils/x86_descr.c | 124 ++
target/i386/hvf-utils/x86_descr.h | 55 +
target/i386/hvf-utils/x86_emu.c | 1536 ++++++++++++++++++++++++
target/i386/hvf-utils/x86_emu.h | 32 +
target/i386/hvf-utils/x86_flags.c | 333 ++++++
target/i386/hvf-utils/x86_flags.h | 243 ++++
target/i386/hvf-utils/x86_gen.h | 36 +
target/i386/hvf-utils/x86_mmu.c | 273 +++++
target/i386/hvf-utils/x86_mmu.h | 28 +
target/i386/hvf-utils/x86hvf.c | 463 ++++++++
target/i386/hvf-utils/x86hvf.h | 22 +
target/i386/kvm.c | 2 -
vl.c | 7 +
36 files changed, 8957 insertions(+), 34 deletions(-)
create mode 100644 include/sysemu/hvf.h
create mode 100644 target/i386/hvf-all.c
create mode 100644 target/i386/hvf-i386.h
create mode 100644 target/i386/hvf-utils/Makefile.objs
create mode 100644 target/i386/hvf-utils/README.md
create mode 100644 target/i386/hvf-utils/vmcs.h
create mode 100644 target/i386/hvf-utils/vmx.h
create mode 100644 target/i386/hvf-utils/x86.c
create mode 100644 target/i386/hvf-utils/x86.h
create mode 100644 target/i386/hvf-utils/x86_cpuid.c
create mode 100644 target/i386/hvf-utils/x86_cpuid.h
create mode 100644 target/i386/hvf-utils/x86_decode.c
create mode 100644 target/i386/hvf-utils/x86_decode.h
create mode 100644 target/i386/hvf-utils/x86_descr.c
create mode 100644 target/i386/hvf-utils/x86_descr.h
create mode 100644 target/i386/hvf-utils/x86_emu.c
create mode 100644 target/i386/hvf-utils/x86_emu.h
create mode 100644 target/i386/hvf-utils/x86_flags.c
create mode 100644 target/i386/hvf-utils/x86_flags.h
create mode 100644 target/i386/hvf-utils/x86_gen.h
create mode 100644 target/i386/hvf-utils/x86_mmu.c
create mode 100644 target/i386/hvf-utils/x86_mmu.h
create mode 100644 target/i386/hvf-utils/x86hvf.c
create mode 100644 target/i386/hvf-utils/x86hvf.h
--
2.14.1
Subject: [PATCH 00/15]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:00 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository Sergio Andres Gomez Del Real
` (15 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This patch adds to the configure script the code to support the
--enable-hvf argument. If the OS is Darwin, it checks for presence of
HVF in the system. The patch also adds strings related to HVF in the
file qemu-options.hx
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
configure | 32 ++++++++++++++++++++++++++++++++
qemu-options.hx | 20 +++++++++++++++-----
2 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/configure b/configure
index dd73cce62f..d9126462a1 100755
--- a/configure
+++ b/configure
@@ -309,6 +309,7 @@ vhost_vsock="no"
vhost_user=""
kvm="no"
hax="no"
+hvf="no"
rdma=""
gprof="no"
debug_tcg="no"
@@ -727,6 +728,7 @@ Darwin)
bsd="yes"
darwin="yes"
hax="yes"
+ hvf="yes"
LDFLAGS_SHARED="-bundle -undefined dynamic_lookup"
if [ "$cpu" = "x86_64" ] ; then
QEMU_CFLAGS="-arch x86_64 $QEMU_CFLAGS"
@@ -1027,6 +1029,10 @@ for opt do
;;
--enable-hax) hax="yes"
;;
+ --disable-hvf) hvf="no"
+ ;;
+ --enable-hvf) hvf="yes"
+ ;;
--disable-tcg-interpreter) tcg_interpreter="no"
;;
--enable-tcg-interpreter) tcg_interpreter="yes"
@@ -1499,6 +1505,7 @@ disabled with --disable-FEATURE, default is enabled if available:
bluez bluez stack connectivity
kvm KVM acceleration support
hax HAX acceleration support
+ hvf Hypervisor.framework acceleration support
rdma RDMA-based migration support
vde support for vde network
netmap support for netmap network
@@ -4900,6 +4907,21 @@ then
fi
+#################################################
+# Check to see if we have the Hypervisor framework
+if [ "$darwin" == "yes" ] ; then
+ cat > $TMPC << EOF
+#include <Hypervisor/hv.h>
+int main() { return 0;}
+EOF
+ if ! compile_object ""; then
+ hvf='no'
+ else
+ hvf='yes'
+ LDFLAGS="-framework Hypervisor $LDFLAGS"
+ fi
+fi
+
#################################################
# Sparc implicitly links with --relax, which is
# incompatible with -r, so --no-relax should be
@@ -5356,6 +5378,7 @@ if test "$tcg" = "yes" ; then
echo "TCG debug enabled $debug_tcg"
echo "TCG interpreter $tcg_interpreter"
fi
+echo "HVF support $hvf"
echo "RDMA support $rdma"
echo "fdt support $fdt"
echo "preadv support $preadv"
@@ -6388,6 +6411,15 @@ fi
if supported_hax_target $target; then
echo "CONFIG_HAX=y" >> $config_target_mak
fi
+if test "$hvf" = "yes" ; then
+ if test "$target_softmmu" = "yes" ; then
+ case "$target_name" in
+ i386|x86_64)
+ echo "CONFIG_HVF=y" >> $config_target_mak
+ ;;
+ esac
+ fi
+fi
if test "$target_bigendian" = "yes" ; then
echo "TARGET_WORDS_BIGENDIAN=y" >> $config_target_mak
fi
diff --git a/qemu-options.hx b/qemu-options.hx
index 9f6e2adfff..841d75cf6c 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -31,7 +31,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
"-machine [type=]name[,prop[=value][,...]]\n"
" selects emulated machine ('-machine help' for list)\n"
" property accel=accel1[:accel2[:...]] selects accelerator\n"
- " supported accelerators are kvm, xen, hax or tcg (default: tcg)\n"
+ " supported accelerators are kvm, xen, hax, hvf or tcg (default: tcg)\n"
" kernel_irqchip=on|off|split controls accelerated irqchip support (default=off)\n"
" vmport=on|off|auto controls emulation of vmport (default: auto)\n"
" kvm_shadow_mem=size of KVM shadow MMU in bytes\n"
@@ -66,7 +66,7 @@ Supported machine properties are:
@table @option
@item accel=@var{accels1}[:@var{accels2}[:...]]
This is used to enable an accelerator. Depending on the target architecture,
-kvm, xen, hax or tcg can be available. By default, tcg is used. If there is
+kvm, xen, hax, hvf or tcg can be available. By default, tcg is used. If there is
more than one accelerator specified, the next one is used if the previous one
fails to initialize.
@item kernel_irqchip=on|off
@@ -120,13 +120,13 @@ ETEXI
DEF("accel", HAS_ARG, QEMU_OPTION_accel,
"-accel [accel=]accelerator[,thread=single|multi]\n"
- " select accelerator (kvm, xen, hax or tcg; use 'help' for a list)\n"
- " thread=single|multi (enable multi-threaded TCG)\n", QEMU_ARCH_ALL)
+ " select accelerator (kvm, xen, hax, hvf or tcg; use 'help' for a list)\n"
+ " thread=single|multi (enable multi-threaded TCG)", QEMU_ARCH_ALL)
STEXI
@item -accel @var{name}[,prop=@var{value}[,...]]
@findex -accel
This is used to enable an accelerator. Depending on the target architecture,
-kvm, xen, hax or tcg can be available. By default, tcg is used. If there is
+kvm, xen, hax, hvf or tcg can be available. By default, tcg is used. If there is
more than one accelerator specified, the next one is used if the previous one
fails to initialize.
@table @option
@@ -3619,6 +3619,16 @@ applicable to MAC and Windows platform, and thus does not conflict with
KVM.
ETEXI
+DEF("enable-hvf", 0, QEMU_OPTION_enable_hvf, \
+ "-enable-hvf enable Hypervisor.framework virtualization support\n", QEMU_ARCH_I386)
+STEXI
+@item -enable-hvf
+@findex -enable-hvf
+Enable Hypervisor.framework support. This option is only available if
+HVF support is enabled when compiling. HVF is only applicable to MAC
+platform, and thus does not conflict with KVM.
+ETEXI
+
DEF("xen-domid", HAS_ARG, QEMU_OPTION_xen_domid,
"-xen-domid id specify xen guest domain id\n", QEMU_ARCH_ALL)
DEF("xen-create", 0, QEMU_OPTION_xen_create,
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:12 ` Stefan Hajnoczi
2017-08-29 11:22 ` Daniel P. Berrange
2017-08-28 1:56 ` [Qemu-devel] [PATCH 03/14] hvf: add conditional macros around hvf code in cpus.c Sergio Andres Gomez Del Real
` (14 subsequent siblings)
16 siblings, 2 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This file begins tracking the files that will be the code base for HVF
support in QEMU.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
cpus.c | 42 +
include/sysemu/hvf.h | 96 ++
target/i386/hvf-all.c | 982 +++++++++++++++++++++
target/i386/hvf-i386.h | 48 +
target/i386/hvf-utils/Makefile.objs | 1 +
target/i386/hvf-utils/README.md | 7 +
target/i386/hvf-utils/vmcs.h | 368 ++++++++
target/i386/hvf-utils/vmx.h | 200 +++++
target/i386/hvf-utils/x86.c | 174 ++++
target/i386/hvf-utils/x86.h | 470 ++++++++++
target/i386/hvf-utils/x86_cpuid.c | 270 ++++++
target/i386/hvf-utils/x86_cpuid.h | 51 ++
target/i386/hvf-utils/x86_decode.c | 1659 +++++++++++++++++++++++++++++++++++
target/i386/hvf-utils/x86_decode.h | 314 +++++++
target/i386/hvf-utils/x86_descr.c | 124 +++
target/i386/hvf-utils/x86_descr.h | 40 +
target/i386/hvf-utils/x86_emu.c | 1466 +++++++++++++++++++++++++++++++
target/i386/hvf-utils/x86_emu.h | 16 +
target/i386/hvf-utils/x86_flags.c | 317 +++++++
target/i386/hvf-utils/x86_flags.h | 218 +++++
target/i386/hvf-utils/x86_gen.h | 36 +
target/i386/hvf-utils/x86_mmu.c | 254 ++++++
target/i386/hvf-utils/x86_mmu.h | 28 +
target/i386/hvf-utils/x86hvf.c | 501 +++++++++++
target/i386/hvf-utils/x86hvf.h | 19 +
25 files changed, 7701 insertions(+)
create mode 100644 include/sysemu/hvf.h
create mode 100644 target/i386/hvf-all.c
create mode 100644 target/i386/hvf-i386.h
create mode 100644 target/i386/hvf-utils/Makefile.objs
create mode 100644 target/i386/hvf-utils/README.md
create mode 100644 target/i386/hvf-utils/vmcs.h
create mode 100644 target/i386/hvf-utils/vmx.h
create mode 100644 target/i386/hvf-utils/x86.c
create mode 100644 target/i386/hvf-utils/x86.h
create mode 100644 target/i386/hvf-utils/x86_cpuid.c
create mode 100644 target/i386/hvf-utils/x86_cpuid.h
create mode 100644 target/i386/hvf-utils/x86_decode.c
create mode 100644 target/i386/hvf-utils/x86_decode.h
create mode 100644 target/i386/hvf-utils/x86_descr.c
create mode 100644 target/i386/hvf-utils/x86_descr.h
create mode 100644 target/i386/hvf-utils/x86_emu.c
create mode 100644 target/i386/hvf-utils/x86_emu.h
create mode 100644 target/i386/hvf-utils/x86_flags.c
create mode 100644 target/i386/hvf-utils/x86_flags.h
create mode 100644 target/i386/hvf-utils/x86_gen.h
create mode 100644 target/i386/hvf-utils/x86_mmu.c
create mode 100644 target/i386/hvf-utils/x86_mmu.h
create mode 100644 target/i386/hvf-utils/x86hvf.c
create mode 100644 target/i386/hvf-utils/x86hvf.h
diff --git a/cpus.c b/cpus.c
index 9bed61eefc..a2cd9dfa5d 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1434,6 +1434,48 @@ static void *qemu_hax_cpu_thread_fn(void *arg)
return NULL;
}
+/* The HVF-specific vCPU thread function. This one should only run when the host
+ * CPU supports the VMX "unrestricted guest" feature. */
+static void *qemu_hvf_cpu_thread_fn(void *arg)
+{
+ CPUState *cpu = arg;
+
+ int r;
+
+ assert(hvf_enabled());
+
+ rcu_register_thread();
+
+ qemu_mutex_lock_iothread();
+ qemu_thread_get_self(cpu->thread);
+
+ cpu->thread_id = qemu_get_thread_id();
+ cpu->can_do_io = 1;
+ current_cpu = cpu;
+
+ hvf_init_vcpu(cpu);
+
+ /* signal CPU creation */
+ cpu->created = true;
+ qemu_cond_signal(&qemu_cpu_cond);
+
+ do {
+ if (cpu_can_run(cpu)) {
+ r = hvf_vcpu_exec(cpu);
+ if (r == EXCP_DEBUG) {
+ cpu_handle_guest_debug(cpu);
+ }
+ }
+ qemu_hvf_wait_io_event(cpu);
+ } while (!cpu->unplug || cpu_can_run(cpu));
+
+ hvf_vcpu_destroy(cpu);
+ cpu->created = false;
+ qemu_cond_signal(&qemu_cpu_cond);
+ qemu_mutex_unlock_iothread();
+ return NULL;
+}
+
#ifdef _WIN32
static void CALLBACK dummy_apc_func(ULONG_PTR unused)
{
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
new file mode 100644
index 0000000000..b96bd5e8ba
--- /dev/null
+++ b/include/sysemu/hvf.h
@@ -0,0 +1,96 @@
+/*
+ * QEMU Hypervisor.framework (HVF) support
+ *
+ * Copyright Google Inc., 2017
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+/* header to be included in non-HVF-specific code */
+#ifndef _HVF_H
+#define _HVF_H
+
+#include "config-host.h"
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "hw/hw.h"
+#include "target/i386/cpu.h"
+#include "qemu/bitops.h"
+#include "exec/memory.h"
+#include "sysemu/accel.h"
+#include <Hypervisor/hv.h>
+#include <Hypervisor/hv_vmx.h>
+#include <Hypervisor/hv_error.h>
+
+
+typedef struct hvf_slot {
+ uint64_t start;
+ uint64_t size;
+ uint8_t *mem;
+ int slot_id;
+} hvf_slot;
+
+typedef struct HVFState {
+ AccelState parent;
+ hvf_slot slots[32];
+ int num_slots;
+} HVFState;
+
+struct hvf_vcpu_caps {
+ uint64_t vmx_cap_pinbased;
+ uint64_t vmx_cap_procbased;
+ uint64_t vmx_cap_procbased2;
+ uint64_t vmx_cap_entry;
+ uint64_t vmx_cap_exit;
+ uint64_t vmx_cap_preemption_timer;
+};
+
+int __hvf_set_memory(hvf_slot *);
+void hvf_set_phys_mem(MemoryRegionSection *, bool);
+void hvf_handle_io(CPUArchState *, uint16_t, void *,
+ int, int, int);
+hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);
+
+/* Returns 1 if HVF is available and enabled, 0 otherwise. */
+int hvf_enabled(void);
+
+/* Disable HVF if |disable| is 1, otherwise, enable it iff it is supported by the host CPU.
+ * Use hvf_enabled() after this to get the result. */
+void hvf_disable(int disable);
+
+/* Returns non-0 if the host CPU supports the VMX "unrestricted guest" feature which
+ * allows the virtual CPU to directly run in "real mode". If true, this allows QEMU to run
+ * several vCPU threads in parallel (see cpus.c). Otherwise, only a a single TCG thread
+ * can run, and it will call HVF to run the current instructions, except in case of
+ * "real mode" (paging disabled, typically at boot time), or MMIO operations. */
+// int hvf_ug_platform(void); does not apply to HVF; assume we must be in UG mode
+
+int hvf_sync_vcpus(void);
+
+int hvf_init_vcpu(CPUState *);
+int hvf_vcpu_exec(CPUState *);
+int hvf_smp_cpu_exec(CPUState *);
+void hvf_cpu_synchronize_state(CPUState *);
+void hvf_cpu_synchronize_post_reset(CPUState *);
+void hvf_cpu_synchronize_post_init(CPUState *);
+void _hvf_cpu_synchronize_post_init(CPUState *, run_on_cpu_data);
+
+void hvf_vcpu_destroy(CPUState *);
+void hvf_raise_event(CPUState *);
+// void hvf_reset_vcpu_state(void *opaque);
+void vmx_reset_vcpu(CPUState *);
+void __hvf_cpu_synchronize_state(CPUState *, run_on_cpu_data);
+void __hvf_cpu_synchronize_post_reset(CPUState *, run_on_cpu_data);
+void vmx_update_tpr(CPUState *);
+void update_apic_tpr(CPUState *);
+int apic_get_highest_priority_irr(DeviceState *);
+int hvf_put_registers(CPUState *);
+
+#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
+
+#define HVF_STATE(obj) \
+ OBJECT_CHECK(HVFState, (obj), TYPE_HVF_ACCEL)
+
+#endif
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
new file mode 100644
index 0000000000..06cd8429eb
--- /dev/null
+++ b/target/i386/hvf-all.c
@@ -0,0 +1,982 @@
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+
+#include "sysemu/hvf.h"
+#include "hvf-i386.h"
+#include "hvf-utils/vmcs.h"
+#include "hvf-utils/vmx.h"
+#include "hvf-utils/x86.h"
+#include "hvf-utils/x86_descr.h"
+#include "hvf-utils/x86_mmu.h"
+#include "hvf-utils/x86_decode.h"
+#include "hvf-utils/x86_emu.h"
+#include "hvf-utils/x86_cpuid.h"
+#include "hvf-utils/x86hvf.h"
+
+#include <Hypervisor/hv.h>
+#include <Hypervisor/hv_vmx.h>
+
+#include "exec/address-spaces.h"
+#include "exec/exec-all.h"
+#include "exec/ioport.h"
+#include "hw/i386/apic_internal.h"
+#include "hw/boards.h"
+#include "qemu/main-loop.h"
+#include "strings.h"
+#include "trace.h"
+#include "sysemu/accel.h"
+#include "sysemu/sysemu.h"
+#include "target/i386/cpu.h"
+
+pthread_rwlock_t mem_lock = PTHREAD_RWLOCK_INITIALIZER;
+HVFState *hvf_state;
+static int hvf_disabled = 1;
+
+static void assert_hvf_ok(hv_return_t ret)
+{
+ if (ret == HV_SUCCESS)
+ return;
+
+ switch (ret) {
+ case HV_ERROR:
+ fprintf(stderr, "Error: HV_ERROR\n");
+ break;
+ case HV_BUSY:
+ fprintf(stderr, "Error: HV_BUSY\n");
+ break;
+ case HV_BAD_ARGUMENT:
+ fprintf(stderr, "Error: HV_BAD_ARGUMENT\n");
+ break;
+ case HV_NO_RESOURCES:
+ fprintf(stderr, "Error: HV_NO_RESOURCES\n");
+ break;
+ case HV_NO_DEVICE:
+ fprintf(stderr, "Error: HV_NO_DEVICE\n");
+ break;
+ case HV_UNSUPPORTED:
+ fprintf(stderr, "Error: HV_UNSUPPORTED\n");
+ break;
+ default:
+ fprintf(stderr, "Unknown Error\n");
+ }
+
+ abort();
+}
+
+// Memory slots/////////////////////////////////////////////////////////////////
+
+hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t end) {
+ hvf_slot *slot;
+ int x;
+ for (x = 0; x < hvf_state->num_slots; ++x) {
+ slot = &hvf_state->slots[x];
+ if (slot->size && start < (slot->start + slot->size) && end > slot->start)
+ return slot;
+ }
+ return NULL;
+}
+
+struct mac_slot {
+ int present;
+ uint64_t size;
+ uint64_t gpa_start;
+ uint64_t gva;
+};
+
+struct mac_slot mac_slots[32];
+#define ALIGN(x, y) (((x)+(y)-1) & ~((y)-1))
+
+int __hvf_set_memory(hvf_slot *slot)
+{
+ struct mac_slot *macslot;
+ hv_memory_flags_t flags;
+ pthread_rwlock_wrlock(&mem_lock);
+ hv_return_t ret;
+
+ macslot = &mac_slots[slot->slot_id];
+
+ if (macslot->present) {
+ if (macslot->size != slot->size) {
+ macslot->present = 0;
+ ret = hv_vm_unmap(macslot->gpa_start, macslot->size);
+ assert_hvf_ok(ret);
+ }
+ }
+
+ if (!slot->size) {
+ pthread_rwlock_unlock(&mem_lock);
+ return 0;
+ }
+
+ flags = HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC;
+
+ macslot->present = 1;
+ macslot->gpa_start = slot->start;
+ macslot->size = slot->size;
+ ret = hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, flags);
+ assert_hvf_ok(ret);
+ pthread_rwlock_unlock(&mem_lock);
+ return 0;
+}
+
+void hvf_set_phys_mem(MemoryRegionSection* section, bool add)
+{
+ hvf_slot *mem;
+ MemoryRegion *area = section->mr;
+
+ if (!memory_region_is_ram(area)) return;
+
+ mem = hvf_find_overlap_slot(
+ section->offset_within_address_space,
+ section->offset_within_address_space + int128_get64(section->size));
+
+ if (mem && add) {
+ if (mem->size == int128_get64(section->size) &&
+ mem->start == section->offset_within_address_space &&
+ mem->mem == (memory_region_get_ram_ptr(area) + section->offset_within_region))
+ return; // Same region was attempted to register, go away.
+ }
+
+ // Region needs to be reset. set the size to 0 and remap it.
+ if (mem) {
+ mem->size = 0;
+ if (__hvf_set_memory(mem)) {
+ fprintf(stderr, "Failed to reset overlapping slot\n");
+ abort();
+ }
+ }
+
+ if (!add) return;
+
+ // Now make a new slot.
+ int x;
+
+ for (x = 0; x < hvf_state->num_slots; ++x) {
+ mem = &hvf_state->slots[x];
+ if (!mem->size)
+ break;
+ }
+
+ if (x == hvf_state->num_slots) {
+ fprintf(stderr, "No free slots\n");
+ abort();
+ }
+
+ mem->size = int128_get64(section->size);
+ mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region;
+ mem->start = section->offset_within_address_space;
+
+ if (__hvf_set_memory(mem)) {
+ fprintf(stderr, "Error registering new memory slot\n");
+ abort();
+ }
+}
+
+/* return -1 if no bit is set */
+static int get_highest_priority_int(uint32_t *tab)
+{
+ int i;
+ for (i = 7; i >= 0; i--) {
+ if (tab[i] != 0) {
+ return i * 32 + apic_fls_bit(tab[i]);
+ }
+ }
+ return -1;
+}
+
+void vmx_update_tpr(CPUState *cpu)
+{
+ // TODO: need integrate APIC handling
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
+ int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
+
+ wreg(cpu->hvf_fd, HV_X86_TPR, tpr);
+ if (irr == -1)
+ wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
+ else
+ wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4);
+}
+
+void update_apic_tpr(CPUState *cpu)
+{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ int tpr = rreg(cpu->hvf_fd, HV_X86_TPR) >> 4;
+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
+}
+
+#define VECTORING_INFO_VECTOR_MASK 0xff
+
+// TODO: taskswitch handling
+static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
+{
+ /* CR3 and ldt selector are not saved intentionally */
+ tss->eip = EIP(cpu);
+ tss->eflags = EFLAGS(cpu);
+ tss->eax = EAX(cpu);
+ tss->ecx = ECX(cpu);
+ tss->edx = EDX(cpu);
+ tss->ebx = EBX(cpu);
+ tss->esp = ESP(cpu);
+ tss->ebp = EBP(cpu);
+ tss->esi = ESI(cpu);
+ tss->edi = EDI(cpu);
+
+ tss->es = vmx_read_segment_selector(cpu, REG_SEG_ES).sel;
+ tss->cs = vmx_read_segment_selector(cpu, REG_SEG_CS).sel;
+ tss->ss = vmx_read_segment_selector(cpu, REG_SEG_SS).sel;
+ tss->ds = vmx_read_segment_selector(cpu, REG_SEG_DS).sel;
+ tss->fs = vmx_read_segment_selector(cpu, REG_SEG_FS).sel;
+ tss->gs = vmx_read_segment_selector(cpu, REG_SEG_GS).sel;
+}
+
+static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
+{
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3);
+
+ RIP(cpu) = tss->eip;
+ EFLAGS(cpu) = tss->eflags | 2;
+
+ /* General purpose registers */
+ RAX(cpu) = tss->eax;
+ RCX(cpu) = tss->ecx;
+ RDX(cpu) = tss->edx;
+ RBX(cpu) = tss->ebx;
+ RSP(cpu) = tss->esp;
+ RBP(cpu) = tss->ebp;
+ RSI(cpu) = tss->esi;
+ RDI(cpu) = tss->edi;
+
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS);
+
+#if 0
+ load_segment(cpu, REG_SEG_LDTR, tss->ldt);
+ load_segment(cpu, REG_SEG_ES, tss->es);
+ load_segment(cpu, REG_SEG_CS, tss->cs);
+ load_segment(cpu, REG_SEG_SS, tss->ss);
+ load_segment(cpu, REG_SEG_DS, tss->ds);
+ load_segment(cpu, REG_SEG_FS, tss->fs);
+ load_segment(cpu, REG_SEG_GS, tss->gs);
+#endif
+}
+
+static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
+ uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
+{
+ struct x86_tss_segment32 tss_seg;
+ uint32_t new_tss_base = x86_segment_base(new_desc);
+ uint32_t eip_offset = offsetof(struct x86_tss_segment32, eip);
+ uint32_t ldt_sel_offset = offsetof(struct x86_tss_segment32, ldt);
+
+ vmx_read_mem(cpu, &tss_seg, old_tss_base, sizeof(tss_seg));
+ save_state_to_tss32(cpu, &tss_seg);
+
+ vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset);
+ vmx_read_mem(cpu, &tss_seg, new_tss_base, sizeof(tss_seg));
+
+ if (old_tss_sel.sel != 0xffff) {
+ tss_seg.prev_tss = old_tss_sel.sel;
+
+ vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss));
+ }
+ load_state_from_tss32(cpu, &tss_seg);
+ return 0;
+}
+
+static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
+{
+ uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP);
+ if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
+ gate_type != VMCS_INTR_T_HWINTR &&
+ gate_type != VMCS_INTR_T_NMI)) {
+ int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ macvm_set_rip(cpu, rip + ins_len);
+ return;
+ }
+
+ load_regs(cpu);
+
+ struct x86_segment_descriptor curr_tss_desc, next_tss_desc;
+ int ret;
+ x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, REG_SEG_TR);
+ uint64_t old_tss_base = vmx_read_segment_base(cpu, REG_SEG_TR);
+ uint32_t desc_limit;
+ struct x86_call_gate task_gate_desc;
+ struct vmx_segment vmx_seg;
+
+ x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel);
+ x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
+
+ if (reason == TSR_IDT_GATE && gate_valid) {
+ int dpl;
+
+ ret = x86_read_call_gate(cpu, &task_gate_desc, gate);
+
+ dpl = task_gate_desc.dpl;
+ x68_segment_selector cs = vmx_read_segment_selector(cpu, REG_SEG_CS);
+ if (tss_sel.rpl > dpl || cs.rpl > dpl)
+ ;//DPRINTF("emulate_gp");
+ }
+
+ desc_limit = x86_segment_limit(&next_tss_desc);
+ if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) {
+ VM_PANIC("emulate_ts");
+ }
+
+ if (reason == TSR_IRET || reason == TSR_JMP) {
+ curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
+ x86_write_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
+ }
+
+ if (reason == TSR_IRET)
+ EFLAGS(cpu) &= ~RFLAGS_NT;
+
+ if (reason != TSR_CALL && reason != TSR_IDT_GATE)
+ old_tss_sel.sel = 0xffff;
+
+ if (reason != TSR_IRET) {
+ next_tss_desc.type |= (1 << 1); /* set busy flag */
+ x86_write_segment_descriptor(cpu, &next_tss_desc, tss_sel);
+ }
+
+ if (next_tss_desc.type & 8)
+ ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
+ else
+ //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
+ VM_PANIC("task_switch_16");
+
+ macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS);
+ x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
+ vmx_write_segment_descriptor(cpu, &vmx_seg, REG_SEG_TR);
+
+ store_regs(cpu);
+
+ hv_vcpu_invalidate_tlb(cpu->hvf_fd);
+ hv_vcpu_flush(cpu->hvf_fd);
+}
+
+static void hvf_handle_interrupt(CPUState * cpu, int mask)
+{
+ cpu->interrupt_request |= mask;
+ if (!qemu_cpu_is_self(cpu)) {
+ qemu_cpu_kick(cpu);
+ }
+}
+
+void hvf_handle_io(CPUArchState * env, uint16_t port, void* buffer,
+ int direction, int size, int count)
+{
+ int i;
+ uint8_t *ptr = buffer;
+
+ for (i = 0; i < count; i++) {
+ address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED,
+ ptr, size,
+ direction);
+ ptr += size;
+ }
+}
+//
+// TODO: synchronize vcpu state
+void __hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
+{
+ CPUState *cpu_state = cpu;//(CPUState *)data;
+ if (cpu_state->hvf_vcpu_dirty == 0)
+ hvf_get_registers(cpu_state);
+
+ cpu_state->hvf_vcpu_dirty = 1;
+}
+
+void hvf_cpu_synchronize_state(CPUState *cpu_state)
+{
+ if (cpu_state->hvf_vcpu_dirty == 0)
+ run_on_cpu(cpu_state, __hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
+}
+
+void __hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
+{
+ CPUState *cpu_state = cpu;
+ hvf_put_registers(cpu_state);
+ cpu_state->hvf_vcpu_dirty = false;
+}
+
+void hvf_cpu_synchronize_post_reset(CPUState *cpu_state)
+{
+ run_on_cpu(cpu_state, __hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
+}
+
+void _hvf_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
+{
+ CPUState *cpu_state = cpu;
+ hvf_put_registers(cpu_state);
+ cpu_state->hvf_vcpu_dirty = false;
+}
+
+void hvf_cpu_synchronize_post_init(CPUState *cpu_state)
+{
+ run_on_cpu(cpu_state, _hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
+}
+
+// TODO: ept fault handlig
+void vmx_clear_int_window_exiting(CPUState *cpu);
+static bool ept_emulation_fault(uint64_t ept_qual)
+{
+ int read, write;
+
+ /* EPT fault on an instruction fetch doesn't make sense here */
+ if (ept_qual & EPT_VIOLATION_INST_FETCH)
+ return false;
+
+ /* EPT fault must be a read fault or a write fault */
+ read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
+ write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
+ if ((read | write) == 0)
+ return false;
+
+ /*
+ * The EPT violation must have been caused by accessing a
+ * guest-physical address that is a translation of a guest-linear
+ * address.
+ */
+ if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
+ (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
+ return false;
+ }
+
+ return true;
+}
+
+static void hvf_region_add(MemoryListener * listener,
+ MemoryRegionSection * section)
+{
+ hvf_set_phys_mem(section, true);
+}
+
+static void hvf_region_del(MemoryListener * listener,
+ MemoryRegionSection * section)
+{
+ hvf_set_phys_mem(section, false);
+}
+
+static MemoryListener hvf_memory_listener = {
+ .priority = 10,
+ .region_add = hvf_region_add,
+ .region_del = hvf_region_del,
+};
+
+static MemoryListener hvf_io_listener = {
+ .priority = 10,
+};
+
+void vmx_reset_vcpu(CPUState *cpu) {
+
+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, 0);
+ macvm_set_cr0(cpu->hvf_fd, 0x60000010);
+
+ wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK);
+ wvmcs(cpu->hvf_fd, VMCS_CR4_SHADOW, 0x0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CR4, CR4_VMXE_MASK);
+
+ // set VMCS guest state fields
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_SELECTOR, 0xf000);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_LIMIT, 0xffff);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_ACCESS_RIGHTS, 0x9b);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_BASE, 0xffff0000);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_LIMIT, 0xffff);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_ACCESS_RIGHTS, 0x93);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_LIMIT, 0xffff);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_ACCESS_RIGHTS, 0x93);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_LIMIT, 0xffff);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_ACCESS_RIGHTS, 0x93);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_LIMIT, 0xffff);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_ACCESS_RIGHTS, 0x93);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_LIMIT, 0xffff);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_ACCESS_RIGHTS, 0x93);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x10000);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_SELECTOR, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_LIMIT, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_ACCESS_RIGHTS, 0x83);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE, 0);
+
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT, 0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE, 0);
+
+ //wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, 0x0);
+
+ wreg(cpu->hvf_fd, HV_X86_RIP, 0xfff0);
+ wreg(cpu->hvf_fd, HV_X86_RDX, 0x623);
+ wreg(cpu->hvf_fd, HV_X86_RFLAGS, 0x2);
+ wreg(cpu->hvf_fd, HV_X86_RSP, 0x0);
+ wreg(cpu->hvf_fd, HV_X86_RAX, 0x0);
+ wreg(cpu->hvf_fd, HV_X86_RBX, 0x0);
+ wreg(cpu->hvf_fd, HV_X86_RCX, 0x0);
+ wreg(cpu->hvf_fd, HV_X86_RSI, 0x0);
+ wreg(cpu->hvf_fd, HV_X86_RDI, 0x0);
+ wreg(cpu->hvf_fd, HV_X86_RBP, 0x0);
+
+ for (int i = 0; i < 8; i++)
+ wreg(cpu->hvf_fd, HV_X86_R8+i, 0x0);
+
+ hv_vm_sync_tsc(0);
+ cpu->halted = 0;
+ hv_vcpu_invalidate_tlb(cpu->hvf_fd);
+ hv_vcpu_flush(cpu->hvf_fd);
+}
+
+void hvf_vcpu_destroy(CPUState* cpu)
+{
+ hv_return_t ret = hv_vcpu_destroy((hv_vcpuid_t)cpu->hvf_fd);
+ assert_hvf_ok(ret);
+}
+
+static void dummy_signal(int sig)
+{
+}
+
+int hvf_init_vcpu(CPUState * cpu) {
+
+ X86CPU *x86cpu;
+
+ // init cpu signals
+ sigset_t set;
+ struct sigaction sigact;
+
+ memset(&sigact, 0, sizeof(sigact));
+ sigact.sa_handler = dummy_signal;
+ sigaction(SIG_IPI, &sigact, NULL);
+
+ pthread_sigmask(SIG_BLOCK, NULL, &set);
+ sigdelset(&set, SIG_IPI);
+
+ int r;
+ init_emu(cpu);
+ init_decoder(cpu);
+ init_cpuid(cpu);
+
+ cpu->hvf_caps = (struct hvf_vcpu_caps*)g_malloc0(sizeof(struct hvf_vcpu_caps));
+ cpu->hvf_x86 = (struct hvf_x86_state*)g_malloc0(sizeof(struct hvf_x86_state));
+
+ r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);
+ cpu->hvf_vcpu_dirty = 1;
+ assert_hvf_ok(r);
+
+ if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &cpu->hvf_caps->vmx_cap_pinbased))
+ abort();
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cpu->hvf_caps->vmx_cap_procbased))
+ abort();
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cpu->hvf_caps->vmx_cap_procbased2))
+ abort();
+ if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cpu->hvf_caps->vmx_cap_entry))
+ abort();
+
+ /* set VMCS control fields */
+ wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,
+ VMCS_PRI_PROC_BASED_CTLS_HLT |
+ VMCS_PRI_PROC_BASED_CTLS_MWAIT |
+ VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
+ VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
+ VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
+ wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,
+ cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
+
+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry, 0));
+ wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
+
+ wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
+
+ vmx_reset_vcpu(cpu);
+
+ x86cpu = X86_CPU(cpu);
+ x86cpu->env.kvm_xsave_buf = qemu_memalign(4096, sizeof(struct hvf_xsave_buf));
+
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1);
+ //hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1);
+ hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1);
+
+ return 0;
+}
+
+int hvf_enabled() { return !hvf_disabled; }
+void hvf_disable(int shouldDisable) {
+ hvf_disabled = shouldDisable;
+}
+
+int hvf_vcpu_exec(CPUState* cpu) {
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ int ret = 0;
+ uint64_t rip = 0;
+
+ cpu->halted = 0;
+
+ if (hvf_process_events(cpu)) {
+ return EXCP_HLT;
+ }
+
+ do {
+ if (cpu->hvf_vcpu_dirty) {
+ hvf_put_registers(cpu);
+ cpu->hvf_vcpu_dirty = false;
+ }
+
+ cpu->hvf_x86->interruptable =
+ !(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
+ (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
+
+ hvf_inject_interrupts(cpu);
+ vmx_update_tpr(cpu);
+
+
+ qemu_mutex_unlock_iothread();
+ if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) {
+ qemu_mutex_lock_iothread();
+ return EXCP_HLT;
+ }
+
+ hv_return_t r = hv_vcpu_run(cpu->hvf_fd);
+ assert_hvf_ok(r);
+
+ /* handle VMEXIT */
+ uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON);
+ uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);
+ uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
+ rip = rreg(cpu->hvf_fd, HV_X86_RIP);
+ RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
+ env->eflags = RFLAGS(cpu);
+
+ trace_hvf_vm_exit(exit_reason, exit_qual);
+
+ qemu_mutex_lock_iothread();
+
+ update_apic_tpr(cpu);
+ current_cpu = cpu;
+
+ ret = 0;
+ switch (exit_reason) {
+ case EXIT_REASON_HLT: {
+ macvm_set_rip(cpu, rip + ins_len);
+ if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu) & IF_MASK))
+ && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
+ !(idtvec_info & VMCS_IDT_VEC_VALID)) {
+ cpu->halted = 1;
+ ret = EXCP_HLT;
+ }
+ ret = EXCP_INTERRUPT;
+ break;
+ }
+ case EXIT_REASON_MWAIT: {
+ ret = EXCP_INTERRUPT;
+ break;
+ }
+ /* Need to check if MMIO or unmmaped fault */
+ case EXIT_REASON_EPT_FAULT:
+ {
+ hvf_slot *slot;
+ addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
+ trace_hvf_vm_exit_gpa(gpa);
+
+ if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && (exit_qual & EXIT_QUAL_NMIUDTI) != 0)
+ vmx_set_nmi_blocking(cpu);
+
+ slot = hvf_find_overlap_slot(gpa, gpa);
+ // mmio
+ if (ept_emulation_fault(exit_qual) && !slot) {
+ struct x86_decode decode;
+
+ load_regs(cpu);
+ cpu->hvf_x86->fetch_rip = rip;
+
+ decode_instruction(cpu, &decode);
+ exec_instruction(cpu, &decode);
+ store_regs(cpu);
+ break;
+ }
+#ifdef DIRTY_VGA_TRACKING
+ if (slot) {
+ bool read = exit_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
+ bool write = exit_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
+ if (!read && !write)
+ break;
+ int flags = HV_MEMORY_READ | HV_MEMORY_EXEC;
+ if (write) flags |= HV_MEMORY_WRITE;
+
+ pthread_rwlock_wrlock(&mem_lock);
+ if (write)
+ mark_slot_page_dirty(slot, gpa);
+ hv_vm_protect(gpa & ~0xfff, 4096, flags);
+ pthread_rwlock_unlock(&mem_lock);
+ }
+#endif
+ break;
+ }
+ case EXIT_REASON_INOUT:
+ {
+ uint32_t in = (exit_qual & 8) != 0;
+ uint32_t size = (exit_qual & 7) + 1;
+ uint32_t string = (exit_qual & 16) != 0;
+ uint32_t port = exit_qual >> 16;
+ //uint32_t rep = (exit_qual & 0x20) != 0;
+
+#if 1
+ if (!string && in) {
+ uint64_t val = 0;
+ load_regs(cpu);
+ hvf_handle_io(env, port, &val, 0, size, 1);
+ if (size == 1) AL(cpu) = val;
+ else if (size == 2) AX(cpu) = val;
+ else if (size == 4) RAX(cpu) = (uint32_t)val;
+ else VM_PANIC("size");
+ RIP(cpu) += ins_len;
+ store_regs(cpu);
+ break;
+ } else if (!string && !in) {
+ RAX(cpu) = rreg(cpu->hvf_fd, HV_X86_RAX);
+ hvf_handle_io(env, port, &RAX(cpu), 1, size, 1);
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ }
+#endif
+ struct x86_decode decode;
+
+ load_regs(cpu);
+ cpu->hvf_x86->fetch_rip = rip;
+
+ decode_instruction(cpu, &decode);
+ VM_PANIC_ON(ins_len != decode.len);
+ exec_instruction(cpu, &decode);
+ store_regs(cpu);
+
+ break;
+ }
+ case EXIT_REASON_CPUID: {
+ uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
+ uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX);
+ uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
+ uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
+
+ get_cpuid_func(cpu, rax, rcx, &rax, &rbx, &rcx, &rdx);
+
+ wreg(cpu->hvf_fd, HV_X86_RAX, rax);
+ wreg(cpu->hvf_fd, HV_X86_RBX, rbx);
+ wreg(cpu->hvf_fd, HV_X86_RCX, rcx);
+ wreg(cpu->hvf_fd, HV_X86_RDX, rdx);
+
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ }
+ case EXIT_REASON_XSETBV: {
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
+ uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
+ uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
+
+ if (ecx) {
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ }
+ env->xcr0 = ((uint64_t)edx << 32) | eax;
+ wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1);
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ }
+ case EXIT_REASON_INTR_WINDOW:
+ vmx_clear_int_window_exiting(cpu);
+ ret = EXCP_INTERRUPT;
+ break;
+ case EXIT_REASON_NMI_WINDOW:
+ vmx_clear_nmi_window_exiting(cpu);
+ ret = EXCP_INTERRUPT;
+ break;
+ case EXIT_REASON_EXT_INTR:
+ /* force exit and allow io handling */
+ ret = EXCP_INTERRUPT;
+ break;
+ case EXIT_REASON_RDMSR:
+ case EXIT_REASON_WRMSR:
+ {
+ load_regs(cpu);
+ if (exit_reason == EXIT_REASON_RDMSR)
+ simulate_rdmsr(cpu);
+ else
+ simulate_wrmsr(cpu);
+ RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ store_regs(cpu);
+ break;
+ }
+ case EXIT_REASON_CR_ACCESS: {
+ int cr;
+ int reg;
+
+ load_regs(cpu);
+ cr = exit_qual & 15;
+ reg = (exit_qual >> 8) & 15;
+
+ switch (cr) {
+ case 0x0: {
+ macvm_set_cr0(cpu->hvf_fd, RRX(cpu, reg));
+ break;
+ }
+ case 4: {
+ macvm_set_cr4(cpu->hvf_fd, RRX(cpu, reg));
+ break;
+ }
+ case 8: {
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ if (exit_qual & 0x10) {
+ RRX(cpu, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
+ }
+ else {
+ int tpr = RRX(cpu, reg);
+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
+ ret = EXCP_INTERRUPT;
+ }
+ break;
+ }
+ default:
+ fprintf(stderr, "Unrecognized CR %d\n", cr);
+ abort();
+ }
+ RIP(cpu) += ins_len;
+ store_regs(cpu);
+ break;
+ }
+ case EXIT_REASON_APIC_ACCESS: { // TODO
+ struct x86_decode decode;
+
+ load_regs(cpu);
+ cpu->hvf_x86->fetch_rip = rip;
+
+ decode_instruction(cpu, &decode);
+ exec_instruction(cpu, &decode);
+ store_regs(cpu);
+ break;
+ }
+ case EXIT_REASON_TPR: {
+ ret = 1;
+ break;
+ }
+ case EXIT_REASON_TASK_SWITCH: {
+ uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
+ x68_segment_selector sel = {.sel = exit_qual & 0xffff};
+ vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
+ vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo & VMCS_INTR_T_MASK);
+ break;
+ }
+ case EXIT_REASON_TRIPLE_FAULT: {
+ //addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ usleep(1000 * 100);
+ ret = EXCP_INTERRUPT;
+ break;
+ }
+ case EXIT_REASON_RDPMC:
+ wreg(cpu->hvf_fd, HV_X86_RAX, 0);
+ wreg(cpu->hvf_fd, HV_X86_RDX, 0);
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ case VMX_REASON_VMCALL:
+ // TODO: maybe just take this out?
+ // if (g_hypervisor_iface) {
+ // load_regs(cpu);
+ // g_hypervisor_iface->hypercall_handler(cpu);
+ // RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ // store_regs(cpu);
+ // }
+ break;
+ default:
+ fprintf(stderr, "%llx: unhandled exit %llx\n", rip, exit_reason);
+ }
+ } while (ret == 0);
+
+ return ret;
+}
+
+static bool hvf_allowed;
+
+static int hvf_accel_init(MachineState *ms)
+{
+ int x;
+ hv_return_t ret;
+ HVFState *s;
+
+ ret = hv_vm_create(HV_VM_DEFAULT);
+ assert_hvf_ok(ret);
+
+ s = (HVFState *)g_malloc0(sizeof(HVFState));
+
+ s->num_slots = 32;
+ for (x = 0; x < s->num_slots; ++x) {
+ s->slots[x].size = 0;
+ s->slots[x].slot_id = x;
+ }
+
+ hvf_state = s;
+ cpu_interrupt_handler = hvf_handle_interrupt;
+ memory_listener_register(&hvf_memory_listener, &address_space_memory);
+ memory_listener_register(&hvf_io_listener, &address_space_io);
+ return 0;
+}
+
+static void hvf_accel_class_init(ObjectClass *oc, void *data)
+{
+ AccelClass *ac = ACCEL_CLASS(oc);
+ ac->name = "HVF";
+ ac->init_machine = hvf_accel_init;
+ ac->allowed = &hvf_allowed;
+}
+
+static const TypeInfo hvf_accel_type = {
+ .name = TYPE_HVF_ACCEL,
+ .parent = TYPE_ACCEL,
+ .class_init = hvf_accel_class_init,
+};
+
+static void hvf_type_init(void)
+{
+ type_register_static(&hvf_accel_type);
+}
+
+type_init(hvf_type_init);
diff --git a/target/i386/hvf-i386.h b/target/i386/hvf-i386.h
new file mode 100644
index 0000000000..f3f958058a
--- /dev/null
+++ b/target/i386/hvf-i386.h
@@ -0,0 +1,48 @@
+/*
+ * QEMU Hypervisor.framework (HVF) support
+ *
+ * Copyright 2017 Google Inc
+ *
+ * Adapted from target-i386/hax-i386.h:
+ * Copyright (c) 2011 Intel Corporation
+ * Written by:
+ * Jiang Yunhong<yunhong.jiang@intel.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef _HVF_I386_H
+#define _HVF_I386_H
+
+#include "sysemu/hvf.h"
+#include "cpu.h"
+#include "hvf-utils/x86.h"
+
+#define HVF_MAX_VCPU 0x10
+#define MAX_VM_ID 0x40
+#define MAX_VCPU_ID 0x40
+
+extern struct hvf_state hvf_global;
+
+struct hvf_vm {
+ int id;
+ struct hvf_vcpu_state *vcpus[HVF_MAX_VCPU];
+};
+
+struct hvf_state {
+ uint32_t version;
+ struct hvf_vm *vm;
+ uint64_t mem_quota;
+};
+
+#ifdef NEED_CPU_H
+/* Functions exported to host specific mode */
+
+/* Host specific functions */
+int hvf_inject_interrupt(CPUArchState * env, int vector);
+int hvf_vcpu_run(struct hvf_vcpu_state *vcpu);
+#endif
+
+#endif
diff --git a/target/i386/hvf-utils/Makefile.objs b/target/i386/hvf-utils/Makefile.objs
new file mode 100644
index 0000000000..7df219ad9c
--- /dev/null
+++ b/target/i386/hvf-utils/Makefile.objs
@@ -0,0 +1 @@
+obj-y += x86.o x86_cpuid.o x86_decode.o x86_descr.o x86_emu.o x86_flags.o x86_mmu.o x86hvf.o
diff --git a/target/i386/hvf-utils/README.md b/target/i386/hvf-utils/README.md
new file mode 100644
index 0000000000..0d27a0d52b
--- /dev/null
+++ b/target/i386/hvf-utils/README.md
@@ -0,0 +1,7 @@
+# OS X Hypervisor.framework support in QEMU
+
+These sources (and ../hvf-all.c) are adapted from Veertu Inc's vdhh (Veertu Desktop Hosted Hypervisor) (last known location: https://github.com/veertuinc/vdhh) with some minor changes, the most significant of which were:
+
+1. Adapt to our current QEMU's `CPUState` structure and `address_space_rw` API; many struct members have been moved around (emulated x86 state, kvm_xsave_buf) due to historical differences + QEMU needing to handle more emulation targets.
+2. Removal of `apic_page` and hyperv-related functionality.
+3. More relaxed use of `qemu_mutex_lock_iothread`.
diff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf-utils/vmcs.h
new file mode 100644
index 0000000000..6f7ccb361a
--- /dev/null
+++ b/target/i386/hvf-utils/vmcs.h
@@ -0,0 +1,368 @@
+/*-
+ * Copyright (c) 2011 NetApp, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _VMCS_H_
+#define _VMCS_H_
+
+#include <Hypervisor/hv.h>
+#include <Hypervisor/hv_vmx.h>
+
+#define VMCS_INITIAL 0xffffffffffffffff
+
+#define VMCS_IDENT(encoding) ((encoding) | 0x80000000)
+/*
+ * VMCS field encodings from Appendix H, Intel Architecture Manual Vol3B.
+ */
+#define VMCS_INVALID_ENCODING 0xffffffff
+
+/* 16-bit control fields */
+#define VMCS_VPID 0x00000000
+#define VMCS_PIR_VECTOR 0x00000002
+
+/* 16-bit guest-state fields */
+#define VMCS_GUEST_ES_SELECTOR 0x00000800
+#define VMCS_GUEST_CS_SELECTOR 0x00000802
+#define VMCS_GUEST_SS_SELECTOR 0x00000804
+#define VMCS_GUEST_DS_SELECTOR 0x00000806
+#define VMCS_GUEST_FS_SELECTOR 0x00000808
+#define VMCS_GUEST_GS_SELECTOR 0x0000080A
+#define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
+#define VMCS_GUEST_TR_SELECTOR 0x0000080E
+#define VMCS_GUEST_INTR_STATUS 0x00000810
+
+/* 16-bit host-state fields */
+#define VMCS_HOST_ES_SELECTOR 0x00000C00
+#define VMCS_HOST_CS_SELECTOR 0x00000C02
+#define VMCS_HOST_SS_SELECTOR 0x00000C04
+#define VMCS_HOST_DS_SELECTOR 0x00000C06
+#define VMCS_HOST_FS_SELECTOR 0x00000C08
+#define VMCS_HOST_GS_SELECTOR 0x00000C0A
+#define VMCS_HOST_TR_SELECTOR 0x00000C0C
+
+/* 64-bit control fields */
+#define VMCS_IO_BITMAP_A 0x00002000
+#define VMCS_IO_BITMAP_B 0x00002002
+#define VMCS_MSR_BITMAP 0x00002004
+#define VMCS_EXIT_MSR_STORE 0x00002006
+#define VMCS_EXIT_MSR_LOAD 0x00002008
+#define VMCS_ENTRY_MSR_LOAD 0x0000200A
+#define VMCS_EXECUTIVE_VMCS 0x0000200C
+#define VMCS_TSC_OFFSET 0x00002010
+#define VMCS_VIRTUAL_APIC 0x00002012
+#define VMCS_APIC_ACCESS 0x00002014
+#define VMCS_PIR_DESC 0x00002016
+#define VMCS_EPTP 0x0000201A
+#define VMCS_EOI_EXIT0 0x0000201C
+#define VMCS_EOI_EXIT1 0x0000201E
+#define VMCS_EOI_EXIT2 0x00002020
+#define VMCS_EOI_EXIT3 0x00002022
+#define VMCS_EOI_EXIT(vector) (VMCS_EOI_EXIT0 + ((vector) / 64) * 2)
+
+/* 64-bit read-only fields */
+#define VMCS_GUEST_PHYSICAL_ADDRESS 0x00002400
+
+/* 64-bit guest-state fields */
+#define VMCS_LINK_POINTER 0x00002800
+#define VMCS_GUEST_IA32_DEBUGCTL 0x00002802
+#define VMCS_GUEST_IA32_PAT 0x00002804
+#define VMCS_GUEST_IA32_EFER 0x00002806
+#define VMCS_GUEST_IA32_PERF_GLOBAL_CTRL 0x00002808
+#define VMCS_GUEST_PDPTE0 0x0000280A
+#define VMCS_GUEST_PDPTE1 0x0000280C
+#define VMCS_GUEST_PDPTE2 0x0000280E
+#define VMCS_GUEST_PDPTE3 0x00002810
+
+/* 64-bit host-state fields */
+#define VMCS_HOST_IA32_PAT 0x00002C00
+#define VMCS_HOST_IA32_EFER 0x00002C02
+#define VMCS_HOST_IA32_PERF_GLOBAL_CTRL 0x00002C04
+
+/* 32-bit control fields */
+#define VMCS_PIN_BASED_CTLS 0x00004000
+#define VMCS_PRI_PROC_BASED_CTLS 0x00004002
+#define VMCS_EXCEPTION_BITMAP 0x00004004
+#define VMCS_PF_ERROR_MASK 0x00004006
+#define VMCS_PF_ERROR_MATCH 0x00004008
+#define VMCS_CR3_TARGET_COUNT 0x0000400A
+#define VMCS_EXIT_CTLS 0x0000400C
+#define VMCS_EXIT_MSR_STORE_COUNT 0x0000400E
+#define VMCS_EXIT_MSR_LOAD_COUNT 0x00004010
+#define VMCS_ENTRY_CTLS 0x00004012
+#define VMCS_ENTRY_MSR_LOAD_COUNT 0x00004014
+#define VMCS_ENTRY_INTR_INFO 0x00004016
+#define VMCS_ENTRY_EXCEPTION_ERROR 0x00004018
+#define VMCS_ENTRY_INST_LENGTH 0x0000401A
+#define VMCS_TPR_THRESHOLD 0x0000401C
+#define VMCS_SEC_PROC_BASED_CTLS 0x0000401E
+#define VMCS_PLE_GAP 0x00004020
+#define VMCS_PLE_WINDOW 0x00004022
+
+/* 32-bit read-only data fields */
+#define VMCS_INSTRUCTION_ERROR 0x00004400
+#define VMCS_EXIT_REASON 0x00004402
+#define VMCS_EXIT_INTR_INFO 0x00004404
+#define VMCS_EXIT_INTR_ERRCODE 0x00004406
+#define VMCS_IDT_VECTORING_INFO 0x00004408
+#define VMCS_IDT_VECTORING_ERROR 0x0000440A
+#define VMCS_EXIT_INSTRUCTION_LENGTH 0x0000440C
+#define VMCS_EXIT_INSTRUCTION_INFO 0x0000440E
+
+/* 32-bit guest-state fields */
+#define VMCS_GUEST_ES_LIMIT 0x00004800
+#define VMCS_GUEST_CS_LIMIT 0x00004802
+#define VMCS_GUEST_SS_LIMIT 0x00004804
+#define VMCS_GUEST_DS_LIMIT 0x00004806
+#define VMCS_GUEST_FS_LIMIT 0x00004808
+#define VMCS_GUEST_GS_LIMIT 0x0000480A
+#define VMCS_GUEST_LDTR_LIMIT 0x0000480C
+#define VMCS_GUEST_TR_LIMIT 0x0000480E
+#define VMCS_GUEST_GDTR_LIMIT 0x00004810
+#define VMCS_GUEST_IDTR_LIMIT 0x00004812
+#define VMCS_GUEST_ES_ACCESS_RIGHTS 0x00004814
+#define VMCS_GUEST_CS_ACCESS_RIGHTS 0x00004816
+#define VMCS_GUEST_SS_ACCESS_RIGHTS 0x00004818
+#define VMCS_GUEST_DS_ACCESS_RIGHTS 0x0000481A
+#define VMCS_GUEST_FS_ACCESS_RIGHTS 0x0000481C
+#define VMCS_GUEST_GS_ACCESS_RIGHTS 0x0000481E
+#define VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x00004820
+#define VMCS_GUEST_TR_ACCESS_RIGHTS 0x00004822
+#define VMCS_GUEST_INTERRUPTIBILITY 0x00004824
+#define VMCS_GUEST_ACTIVITY 0x00004826
+#define VMCS_GUEST_SMBASE 0x00004828
+#define VMCS_GUEST_IA32_SYSENTER_CS 0x0000482A
+#define VMCS_PREEMPTION_TIMER_VALUE 0x0000482E
+
+/* 32-bit host state fields */
+#define VMCS_HOST_IA32_SYSENTER_CS 0x00004C00
+
+/* Natural Width control fields */
+#define VMCS_CR0_MASK 0x00006000
+#define VMCS_CR4_MASK 0x00006002
+#define VMCS_CR0_SHADOW 0x00006004
+#define VMCS_CR4_SHADOW 0x00006006
+#define VMCS_CR3_TARGET0 0x00006008
+#define VMCS_CR3_TARGET1 0x0000600A
+#define VMCS_CR3_TARGET2 0x0000600C
+#define VMCS_CR3_TARGET3 0x0000600E
+
+/* Natural Width read-only fields */
+#define VMCS_EXIT_QUALIFICATION 0x00006400
+#define VMCS_IO_RCX 0x00006402
+#define VMCS_IO_RSI 0x00006404
+#define VMCS_IO_RDI 0x00006406
+#define VMCS_IO_RIP 0x00006408
+#define VMCS_GUEST_LINEAR_ADDRESS 0x0000640A
+
+/* Natural Width guest-state fields */
+#define VMCS_GUEST_CR0 0x00006800
+#define VMCS_GUEST_CR3 0x00006802
+#define VMCS_GUEST_CR4 0x00006804
+#define VMCS_GUEST_ES_BASE 0x00006806
+#define VMCS_GUEST_CS_BASE 0x00006808
+#define VMCS_GUEST_SS_BASE 0x0000680A
+#define VMCS_GUEST_DS_BASE 0x0000680C
+#define VMCS_GUEST_FS_BASE 0x0000680E
+#define VMCS_GUEST_GS_BASE 0x00006810
+#define VMCS_GUEST_LDTR_BASE 0x00006812
+#define VMCS_GUEST_TR_BASE 0x00006814
+#define VMCS_GUEST_GDTR_BASE 0x00006816
+#define VMCS_GUEST_IDTR_BASE 0x00006818
+#define VMCS_GUEST_DR7 0x0000681A
+#define VMCS_GUEST_RSP 0x0000681C
+#define VMCS_GUEST_RIP 0x0000681E
+#define VMCS_GUEST_RFLAGS 0x00006820
+#define VMCS_GUEST_PENDING_DBG_EXCEPTIONS 0x00006822
+#define VMCS_GUEST_IA32_SYSENTER_ESP 0x00006824
+#define VMCS_GUEST_IA32_SYSENTER_EIP 0x00006826
+
+/* Natural Width host-state fields */
+#define VMCS_HOST_CR0 0x00006C00
+#define VMCS_HOST_CR3 0x00006C02
+#define VMCS_HOST_CR4 0x00006C04
+#define VMCS_HOST_FS_BASE 0x00006C06
+#define VMCS_HOST_GS_BASE 0x00006C08
+#define VMCS_HOST_TR_BASE 0x00006C0A
+#define VMCS_HOST_GDTR_BASE 0x00006C0C
+#define VMCS_HOST_IDTR_BASE 0x00006C0E
+#define VMCS_HOST_IA32_SYSENTER_ESP 0x00006C10
+#define VMCS_HOST_IA32_SYSENTER_EIP 0x00006C12
+#define VMCS_HOST_RSP 0x00006C14
+#define VMCS_HOST_RIP 0x00006c16
+
+/*
+ * VM instruction error numbers
+ */
+#define VMRESUME_WITH_NON_LAUNCHED_VMCS 5
+
+/*
+ * VMCS exit reasons
+ */
+#define EXIT_REASON_EXCEPTION 0
+#define EXIT_REASON_EXT_INTR 1
+#define EXIT_REASON_TRIPLE_FAULT 2
+#define EXIT_REASON_INIT 3
+#define EXIT_REASON_SIPI 4
+#define EXIT_REASON_IO_SMI 5
+#define EXIT_REASON_SMI 6
+#define EXIT_REASON_INTR_WINDOW 7
+#define EXIT_REASON_NMI_WINDOW 8
+#define EXIT_REASON_TASK_SWITCH 9
+#define EXIT_REASON_CPUID 10
+#define EXIT_REASON_GETSEC 11
+#define EXIT_REASON_HLT 12
+#define EXIT_REASON_INVD 13
+#define EXIT_REASON_INVLPG 14
+#define EXIT_REASON_RDPMC 15
+#define EXIT_REASON_RDTSC 16
+#define EXIT_REASON_RSM 17
+#define EXIT_REASON_VMCALL 18
+#define EXIT_REASON_VMCLEAR 19
+#define EXIT_REASON_VMLAUNCH 20
+#define EXIT_REASON_VMPTRLD 21
+#define EXIT_REASON_VMPTRST 22
+#define EXIT_REASON_VMREAD 23
+#define EXIT_REASON_VMRESUME 24
+#define EXIT_REASON_VMWRITE 25
+#define EXIT_REASON_VMXOFF 26
+#define EXIT_REASON_VMXON 27
+#define EXIT_REASON_CR_ACCESS 28
+#define EXIT_REASON_DR_ACCESS 29
+#define EXIT_REASON_INOUT 30
+#define EXIT_REASON_RDMSR 31
+#define EXIT_REASON_WRMSR 32
+#define EXIT_REASON_INVAL_VMCS 33
+#define EXIT_REASON_INVAL_MSR 34
+#define EXIT_REASON_MWAIT 36
+#define EXIT_REASON_MTF 37
+#define EXIT_REASON_MONITOR 39
+#define EXIT_REASON_PAUSE 40
+#define EXIT_REASON_MCE_DURING_ENTRY 41
+#define EXIT_REASON_TPR 43
+#define EXIT_REASON_APIC_ACCESS 44
+#define EXIT_REASON_VIRTUALIZED_EOI 45
+#define EXIT_REASON_GDTR_IDTR 46
+#define EXIT_REASON_LDTR_TR 47
+#define EXIT_REASON_EPT_FAULT 48
+#define EXIT_REASON_EPT_MISCONFIG 49
+#define EXIT_REASON_INVEPT 50
+#define EXIT_REASON_RDTSCP 51
+#define EXIT_REASON_VMX_PREEMPT 52
+#define EXIT_REASON_INVVPID 53
+#define EXIT_REASON_WBINVD 54
+#define EXIT_REASON_XSETBV 55
+#define EXIT_REASON_APIC_WRITE 56
+
+/*
+ * NMI unblocking due to IRET.
+ *
+ * Applies to VM-exits due to hardware exception or EPT fault.
+ */
+#define EXIT_QUAL_NMIUDTI (1 << 12)
+/*
+ * VMCS interrupt information fields
+ */
+#define VMCS_INTR_VALID (1U << 31)
+#define VMCS_INTR_T_MASK 0x700 /* Interruption-info type */
+#define VMCS_INTR_T_HWINTR (0 << 8)
+#define VMCS_INTR_T_NMI (2 << 8)
+#define VMCS_INTR_T_HWEXCEPTION (3 << 8)
+#define VMCS_INTR_T_SWINTR (4 << 8)
+#define VMCS_INTR_T_PRIV_SWEXCEPTION (5 << 8)
+#define VMCS_INTR_T_SWEXCEPTION (6 << 8)
+#define VMCS_INTR_DEL_ERRCODE (1 << 11)
+
+/*
+ * VMCS IDT-Vectoring information fields
+ */
+#define VMCS_IDT_VEC_VALID (1U << 31)
+#define VMCS_IDT_VEC_TYPE 0x700
+#define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11)
+#define VMCS_IDT_VEC_HWINTR (0 << 8)
+#define VMCS_IDT_VEC_NMI (2 << 8)
+#define VMCS_IDT_VEC_HWEXCEPTION (3 << 8)
+#define VMCS_IDT_VEC_SWINTR (4 << 8)
+
+/*
+ * VMCS Guest interruptibility field
+ */
+#define VMCS_INTERRUPTIBILITY_STI_BLOCKING (1 << 0)
+#define VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING (1 << 1)
+#define VMCS_INTERRUPTIBILITY_SMI_BLOCKING (1 << 2)
+#define VMCS_INTERRUPTIBILITY_NMI_BLOCKING (1 << 3)
+
+/*
+ * Exit qualification for EXIT_REASON_INVAL_VMCS
+ */
+#define EXIT_QUAL_NMI_WHILE_STI_BLOCKING 3
+
+/*
+ * Exit qualification for EPT violation
+ */
+#define EPT_VIOLATION_DATA_READ (1UL << 0)
+#define EPT_VIOLATION_DATA_WRITE (1UL << 1)
+#define EPT_VIOLATION_INST_FETCH (1UL << 2)
+#define EPT_VIOLATION_GPA_READABLE (1UL << 3)
+#define EPT_VIOLATION_GPA_WRITEABLE (1UL << 4)
+#define EPT_VIOLATION_GPA_EXECUTABLE (1UL << 5)
+#define EPT_VIOLATION_GLA_VALID (1UL << 7)
+#define EPT_VIOLATION_XLAT_VALID (1UL << 8)
+
+/*
+ * Exit qualification for APIC-access VM exit
+ */
+#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
+#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
+
+/*
+ * Exit qualification for APIC-write VM exit
+ */
+#define APIC_WRITE_OFFSET(qual) ((qual) & 0xFFF)
+
+
+#define VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING (1 << 2)
+#define VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET (1 << 3)
+#define VMCS_PRI_PROC_BASED_CTLS_HLT (1 << 7)
+#define VMCS_PRI_PROC_BASED_CTLS_MWAIT (1 << 10)
+#define VMCS_PRI_PROC_BASED_CTLS_TSC (1 << 12)
+#define VMCS_PRI_PROC_BASED_CTLS_CR8_LOAD (1 << 19)
+#define VMCS_PRI_PROC_BASED_CTLS_CR8_STORE (1 << 20)
+#define VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW (1 << 21)
+#define VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING (1 << 22)
+#define VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL (1 << 31)
+
+#define VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES (1 << 0)
+#define VMCS_PRI_PROC_BASED2_CTLS_X2APIC (1 << 4)
+
+enum task_switch_reason {
+ TSR_CALL,
+ TSR_IRET,
+ TSR_JMP,
+ TSR_IDT_GATE, /* task gate in IDT */
+};
+
+#endif
diff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf-utils/vmx.h
new file mode 100644
index 0000000000..8a080e6777
--- /dev/null
+++ b/target/i386/hvf-utils/vmx.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ * Based on Veertu vddh/vmm/vmx.h
+ *
+ * Interfaces to Hypervisor.framework to read/write X86 registers and VMCS.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef VMX_H
+#define VMX_H
+
+#include <stdint.h>
+#include <Hypervisor/hv.h>
+#include <Hypervisor/hv_vmx.h>
+#include "vmcs.h"
+#include "cpu.h"
+#include "x86.h"
+
+#include "exec/address-spaces.h"
+
+static uint64_t inline rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg)
+{
+ uint64_t v;
+
+ if (hv_vcpu_read_register(vcpu, reg, &v)) {
+ abort();
+ }
+
+ return v;
+}
+
+/* write GPR */
+static void inline wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v)
+{
+ if (hv_vcpu_write_register(vcpu, reg, v)) {
+ abort();
+ }
+}
+
+/* read VMCS field */
+static uint64_t inline rvmcs(hv_vcpuid_t vcpu, uint32_t field)
+{
+ uint64_t v;
+
+ hv_vmx_vcpu_read_vmcs(vcpu, field, &v);
+
+ return v;
+}
+
+/* write VMCS field */
+static void inline wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v)
+{
+ hv_vmx_vcpu_write_vmcs(vcpu, field, v);
+}
+
+/* desired control word constrained by hardware/hypervisor capabilities */
+static uint64_t inline cap2ctrl(uint64_t cap, uint64_t ctrl)
+{
+ return (ctrl | (cap & 0xffffffff)) & (cap >> 32);
+}
+
+#define VM_ENTRY_GUEST_LMA (1LL << 9)
+
+#define AR_TYPE_ACCESSES_MASK 1
+#define AR_TYPE_READABLE_MASK (1 << 1)
+#define AR_TYPE_WRITEABLE_MASK (1 << 2)
+#define AR_TYPE_CODE_MASK (1 << 3)
+#define AR_TYPE_MASK 0x0f
+#define AR_TYPE_BUSY_64_TSS 11
+#define AR_TYPE_BUSY_32_TSS 11
+#define AR_TYPE_BUSY_16_TSS 3
+#define AR_TYPE_LDT 2
+
+static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
+{
+ uint64_t entry_ctls;
+
+ efer |= EFER_LMA;
+ wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
+ entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
+ wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | VM_ENTRY_GUEST_LMA);
+
+ uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS);
+ if ((efer & EFER_LME) && (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
+ wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS);
+ }
+}
+
+static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
+{
+ uint64_t entry_ctls;
+
+ entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
+ wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA);
+
+ efer &= ~EFER_LMA;
+ wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
+}
+
+static void inline macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
+{
+ int i;
+ uint64_t pdpte[4] = {0, 0, 0, 0};
+ uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER);
+ uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0);
+
+ if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & EFER_LME))
+ address_space_rw(&address_space_memory, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
+ MEMTXATTRS_UNSPECIFIED,
+ (uint8_t *)pdpte, 32, 0);
+
+ for (i = 0; i < 4; i++)
+ wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
+
+ wvmcs(vcpu, VMCS_CR0_MASK, CR0_CD | CR0_NE | CR0_PG);
+ wvmcs(vcpu, VMCS_CR0_SHADOW, cr0);
+
+ cr0 &= ~CR0_CD;
+ wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE| CR0_ET);
+
+ if (efer & EFER_LME) {
+ if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG))
+ enter_long_mode(vcpu, cr0, efer);
+ if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG))
+ exit_long_mode(vcpu, cr0, efer);
+ }
+
+ hv_vcpu_invalidate_tlb(vcpu);
+ hv_vcpu_flush(vcpu);
+}
+
+static void inline macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
+{
+ uint64_t guest_cr4 = cr4 | CR4_VMXE;
+
+ wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4);
+ wvmcs(vcpu, VMCS_CR4_SHADOW, cr4);
+
+ hv_vcpu_invalidate_tlb(vcpu);
+ hv_vcpu_flush(vcpu);
+}
+
+static void inline macvm_set_rip(CPUState *cpu, uint64_t rip)
+{
+ uint64_t val;
+
+ /* BUG, should take considering overlap.. */
+ wreg(cpu->hvf_fd, HV_X86_RIP, rip);
+
+ /* after moving forward in rip, we need to clean INTERRUPTABILITY */
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
+ if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING))
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY,
+ val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
+}
+
+static void inline vmx_clear_nmi_blocking(CPUState *cpu)
+{
+ uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
+ gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
+}
+
+static void inline vmx_set_nmi_blocking(CPUState *cpu)
+{
+ uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
+ gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
+}
+
+static void inline vmx_set_nmi_window_exiting(CPUState *cpu)
+{
+ uint64_t val;
+ val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
+
+}
+
+static void inline vmx_clear_nmi_window_exiting(CPUState *cpu)
+{
+
+ uint64_t val;
+ val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
+}
+
+#endif
diff --git a/target/i386/hvf-utils/x86.c b/target/i386/hvf-utils/x86.c
new file mode 100644
index 0000000000..e3db2c9c8b
--- /dev/null
+++ b/target/i386/hvf-utils/x86.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+
+#include "qemu-common.h"
+#include "x86_decode.h"
+#include "x86_emu.h"
+#include "vmcs.h"
+#include "vmx.h"
+#include "x86_mmu.h"
+#include "x86_descr.h"
+
+static uint32_t x86_segment_access_rights(struct x86_segment_descriptor *var)
+{
+ uint32_t ar;
+
+ if (!var->p) {
+ ar = 1 << 16;
+ return ar;
+ }
+
+ ar = var->type & 15;
+ ar |= (var->s & 1) << 4;
+ ar |= (var->dpl & 3) << 5;
+ ar |= (var->p & 1) << 7;
+ ar |= (var->avl & 1) << 12;
+ ar |= (var->l & 1) << 13;
+ ar |= (var->db & 1) << 14;
+ ar |= (var->g & 1) << 15;
+ return ar;
+}
+
+bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
+{
+ addr_t base;
+ uint32_t limit;
+
+ ZERO_INIT(*desc);
+ // valid gdt descriptors start from index 1
+ if (!sel.index && GDT_SEL == sel.ti)
+ return false;
+
+ if (GDT_SEL == sel.ti) {
+ base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);
+ limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
+ } else {
+ base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);
+ limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);
+ }
+
+ if (sel.index * 8 >= limit)
+ return false;
+
+ vmx_read_mem(cpu, desc, base + sel.index * 8, sizeof(*desc));
+ return true;
+}
+
+bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
+{
+ addr_t base;
+ uint32_t limit;
+
+ if (GDT_SEL == sel.ti) {
+ base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);
+ limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
+ } else {
+ base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);
+ limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);
+ }
+
+ if (sel.index * 8 >= limit) {
+ printf("%s: gdt limit\n", __FUNCTION__);
+ return false;
+ }
+ vmx_write_mem(cpu, base + sel.index * 8, desc, sizeof(*desc));
+ return true;
+}
+
+bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate)
+{
+ addr_t base = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE);
+ uint32_t limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT);
+
+ ZERO_INIT(*idt_desc);
+ if (gate * 8 >= limit) {
+ printf("%s: idt limit\n", __FUNCTION__);
+ return false;
+ }
+
+ vmx_read_mem(cpu, idt_desc, base + gate * 8, sizeof(*idt_desc));
+ return true;
+}
+
+bool x86_is_protected(struct CPUState *cpu)
+{
+ uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
+ return cr0 & CR0_PE;
+}
+
+bool x86_is_real(struct CPUState *cpu)
+{
+ return !x86_is_protected(cpu);
+}
+
+bool x86_is_v8086(struct CPUState *cpu)
+{
+ return (x86_is_protected(cpu) && (RFLAGS(cpu) & RFLAGS_VM));
+}
+
+bool x86_is_long_mode(struct CPUState *cpu)
+{
+ return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & EFER_LMA;
+}
+
+bool x86_is_long64_mode(struct CPUState *cpu)
+{
+ struct vmx_segment desc;
+ vmx_read_segment_descriptor(cpu, &desc, REG_SEG_CS);
+
+ return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1);
+}
+
+bool x86_is_paging_mode(struct CPUState *cpu)
+{
+ uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
+ return cr0 & CR0_PG;
+}
+
+bool x86_is_pae_enabled(struct CPUState *cpu)
+{
+ uint64_t cr4 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4);
+ return cr4 & CR4_PAE;
+}
+
+addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg)
+{
+ return vmx_read_segment_base(cpu, seg) + addr;
+}
+
+addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg)
+{
+ switch (size) {
+ case 2:
+ addr = (uint16_t)addr;
+ break;
+ case 4:
+ addr = (uint32_t)addr;
+ break;
+ default:
+ break;
+ }
+ return linear_addr(cpu, addr, seg);
+}
+
+addr_t linear_rip(struct CPUState *cpu, addr_t rip)
+{
+ return linear_addr(cpu, rip, REG_SEG_CS);
+}
diff --git a/target/i386/hvf-utils/x86.h b/target/i386/hvf-utils/x86.h
new file mode 100644
index 0000000000..5dffdd6568
--- /dev/null
+++ b/target/i386/hvf-utils/x86.h
@@ -0,0 +1,470 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Veertu Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <stdarg.h>
+#include "qemu-common.h"
+#include "x86_flags.h"
+
+// exceptions
+typedef enum x86_exception {
+ EXCEPTION_DE, // divide error
+ EXCEPTION_DB, // debug fault
+ EXCEPTION_NMI, // non-maskable interrupt
+ EXCEPTION_BP, // breakpoint trap
+ EXCEPTION_OF, // overflow trap
+ EXCEPTION_BR, // boundary range exceeded fault
+ EXCEPTION_UD, // undefined opcode
+ EXCEPTION_NM, // device not available
+ EXCEPTION_DF, // double fault
+ EXCEPTION_RSVD, // not defined
+ EXCEPTION_TS, // invalid TSS fault
+ EXCEPTION_NP, // not present fault
+ EXCEPTION_GP, // general protection fault
+ EXCEPTION_PF, // page fault
+ EXCEPTION_RSVD2, // not defined
+} x86_exception;
+
+// general purpose regs
+typedef enum x86_reg_name {
+ REG_RAX = 0,
+ REG_RCX = 1,
+ REG_RDX = 2,
+ REG_RBX = 3,
+ REG_RSP = 4,
+ REG_RBP = 5,
+ REG_RSI = 6,
+ REG_RDI = 7,
+ REG_R8 = 8,
+ REG_R9 = 9,
+ REG_R10 = 10,
+ REG_R11 = 11,
+ REG_R12 = 12,
+ REG_R13 = 13,
+ REG_R14 = 14,
+ REG_R15 = 15,
+} x86_reg_name;
+
+// segment regs
+typedef enum x86_reg_segment {
+ REG_SEG_ES = 0,
+ REG_SEG_CS = 1,
+ REG_SEG_SS = 2,
+ REG_SEG_DS = 3,
+ REG_SEG_FS = 4,
+ REG_SEG_GS = 5,
+ REG_SEG_LDTR = 6,
+ REG_SEG_TR = 7,
+} x86_reg_segment;
+
+typedef struct x86_register
+{
+ union {
+ struct {
+ uint64_t rrx; // full 64 bit
+ };
+ struct {
+ uint32_t erx; // low 32 bit part
+ uint32_t hi32_unused1;
+ };
+ struct {
+ uint16_t rx; // low 16 bit part
+ uint16_t hi16_unused1;
+ uint32_t hi32_unused2;
+ };
+ struct {
+ uint8_t lx; // low 8 bit part
+ uint8_t hx; // high 8 bit
+ uint16_t hi16_unused2;
+ uint32_t hi32_unused3;
+ };
+ };
+} __attribute__ ((__packed__)) x86_register;
+
+typedef enum x86_rflags {
+ RFLAGS_CF = (1L << 0),
+ RFLAGS_PF = (1L << 2),
+ RFLAGS_AF = (1L << 4),
+ RFLAGS_ZF = (1L << 6),
+ RFLAGS_SF = (1L << 7),
+ RFLAGS_TF = (1L << 8),
+ RFLAGS_IF = (1L << 9),
+ RFLAGS_DF = (1L << 10),
+ RFLAGS_OF = (1L << 11),
+ RFLAGS_IOPL = (3L << 12),
+ RFLAGS_NT = (1L << 14),
+ RFLAGS_RF = (1L << 16),
+ RFLAGS_VM = (1L << 17),
+ RFLAGS_AC = (1L << 18),
+ RFLAGS_VIF = (1L << 19),
+ RFLAGS_VIP = (1L << 20),
+ RFLAGS_ID = (1L << 21),
+} x86_rflags;
+
+// rflags register
+typedef struct x86_reg_flags {
+ union {
+ struct {
+ uint64_t rflags;
+ };
+ struct {
+ uint32_t eflags;
+ uint32_t hi32_unused1;
+ };
+ struct {
+ uint32_t cf:1;
+ uint32_t unused1:1;
+ uint32_t pf:1;
+ uint32_t unused2:1;
+ uint32_t af:1;
+ uint32_t unused3:1;
+ uint32_t zf:1;
+ uint32_t sf:1;
+ uint32_t tf:1;
+ uint32_t ief:1;
+ uint32_t df:1;
+ uint32_t of:1;
+ uint32_t iopl:2;
+ uint32_t nt:1;
+ uint32_t unused4:1;
+ uint32_t rf:1;
+ uint32_t vm:1;
+ uint32_t ac:1;
+ uint32_t vif:1;
+ uint32_t vip:1;
+ uint32_t id:1;
+ uint32_t unused5:10;
+ uint32_t hi32_unused2;
+ };
+ };
+} __attribute__ ((__packed__)) x86_reg_flags;
+
+typedef enum x86_reg_efer {
+ EFER_SCE = (1L << 0),
+ EFER_LME = (1L << 8),
+ EFER_LMA = (1L << 10),
+ EFER_NXE = (1L << 11),
+ EFER_SVME = (1L << 12),
+ EFER_FXSR = (1L << 14),
+} x86_reg_efer;
+
+typedef struct x86_efer {
+ uint64_t efer;
+} __attribute__ ((__packed__)) x86_efer;
+
+typedef enum x86_reg_cr0 {
+ CR0_PE = (1L << 0),
+ CR0_MP = (1L << 1),
+ CR0_EM = (1L << 2),
+ CR0_TS = (1L << 3),
+ CR0_ET = (1L << 4),
+ CR0_NE = (1L << 5),
+ CR0_WP = (1L << 16),
+ CR0_AM = (1L << 18),
+ CR0_NW = (1L << 29),
+ CR0_CD = (1L << 30),
+ CR0_PG = (1L << 31),
+} x86_reg_cr0;
+
+typedef enum x86_reg_cr4 {
+ CR4_VME = (1L << 0),
+ CR4_PVI = (1L << 1),
+ CR4_TSD = (1L << 2),
+ CR4_DE = (1L << 3),
+ CR4_PSE = (1L << 4),
+ CR4_PAE = (1L << 5),
+ CR4_MSE = (1L << 6),
+ CR4_PGE = (1L << 7),
+ CR4_PCE = (1L << 8),
+ CR4_OSFXSR = (1L << 9),
+ CR4_OSXMMEXCPT = (1L << 10),
+ CR4_VMXE = (1L << 13),
+ CR4_SMXE = (1L << 14),
+ CR4_FSGSBASE = (1L << 16),
+ CR4_PCIDE = (1L << 17),
+ CR4_OSXSAVE = (1L << 18),
+ CR4_SMEP = (1L << 20),
+} x86_reg_cr4;
+
+// 16 bit Task State Segment
+typedef struct x86_tss_segment16 {
+ uint16_t link;
+ uint16_t sp0;
+ uint16_t ss0;
+ uint32_t sp1;
+ uint16_t ss1;
+ uint32_t sp2;
+ uint16_t ss2;
+ uint16_t ip;
+ uint16_t flags;
+ uint16_t ax;
+ uint16_t cx;
+ uint16_t dx;
+ uint16_t bx;
+ uint16_t sp;
+ uint16_t bp;
+ uint16_t si;
+ uint16_t di;
+ uint16_t es;
+ uint16_t cs;
+ uint16_t ss;
+ uint16_t ds;
+ uint16_t ldtr;
+} __attribute__((packed)) x86_tss_segment16;
+
+// 32 bit Task State Segment
+typedef struct x86_tss_segment32
+{
+ uint32_t prev_tss;
+ uint32_t esp0;
+ uint32_t ss0;
+ uint32_t esp1;
+ uint32_t ss1;
+ uint32_t esp2;
+ uint32_t ss2;
+ uint32_t cr3;
+ uint32_t eip;
+ uint32_t eflags;
+ uint32_t eax;
+ uint32_t ecx;
+ uint32_t edx;
+ uint32_t ebx;
+ uint32_t esp;
+ uint32_t ebp;
+ uint32_t esi;
+ uint32_t edi;
+ uint32_t es;
+ uint32_t cs;
+ uint32_t ss;
+ uint32_t ds;
+ uint32_t fs;
+ uint32_t gs;
+ uint32_t ldt;
+ uint16_t trap;
+ uint16_t iomap_base;
+} __attribute__ ((__packed__)) x86_tss_segment32;
+
+// 64 bit Task State Segment
+typedef struct x86_tss_segment64
+{
+ uint32_t unused;
+ uint64_t rsp0;
+ uint64_t rsp1;
+ uint64_t rsp2;
+ uint64_t unused1;
+ uint64_t ist1;
+ uint64_t ist2;
+ uint64_t ist3;
+ uint64_t ist4;
+ uint64_t ist5;
+ uint64_t ist6;
+ uint64_t ist7;
+ uint64_t unused2;
+ uint16_t unused3;
+ uint16_t iomap_base;
+} __attribute__ ((__packed__)) x86_tss_segment64;
+
+// segment descriptors
+typedef struct x86_segment_descriptor {
+ uint64_t limit0:16;
+ uint64_t base0:16;
+ uint64_t base1:8;
+ uint64_t type:4;
+ uint64_t s:1;
+ uint64_t dpl:2;
+ uint64_t p:1;
+ uint64_t limit1:4;
+ uint64_t avl:1;
+ uint64_t l:1;
+ uint64_t db:1;
+ uint64_t g:1;
+ uint64_t base2:8;
+} __attribute__ ((__packed__)) x86_segment_descriptor;
+
+static inline uint32_t x86_segment_base(x86_segment_descriptor *desc)
+{
+ return (uint32_t)((desc->base2 << 24) | (desc->base1 << 16) | desc->base0);
+}
+
+static inline void x86_set_segment_base(x86_segment_descriptor *desc, uint32_t base)
+{
+ desc->base2 = base >> 24;
+ desc->base1 = (base >> 16) & 0xff;
+ desc->base0 = base & 0xffff;
+}
+
+static inline uint32_t x86_segment_limit(x86_segment_descriptor *desc)
+{
+ uint32_t limit = (uint32_t)((desc->limit1 << 16) | desc->limit0);
+ if (desc->g)
+ return (limit << 12) | 0xfff;
+ return limit;
+}
+
+static inline void x86_set_segment_limit(x86_segment_descriptor *desc, uint32_t limit)
+{
+ desc->limit0 = limit & 0xffff;
+ desc->limit1 = limit >> 16;
+}
+
+typedef struct x86_call_gate {
+ uint64_t offset0:16;
+ uint64_t selector:16;
+ uint64_t param_count:4;
+ uint64_t reserved:3;
+ uint64_t type:4;
+ uint64_t dpl:1;
+ uint64_t p:1;
+ uint64_t offset1:16;
+} __attribute__ ((__packed__)) x86_call_gate;
+
+static inline uint32_t x86_call_gate_offset(x86_call_gate *gate)
+{
+ return (uint32_t)((gate->offset1 << 16) | gate->offset0);
+}
+
+#define LDT_SEL 0
+#define GDT_SEL 1
+
+typedef struct x68_segment_selector {
+ union {
+ uint16_t sel;
+ struct {
+ uint16_t rpl:3;
+ uint16_t ti:1;
+ uint16_t index:12;
+ };
+ };
+} __attribute__ ((__packed__)) x68_segment_selector;
+
+// Definition of hvf_x86_state is here
+struct hvf_x86_state {
+ int hlt;
+ uint64_t init_tsc;
+
+ int interruptable;
+ uint64_t exp_rip;
+ uint64_t fetch_rip;
+ uint64_t rip;
+ struct x86_register regs[16];
+ struct x86_reg_flags rflags;
+ struct lazy_flags lflags;
+ struct x86_efer efer;
+ uint8_t mmio_buf[4096];
+ uint8_t* apic_page;
+};
+
+/*
+* hvf xsave area
+*/
+struct hvf_xsave_buf {
+ uint32_t data[1024];
+};
+
+// useful register access macros
+#define RIP(cpu) (cpu->hvf_x86->rip)
+#define EIP(cpu) ((uint32_t)cpu->hvf_x86->rip)
+#define RFLAGS(cpu) (cpu->hvf_x86->rflags.rflags)
+#define EFLAGS(cpu) (cpu->hvf_x86->rflags.eflags)
+
+#define RRX(cpu, reg) (cpu->hvf_x86->regs[reg].rrx)
+#define RAX(cpu) RRX(cpu, REG_RAX)
+#define RCX(cpu) RRX(cpu, REG_RCX)
+#define RDX(cpu) RRX(cpu, REG_RDX)
+#define RBX(cpu) RRX(cpu, REG_RBX)
+#define RSP(cpu) RRX(cpu, REG_RSP)
+#define RBP(cpu) RRX(cpu, REG_RBP)
+#define RSI(cpu) RRX(cpu, REG_RSI)
+#define RDI(cpu) RRX(cpu, REG_RDI)
+#define R8(cpu) RRX(cpu, REG_R8)
+#define R9(cpu) RRX(cpu, REG_R9)
+#define R10(cpu) RRX(cpu, REG_R10)
+#define R11(cpu) RRX(cpu, REG_R11)
+#define R12(cpu) RRX(cpu, REG_R12)
+#define R13(cpu) RRX(cpu, REG_R13)
+#define R14(cpu) RRX(cpu, REG_R14)
+#define R15(cpu) RRX(cpu, REG_R15)
+
+#define ERX(cpu, reg) (cpu->hvf_x86->regs[reg].erx)
+#define EAX(cpu) ERX(cpu, REG_RAX)
+#define ECX(cpu) ERX(cpu, REG_RCX)
+#define EDX(cpu) ERX(cpu, REG_RDX)
+#define EBX(cpu) ERX(cpu, REG_RBX)
+#define ESP(cpu) ERX(cpu, REG_RSP)
+#define EBP(cpu) ERX(cpu, REG_RBP)
+#define ESI(cpu) ERX(cpu, REG_RSI)
+#define EDI(cpu) ERX(cpu, REG_RDI)
+
+#define RX(cpu, reg) (cpu->hvf_x86->regs[reg].rx)
+#define AX(cpu) RX(cpu, REG_RAX)
+#define CX(cpu) RX(cpu, REG_RCX)
+#define DX(cpu) RX(cpu, REG_RDX)
+#define BP(cpu) RX(cpu, REG_RBP)
+#define SP(cpu) RX(cpu, REG_RSP)
+#define BX(cpu) RX(cpu, REG_RBX)
+#define SI(cpu) RX(cpu, REG_RSI)
+#define DI(cpu) RX(cpu, REG_RDI)
+
+#define RL(cpu, reg) (cpu->hvf_x86->regs[reg].lx)
+#define AL(cpu) RL(cpu, REG_RAX)
+#define CL(cpu) RL(cpu, REG_RCX)
+#define DL(cpu) RL(cpu, REG_RDX)
+#define BL(cpu) RL(cpu, REG_RBX)
+
+#define RH(cpu, reg) (cpu->hvf_x86->regs[reg].hx)
+#define AH(cpu) RH(cpu, REG_RAX)
+#define CH(cpu) RH(cpu, REG_RCX)
+#define DH(cpu) RH(cpu, REG_RDX)
+#define BH(cpu) RH(cpu, REG_RBX)
+
+// deal with GDT/LDT descriptors in memory
+bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
+bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
+
+bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate);
+
+// helpers
+bool x86_is_protected(struct CPUState *cpu);
+bool x86_is_real(struct CPUState *cpu);
+bool x86_is_v8086(struct CPUState *cpu);
+bool x86_is_long_mode(struct CPUState *cpu);
+bool x86_is_long64_mode(struct CPUState *cpu);
+bool x86_is_paging_mode(struct CPUState *cpu);
+bool x86_is_pae_enabled(struct CPUState *cpu);
+
+addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg);
+addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg);
+addr_t linear_rip(struct CPUState *cpu, addr_t rip);
+
+static inline uint64_t rdtscp(void)
+{
+ uint64_t tsc;
+ __asm__ __volatile__("rdtscp; " // serializing read of tsc
+ "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up
+ "or %%rdx,%%rax" // and or onto rax
+ : "=a"(tsc) // output to tsc variable
+ :
+ : "%rcx", "%rdx"); // rcx and rdx are clobbered
+
+ return tsc;
+}
+
diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf-utils/x86_cpuid.c
new file mode 100644
index 0000000000..e496cf001c
--- /dev/null
+++ b/target/i386/hvf-utils/x86_cpuid.c
@@ -0,0 +1,270 @@
+/*
+ * i386 CPUID helper functions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ * Copyright (c) 2017 Google Inc.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * cpuid
+ */
+
+#include "qemu/osdep.h"
+#include "x86_cpuid.h"
+#include "x86.h"
+#include "vmx.h"
+
+#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
+ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
+ CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
+ CPUID_PAE | CPUID_SEP | CPUID_APIC)
+
+struct x86_cpuid builtin_cpus[] = {
+ {
+ .name = "vmx32",
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .level = 4,
+ .family = 6,
+ .model = 3,
+ .stepping = 3,
+ .features = PPRO_FEATURES,
+ .ext_features = /*CPUID_EXT_SSE3 |*/ CPUID_EXT_POPCNT, CPUID_MTRR | CPUID_CLFLUSH,
+ CPUID_PSE36,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = 0,//CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000004,
+ .model_id = "vmx32",
+ },
+ {
+ .name = "core2duo",
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .level = 10,
+ .family = 6,
+ .model = 15,
+ .stepping = 11,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
+ CPUID_HT | CPUID_TM | CPUID_PBE,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_DTES64 | CPUID_EXT_DSCPL |
+ CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM | CPUID_EXT_HYPERVISOR,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000008,
+ .model_id = "Intel(R) Core(TM)2 Duo GETCPU T7700 @ 2.40GHz",
+ },
+ {
+ .name = "vmX",
+ .vendor1 = CPUID_VENDOR_INTEL_1,
+ .vendor2 = CPUID_VENDOR_INTEL_2,
+ .vendor3 = CPUID_VENDOR_INTEL_3,
+ .level = 0xd,
+ .family = 6,
+ .model = 15,
+ .stepping = 11,
+ .features = PPRO_FEATURES |
+ CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
+ CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
+ CPUID_HT | CPUID_TM | CPUID_PBE,
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_SSSE3 |
+ CPUID_EXT_DTES64 | CPUID_EXT_DSCPL |
+ CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM | CPUID_EXT_HYPERVISOR,
+ .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
+ .ext3_features = CPUID_EXT3_LAHF_LM,
+ .xlevel = 0x80000008,
+ .model_id = "Common vmX processor",
+ },
+};
+
+static struct x86_cpuid *_cpuid = NULL;
+
+void init_cpuid(struct CPUState* cpu)
+{
+ _cpuid = &builtin_cpus[2]; // core2duo
+}
+
+void get_cpuid_func(struct CPUState* cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
+{
+ uint32_t h_rax, h_rbx, h_rcx, h_rdx;
+ host_cpuid(func, cnt, &h_rax, &h_rbx, &h_rcx, &h_rdx);
+ uint32_t apic_id = X86_CPU(cpu)->apic_id;
+
+
+ *eax = *ebx = *ecx = *edx = 0;
+ switch(func) {
+ case 0:
+ *eax = _cpuid->level;
+ *ebx = _cpuid->vendor1;
+ *edx = _cpuid->vendor2;
+ *ecx = _cpuid->vendor3;
+ break;
+ case 1:
+ *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
+ *ebx = (apic_id << 24) | (h_rbx & 0x00ffffff);
+ *ecx = h_rcx;
+ *edx = h_rdx;
+
+ if (cpu->nr_cores * cpu->nr_threads > 1) {
+ *ebx |= (cpu->nr_cores * cpu->nr_threads) << 16;
+ *edx |= 1 << 28; /* Enable Hyper-Threading */
+ }
+
+ *ecx = *ecx & ~(CPUID_EXT_OSXSAVE | CPUID_EXT_MONITOR | CPUID_EXT_X2APIC |
+ CPUID_EXT_VMX | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_TM2 | CPUID_EXT_PCID |
+ CPUID_EXT_EST | CPUID_EXT_SSE42 | CPUID_EXT_SSE41);
+ *ecx |= CPUID_EXT_HYPERVISOR;
+ break;
+ case 2:
+ /* cache info: needed for Pentium Pro compatibility */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 4:
+ /* cache info: needed for Core compatibility */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 5:
+ /* mwait info: needed for Core compatibility */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 6:
+ /* Thermal and Power Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 7:
+ *eax = h_rax;
+ *ebx = h_rbx & ~(CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF | CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INVPCID);
+ *ecx = h_rcx & ~(CPUID_7_0_ECX_AVX512BMI);
+ *edx = h_rdx;
+ break;
+ case 9:
+ /* Direct Cache Access Information Leaf */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0xA:
+ /* Architectural Performance Monitoring Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0xB:
+ /* CPU Topology Leaf */
+ *eax = 0;
+ *ebx = 0; /* Means that we don't support this leaf */
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0xD:
+ *eax = h_rax;
+ if (!cnt)
+ *eax &= (XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK);
+ if (1 == cnt)
+ *eax &= (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC);
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000000:
+ *eax = _cpuid->xlevel;
+ *ebx = _cpuid->vendor1;
+ *edx = _cpuid->vendor2;
+ *ecx = _cpuid->vendor3;
+ break;
+ case 0x80000001:
+ *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
+ *ebx = 0;
+ *ecx = _cpuid->ext3_features & h_rcx;
+ *edx = _cpuid->ext2_features & h_rdx;
+ break;
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000005:
+ /* cache info (L1 cache) */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000006:
+ /* cache info (L2 cache) */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000007:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0; /* Note - We disable invariant TSC (bit 8) in purpose */
+ break;
+ case 0x80000008:
+ /* virtual & phys address size in low 2 bytes. */
+ *eax = h_rax;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0x8000000A:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0x80000019:
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = 0;
+ *edx = 0;
+ case 0xC0000000:
+ *eax = _cpuid->xlevel2;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ default:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ }
+}
diff --git a/target/i386/hvf-utils/x86_cpuid.h b/target/i386/hvf-utils/x86_cpuid.h
new file mode 100644
index 0000000000..02f2f115b0
--- /dev/null
+++ b/target/i386/hvf-utils/x86_cpuid.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __CPUID_H__
+#define __CPUID_H__
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <stdarg.h>
+#include "qemu-common.h"
+#include "x86_flags.h"
+
+struct x86_cpuid {
+ const char *name;
+ uint32_t level;
+ uint32_t vendor1, vendor2, vendor3;
+ int family;
+ int model;
+ int stepping;
+ int tsc_khz;
+ uint32_t features, ext_features, ext2_features, ext3_features;
+ uint32_t kvm_features, svm_features;
+ uint32_t xlevel;
+ char model_id[48];
+ int vendor_override;
+ uint32_t flags;
+ uint32_t xlevel2;
+ uint32_t cpuid_7_0_ebx_features;
+};
+
+struct CPUState;
+
+void init_cpuid(struct CPUState* cpu);
+void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
+
+#endif /* __CPUID_H__ */
+
diff --git a/target/i386/hvf-utils/x86_decode.c b/target/i386/hvf-utils/x86_decode.c
new file mode 100644
index 0000000000..b4d8e22449
--- /dev/null
+++ b/target/i386/hvf-utils/x86_decode.c
@@ -0,0 +1,1659 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+
+#include "x86_decode.h"
+#include "string.h"
+#include "vmx.h"
+#include "x86_gen.h"
+#include "x86_mmu.h"
+#include "x86_descr.h"
+
+#define OPCODE_ESCAPE 0xf
+
+static void decode_invalid(CPUState *cpu, struct x86_decode *decode)
+{
+ printf("%llx: failed to decode instruction ", cpu->hvf_x86->fetch_rip - decode->len);
+ for (int i = 0; i < decode->opcode_len; i++)
+ printf("%x ", decode->opcode[i]);
+ printf("\n");
+ VM_PANIC("decoder failed\n");
+}
+
+uint64_t sign(uint64_t val, int size)
+{
+ switch (size) {
+ case 1:
+ val = (int8_t)val;
+ break;
+ case 2:
+ val = (int16_t)val;
+ break;
+ case 4:
+ val = (int32_t)val;
+ break;
+ case 8:
+ val = (int64_t)val;
+ break;
+ default:
+ VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
+ break;
+ }
+ return val;
+}
+
+static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode, int size)
+{
+ addr_t val = 0;
+
+ switch (size) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
+ break;
+ }
+ addr_t va = linear_rip(cpu, RIP(cpu)) + decode->len;
+ vmx_read_mem(cpu, &val, va, size);
+ decode->len += size;
+
+ return val;
+}
+
+static inline uint8_t decode_byte(CPUState *cpu, struct x86_decode *decode)
+{
+ return (uint8_t)decode_bytes(cpu, decode, 1);
+}
+
+static inline uint16_t decode_word(CPUState *cpu, struct x86_decode *decode)
+{
+ return (uint16_t)decode_bytes(cpu, decode, 2);
+}
+
+static inline uint32_t decode_dword(CPUState *cpu, struct x86_decode *decode)
+{
+ return (uint32_t)decode_bytes(cpu, decode, 4);
+}
+
+static inline uint64_t decode_qword(CPUState *cpu, struct x86_decode *decode)
+{
+ return decode_bytes(cpu, decode, 8);
+}
+
+static void decode_modrm_rm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_RM;
+}
+
+static void decode_modrm_reg(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_REG;
+ op->reg = decode->modrm.reg;
+ op->ptr = get_reg_ref(cpu, op->reg, decode->rex.r, decode->operand_size);
+}
+
+static void decode_rax(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_REG;
+ op->reg = REG_RAX;
+ op->ptr = get_reg_ref(cpu, op->reg, 0, decode->operand_size);
+}
+
+static inline void decode_immediate(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *var, int size)
+{
+ var->type = X86_VAR_IMMEDIATE;
+ var->size = size;
+ switch (size) {
+ case 1:
+ var->val = decode_byte(cpu, decode);
+ break;
+ case 2:
+ var->val = decode_word(cpu, decode);
+ break;
+ case 4:
+ var->val = decode_dword(cpu, decode);
+ break;
+ case 8:
+ var->val = decode_qword(cpu, decode);
+ break;
+ default:
+ VM_PANIC_EX("bad size %d\n", size);
+ }
+}
+
+static void decode_imm8(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ decode_immediate(cpu, decode, op, 1);
+ op->type = X86_VAR_IMMEDIATE;
+}
+
+static void decode_imm8_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ decode_immediate(cpu, decode, op, 1);
+ op->val = sign(op->val, 1);
+ op->type = X86_VAR_IMMEDIATE;
+}
+
+static void decode_imm16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ decode_immediate(cpu, decode, op, 2);
+ op->type = X86_VAR_IMMEDIATE;
+}
+
+
+static void decode_imm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ if (8 == decode->operand_size) {
+ decode_immediate(cpu, decode, op, 4);
+ op->val = sign(op->val, decode->operand_size);
+ } else {
+ decode_immediate(cpu, decode, op, decode->operand_size);
+ }
+ op->type = X86_VAR_IMMEDIATE;
+}
+
+static void decode_imm_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ decode_immediate(cpu, decode, op, decode->operand_size);
+ op->val = sign(op->val, decode->operand_size);
+ op->type = X86_VAR_IMMEDIATE;
+}
+
+static void decode_imm_1(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_IMMEDIATE;
+ op->val = 1;
+}
+
+static void decode_imm_0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_IMMEDIATE;
+ op->val = 0;
+}
+
+
+static void decode_pushseg(CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
+
+ decode->op[0].type = X86_VAR_REG;
+ switch (op) {
+ case 0xe:
+ decode->op[0].reg = REG_SEG_CS;
+ break;
+ case 0x16:
+ decode->op[0].reg = REG_SEG_SS;
+ break;
+ case 0x1e:
+ decode->op[0].reg = REG_SEG_DS;
+ break;
+ case 0x06:
+ decode->op[0].reg = REG_SEG_ES;
+ break;
+ case 0xa0:
+ decode->op[0].reg = REG_SEG_FS;
+ break;
+ case 0xa8:
+ decode->op[0].reg = REG_SEG_GS;
+ break;
+ }
+}
+
+static void decode_popseg(CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
+
+ decode->op[0].type = X86_VAR_REG;
+ switch (op) {
+ case 0xf:
+ decode->op[0].reg = REG_SEG_CS;
+ break;
+ case 0x17:
+ decode->op[0].reg = REG_SEG_SS;
+ break;
+ case 0x1f:
+ decode->op[0].reg = REG_SEG_DS;
+ break;
+ case 0x07:
+ decode->op[0].reg = REG_SEG_ES;
+ break;
+ case 0xa1:
+ decode->op[0].reg = REG_SEG_FS;
+ break;
+ case 0xa9:
+ decode->op[0].reg = REG_SEG_GS;
+ break;
+ }
+}
+
+static void decode_incgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0x40;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+}
+
+static void decode_decgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0x48;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+}
+
+static void decode_incgroup2(CPUState *cpu, struct x86_decode *decode)
+{
+ if (!decode->modrm.reg)
+ decode->cmd = X86_DECODE_CMD_INC;
+ else if (1 == decode->modrm.reg)
+ decode->cmd = X86_DECODE_CMD_DEC;
+}
+
+static void decode_pushgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0x50;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+}
+
+static void decode_popgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0x58;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+}
+
+static void decode_jxx(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->displacement = decode_bytes(cpu, decode, decode->operand_size);
+ decode->displacement_size = decode->operand_size;
+}
+
+static void decode_farjmp(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_IMMEDIATE;
+ decode->op[0].val = decode_bytes(cpu, decode, decode->operand_size);
+ decode->displacement = decode_word(cpu, decode);
+}
+
+static void decode_addgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_ADD,
+ X86_DECODE_CMD_OR,
+ X86_DECODE_CMD_ADC,
+ X86_DECODE_CMD_SBB,
+ X86_DECODE_CMD_AND,
+ X86_DECODE_CMD_SUB,
+ X86_DECODE_CMD_XOR,
+ X86_DECODE_CMD_CMP
+ };
+ decode->cmd = group[decode->modrm.reg];
+}
+
+static void decode_rotgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_ROL,
+ X86_DECODE_CMD_ROR,
+ X86_DECODE_CMD_RCL,
+ X86_DECODE_CMD_RCR,
+ X86_DECODE_CMD_SHL,
+ X86_DECODE_CMD_SHR,
+ X86_DECODE_CMD_SHL,
+ X86_DECODE_CMD_SAR
+ };
+ decode->cmd = group[decode->modrm.reg];
+}
+
+static void decode_f7group(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_TST,
+ X86_DECODE_CMD_TST,
+ X86_DECODE_CMD_NOT,
+ X86_DECODE_CMD_NEG,
+ X86_DECODE_CMD_MUL,
+ X86_DECODE_CMD_IMUL_1,
+ X86_DECODE_CMD_DIV,
+ X86_DECODE_CMD_IDIV
+ };
+ decode->cmd = group[decode->modrm.reg];
+ decode_modrm_rm(cpu, decode, &decode->op[0]);
+
+ switch (decode->modrm.reg) {
+ case 0:
+ case 1:
+ decode_imm(cpu, decode, &decode->op[1]);
+ break;
+ case 2:
+ break;
+ case 3:
+ decode->op[1].type = X86_VAR_IMMEDIATE;
+ decode->op[1].val = 0;
+ break;
+ default:
+ break;
+ }
+}
+
+static void decode_xchgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0x90;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+}
+
+static void decode_movgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0xb8;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
+}
+
+static void fetch_moffs(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_OFFSET;
+ op->ptr = decode_bytes(cpu, decode, decode->addressing_size);
+}
+
+static void decode_movgroup8(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[0] - 0xb0;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
+}
+
+static void decode_rcx(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X86_VAR_REG;
+ op->reg = REG_RCX;
+ op->ptr = get_reg_ref(cpu, op->reg, decode->rex.b, decode->operand_size);
+}
+
+struct decode_tbl {
+ uint8_t opcode;
+ enum x86_decode_cmd cmd;
+ uint8_t operand_size;
+ bool is_modrm;
+ void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
+ void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
+ void (*decode_op3)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op3);
+ void (*decode_op4)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op4);
+ void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
+ addr_t flags_mask;
+};
+
+struct decode_x87_tbl {
+ uint8_t opcode;
+ uint8_t modrm_reg;
+ uint8_t modrm_mod;
+ enum x86_decode_cmd cmd;
+ uint8_t operand_size;
+ bool rev;
+ bool pop;
+ void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
+ void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
+ void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
+ addr_t flags_mask;
+};
+
+struct decode_tbl invl_inst = {0x0, 0, 0, false, NULL, NULL, NULL, NULL, decode_invalid};
+
+struct decode_tbl _decode_tbl1[255];
+struct decode_tbl _decode_tbl2[255];
+struct decode_x87_tbl _decode_tbl3[255];
+
+static void decode_x87_ins(CPUState *cpu, struct x86_decode *decode)
+{
+ struct decode_x87_tbl *decoder;
+
+ decode->is_fpu = true;
+ int mode = decode->modrm.mod == 3 ? 1 : 0;
+ int index = ((decode->opcode[0] & 0xf) << 4) | (mode << 3) | decode->modrm.reg;
+
+ decoder = &_decode_tbl3[index];
+
+ decode->cmd = decoder->cmd;
+ if (decoder->operand_size)
+ decode->operand_size = decoder->operand_size;
+ decode->flags_mask = decoder->flags_mask;
+ decode->fpop_stack = decoder->pop;
+ decode->frev = decoder->rev;
+
+ if (decoder->decode_op1)
+ decoder->decode_op1(cpu, decode, &decode->op[0]);
+ if (decoder->decode_op2)
+ decoder->decode_op2(cpu, decode, &decode->op[1]);
+ if (decoder->decode_postfix)
+ decoder->decode_postfix(cpu, decode);
+
+ VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n", decode->opcode[0], decode->modrm.modrm, decoder->modrm_reg, decoder->modrm_mod);
+}
+
+static void decode_ffgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_INC,
+ X86_DECODE_CMD_DEC,
+ X86_DECODE_CMD_CALL_NEAR_ABS_INDIRECT,
+ X86_DECODE_CMD_CALL_FAR_ABS_INDIRECT,
+ X86_DECODE_CMD_JMP_NEAR_ABS_INDIRECT,
+ X86_DECODE_CMD_JMP_FAR_ABS_INDIRECT,
+ X86_DECODE_CMD_PUSH,
+ X86_DECODE_CMD_INVL,
+ X86_DECODE_CMD_INVL
+ };
+ decode->cmd = group[decode->modrm.reg];
+ if (decode->modrm.reg > 2)
+ decode->flags_mask = 0;
+}
+
+static void decode_sldtgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_SLDT,
+ X86_DECODE_CMD_STR,
+ X86_DECODE_CMD_LLDT,
+ X86_DECODE_CMD_LTR,
+ X86_DECODE_CMD_VERR,
+ X86_DECODE_CMD_VERW,
+ X86_DECODE_CMD_INVL,
+ X86_DECODE_CMD_INVL
+ };
+ decode->cmd = group[decode->modrm.reg];
+ printf("%llx: decode_sldtgroup: %d\n", cpu->hvf_x86->fetch_rip, decode->modrm.reg);
+}
+
+static void decode_lidtgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_SGDT,
+ X86_DECODE_CMD_SIDT,
+ X86_DECODE_CMD_LGDT,
+ X86_DECODE_CMD_LIDT,
+ X86_DECODE_CMD_SMSW,
+ X86_DECODE_CMD_LMSW,
+ X86_DECODE_CMD_LMSW,
+ X86_DECODE_CMD_INVLPG
+ };
+ decode->cmd = group[decode->modrm.reg];
+ if (0xf9 == decode->modrm.modrm) {
+ decode->opcode[decode->len++] = decode->modrm.modrm;
+ decode->cmd = X86_DECODE_CMD_RDTSCP;
+ }
+}
+
+static void decode_btgroup(CPUState *cpu, struct x86_decode *decode)
+{
+ enum x86_decode_cmd group[] = {
+ X86_DECODE_CMD_INVL,
+ X86_DECODE_CMD_INVL,
+ X86_DECODE_CMD_INVL,
+ X86_DECODE_CMD_INVL,
+ X86_DECODE_CMD_BT,
+ X86_DECODE_CMD_BTS,
+ X86_DECODE_CMD_BTR,
+ X86_DECODE_CMD_BTC
+ };
+ decode->cmd = group[decode->modrm.reg];
+}
+
+static void decode_x87_general(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->is_fpu = true;
+}
+
+static void decode_x87_modrm_floatp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X87_VAR_FLOATP;
+}
+
+static void decode_x87_modrm_intp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X87_VAR_INTP;
+}
+
+static void decode_x87_modrm_bytep(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X87_VAR_BYTEP;
+}
+
+static void decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X87_VAR_REG;
+ op->reg = 0;
+}
+
+static void decode_decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ op->type = X87_VAR_REG;
+ op->reg = decode->modrm.modrm & 7;
+}
+
+
+static void decode_aegroup(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->is_fpu = true;
+ switch (decode->modrm.reg) {
+ case 0:
+ decode->cmd = X86_DECODE_CMD_FXSAVE;
+ decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
+ break;
+ case 1:
+ decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
+ decode->cmd = X86_DECODE_CMD_FXRSTOR;
+ break;
+ case 5:
+ if (decode->modrm.modrm == 0xe8) {
+ decode->cmd = X86_DECODE_CMD_LFENCE;
+ } else {
+ VM_PANIC("xrstor");
+ }
+ break;
+ case 6:
+ VM_PANIC_ON(decode->modrm.modrm != 0xf0);
+ decode->cmd = X86_DECODE_CMD_MFENCE;
+ break;
+ case 7:
+ if (decode->modrm.modrm == 0xf8) {
+ decode->cmd = X86_DECODE_CMD_SFENCE;
+ } else {
+ decode->cmd = X86_DECODE_CMD_CLFLUSH;
+ }
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "0xae: reg %d\n", decode->modrm.reg);
+ break;
+ }
+}
+
+static void decode_bswap(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = decode->opcode[1] - 0xc8;
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+}
+
+static void decode_d9_4(CPUState *cpu, struct x86_decode *decode)
+{
+ switch(decode->modrm.modrm) {
+ case 0xe0:
+ // FCHS
+ decode->cmd = X86_DECODE_CMD_FCHS;
+ break;
+ case 0xe1:
+ decode->cmd = X86_DECODE_CMD_FABS;
+ break;
+ case 0xe4:
+ VM_PANIC_ON_EX(1, "FTST");
+ break;
+ case 0xe5:
+ // FXAM
+ decode->cmd = X86_DECODE_CMD_FXAM;
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "FLDENV");
+ break;
+ }
+}
+
+static void decode_db_4(CPUState *cpu, struct x86_decode *decode)
+{
+ switch (decode->modrm.modrm) {
+ case 0xe0:
+ VM_PANIC_ON_EX(1, "unhandled FNENI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
+ break;
+ case 0xe1:
+ VM_PANIC_ON_EX(1, "unhandled FNDISI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
+ break;
+ case 0xe2:
+ VM_PANIC_ON_EX(1, "unhandled FCLEX: %x %x\n", decode->opcode[0], decode->modrm.modrm);
+ break;
+ case 0xe3:
+ decode->cmd = X86_DECODE_CMD_FNINIT;
+ break;
+ case 0xe4:
+ decode->cmd = X86_DECODE_CMD_FNSETPM;
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "unhandled fpu opcode: %x %x\n", decode->opcode[0], decode->modrm.modrm);
+ break;
+ }
+}
+
+
+#define RFLAGS_MASK_NONE 0
+#define RFLAGS_MASK_OSZAPC (RFLAGS_OF | RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
+#define RFLAGS_MASK_LAHF (RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
+#define RFLAGS_MASK_CF (RFLAGS_CF)
+#define RFLAGS_MASK_IF (RFLAGS_IF)
+#define RFLAGS_MASK_TF (RFLAGS_TF)
+#define RFLAGS_MASK_DF (RFLAGS_DF)
+#define RFLAGS_MASK_ZF (RFLAGS_ZF)
+
+struct decode_tbl _1op_inst[] =
+{
+ {0x0, X86_DECODE_CMD_ADD, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1, X86_DECODE_CMD_ADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2, X86_DECODE_CMD_ADD, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3, X86_DECODE_CMD_ADD, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x4, X86_DECODE_CMD_ADD, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x5, X86_DECODE_CMD_ADD, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x6, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0x7, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+ {0x8, X86_DECODE_CMD_OR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x9, X86_DECODE_CMD_OR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa, X86_DECODE_CMD_OR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xb, X86_DECODE_CMD_OR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xc, X86_DECODE_CMD_OR, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xd, X86_DECODE_CMD_OR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xe, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0xf, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+
+ {0x10, X86_DECODE_CMD_ADC, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x11, X86_DECODE_CMD_ADC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x12, X86_DECODE_CMD_ADC, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x13, X86_DECODE_CMD_ADC, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x14, X86_DECODE_CMD_ADC, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x15, X86_DECODE_CMD_ADC, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x16, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0x17, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+
+ {0x18, X86_DECODE_CMD_SBB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x19, X86_DECODE_CMD_SBB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1a, X86_DECODE_CMD_SBB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1b, X86_DECODE_CMD_SBB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1c, X86_DECODE_CMD_SBB, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1d, X86_DECODE_CMD_SBB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x1e, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0x1f, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+
+ {0x20, X86_DECODE_CMD_AND, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x21, X86_DECODE_CMD_AND, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x22, X86_DECODE_CMD_AND, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x23, X86_DECODE_CMD_AND, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x24, X86_DECODE_CMD_AND, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x25, X86_DECODE_CMD_AND, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x28, X86_DECODE_CMD_SUB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x29, X86_DECODE_CMD_SUB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2a, X86_DECODE_CMD_SUB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2b, X86_DECODE_CMD_SUB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2c, X86_DECODE_CMD_SUB, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2d, X86_DECODE_CMD_SUB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2f, X86_DECODE_CMD_DAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x30, X86_DECODE_CMD_XOR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x31, X86_DECODE_CMD_XOR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x32, X86_DECODE_CMD_XOR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x33, X86_DECODE_CMD_XOR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x34, X86_DECODE_CMD_XOR, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x35, X86_DECODE_CMD_XOR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x38, X86_DECODE_CMD_CMP, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x39, X86_DECODE_CMD_CMP, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3a, X86_DECODE_CMD_CMP, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3b, X86_DECODE_CMD_CMP, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3c, X86_DECODE_CMD_CMP, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3d, X86_DECODE_CMD_CMP, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x3f, X86_DECODE_CMD_AAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x40, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x41, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x42, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x43, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x44, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x45, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x46, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x47, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+
+ {0x48, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x49, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4a, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4b, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4c, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4d, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4e, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4f, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+
+ {0x50, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x51, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x52, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x53, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x54, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x55, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x56, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x57, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+
+ {0x58, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x59, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5a, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5b, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5c, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5d, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5e, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5f, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+
+ {0x60, X86_DECODE_CMD_PUSHA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x61, X86_DECODE_CMD_POPA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x68, X86_DECODE_CMD_PUSH, 0, false, decode_imm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6a, X86_DECODE_CMD_PUSH, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x69, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x6b, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm8_signed, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x6c, X86_DECODE_CMD_INS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6d, X86_DECODE_CMD_INS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6e, X86_DECODE_CMD_OUTS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6f, X86_DECODE_CMD_OUTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x70, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x71, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x72, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x73, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x74, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x75, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x76, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x77, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x78, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x79, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7a, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7b, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7c, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7d, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7e, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7f, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+
+ {0x80, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x81, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x82, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x83, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8_signed, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x84, X86_DECODE_CMD_TST, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x85, X86_DECODE_CMD_TST, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x86, X86_DECODE_CMD_XCHG, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x87, X86_DECODE_CMD_XCHG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x88, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x89, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8a, X86_DECODE_CMD_MOV, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8b, X86_DECODE_CMD_MOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8c, X86_DECODE_CMD_MOV_FROM_SEG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8d, X86_DECODE_CMD_LEA, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8e, X86_DECODE_CMD_MOV_TO_SEG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8f, X86_DECODE_CMD_POP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x90, X86_DECODE_CMD_NOP, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x91, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x92, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x93, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x94, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x95, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x96, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x97, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+
+ {0x98, X86_DECODE_CMD_CBW, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x99, X86_DECODE_CMD_CWD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x9a, X86_DECODE_CMD_CALL_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
+
+ {0x9c, X86_DECODE_CMD_PUSHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ //{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_POPF},
+ {0x9e, X86_DECODE_CMD_SAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9f, X86_DECODE_CMD_LAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_LAHF},
+
+ {0xa0, X86_DECODE_CMD_MOV, 1, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa1, X86_DECODE_CMD_MOV, 0, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa2, X86_DECODE_CMD_MOV, 1, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa3, X86_DECODE_CMD_MOV, 0, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xa4, X86_DECODE_CMD_MOVS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa5, X86_DECODE_CMD_MOVS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa6, X86_DECODE_CMD_CMPS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa7, X86_DECODE_CMD_CMPS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xaa, X86_DECODE_CMD_STOS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xab, X86_DECODE_CMD_STOS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xac, X86_DECODE_CMD_LODS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xad, X86_DECODE_CMD_LODS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xae, X86_DECODE_CMD_SCAS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xaf, X86_DECODE_CMD_SCAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xa8, X86_DECODE_CMD_TST, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa9, X86_DECODE_CMD_TST, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xb0, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb1, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb2, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb3, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb4, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb5, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb6, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb7, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+
+ {0xb8, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xb9, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xba, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbb, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbc, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbd, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbe, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbf, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+
+ {0xc0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xc1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+
+ {0xc2, X86_DECODE_RET_NEAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc3, X86_DECODE_RET_NEAR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xc4, X86_DECODE_CMD_LES, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc5, X86_DECODE_CMD_LDS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xc6, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc7, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xc8, X86_DECODE_CMD_ENTER, 0, false, decode_imm16, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc9, X86_DECODE_CMD_LEAVE, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xca, X86_DECODE_RET_FAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xcb, X86_DECODE_RET_FAR, 0, false, decode_imm_0, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xcd, X86_DECODE_CMD_INT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ //{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IRET},
+
+ {0xd0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xd1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xd2, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xd3, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+
+ {0xd4, X86_DECODE_CMD_AAM, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xd5, X86_DECODE_CMD_AAD, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xd7, X86_DECODE_CMD_XLAT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xd8, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xd9, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xda, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdb, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdc, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdd, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xde, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdf, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+
+ {0xe0, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe1, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe2, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xe3, X86_DECODE_CMD_JCXZ, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+
+ {0xe4, X86_DECODE_CMD_IN, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe5, X86_DECODE_CMD_IN, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe6, X86_DECODE_CMD_OUT, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe7, X86_DECODE_CMD_OUT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe8, X86_DECODE_CMD_CALL_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe9, X86_DECODE_CMD_JMP_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xea, X86_DECODE_CMD_JMP_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
+ {0xeb, X86_DECODE_CMD_JMP_NEAR, 1, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xec, X86_DECODE_CMD_IN, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xed, X86_DECODE_CMD_IN, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xee, X86_DECODE_CMD_OUT, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xef, X86_DECODE_CMD_OUT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xf4, X86_DECODE_CMD_HLT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xf5, X86_DECODE_CMD_CMC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
+
+ {0xf6, X86_DECODE_CMD_INVL, 1, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
+ {0xf7, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
+
+ {0xf8, X86_DECODE_CMD_CLC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
+ {0xf9, X86_DECODE_CMD_STC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
+
+ {0xfa, X86_DECODE_CMD_CLI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
+ {0xfb, X86_DECODE_CMD_STI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
+ {0xfc, X86_DECODE_CMD_CLD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
+ {0xfd, X86_DECODE_CMD_STD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
+ {0xfe, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, NULL, NULL, NULL, decode_incgroup2, RFLAGS_MASK_OSZAPC},
+ {0xff, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_ffgroup, RFLAGS_MASK_OSZAPC},
+};
+
+struct decode_tbl _2op_inst[] =
+{
+ {0x0, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_sldtgroup, RFLAGS_MASK_NONE},
+ {0x1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_lidtgroup, RFLAGS_MASK_NONE},
+ {0x6, X86_DECODE_CMD_CLTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_TF},
+ {0x9, X86_DECODE_CMD_WBINVD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x18, X86_DECODE_CMD_PREFETCH, 0, true, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
+ {0x1f, X86_DECODE_CMD_NOP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x20, X86_DECODE_CMD_MOV_FROM_CR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x21, X86_DECODE_CMD_MOV_FROM_DR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x22, X86_DECODE_CMD_MOV_TO_CR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x23, X86_DECODE_CMD_MOV_TO_DR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x30, X86_DECODE_CMD_WRMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x31, X86_DECODE_CMD_RDTSC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x32, X86_DECODE_CMD_RDMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x40, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x41, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x42, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x43, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x44, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x45, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x46, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x47, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x48, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x49, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4a, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4b, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4c, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4d, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4e, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4f, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x77, X86_DECODE_CMD_EMMS, 0, false, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
+ {0x82, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x83, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x84, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x85, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x86, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x87, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x88, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x89, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8a, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8b, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8c, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8d, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8e, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8f, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x90, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x91, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x92, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x93, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x94, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x95, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x96, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x97, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x98, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x99, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9a, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9b, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9c, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9d, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9e, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9f, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xb0, X86_DECODE_CMD_CMPXCHG, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb1, X86_DECODE_CMD_CMPXCHG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xb6, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb7, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb8, X86_DECODE_CMD_POPCNT, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xbe, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xbf, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa0, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0xa1, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+ {0xa2, X86_DECODE_CMD_CPUID, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa3, X86_DECODE_CMD_BT, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
+ {0xa4, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa5, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa8, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0xa9, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+ {0xab, X86_DECODE_CMD_BTS, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
+ {0xac, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xad, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xae, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_aegroup, RFLAGS_MASK_NONE},
+
+ {0xaf, X86_DECODE_CMD_IMUL_2, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xb2, X86_DECODE_CMD_LSS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb3, X86_DECODE_CMD_BTR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xba, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_btgroup, RFLAGS_MASK_OSZAPC},
+ {0xbb, X86_DECODE_CMD_BTC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xbc, X86_DECODE_CMD_BSF, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xbd, X86_DECODE_CMD_BSR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xc1, X86_DECODE_CMD_XADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xc7, X86_DECODE_CMD_CMPXCHG8B, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_ZF},
+
+ {0xc8, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xc9, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xca, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcb, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcc, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcd, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xce, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcf, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+};
+
+struct decode_x87_tbl invl_inst_x87 = {0x0, 0, 0, 0, 0, false, false, NULL, NULL, decode_invalid, 0};
+
+struct decode_x87_tbl _x87_inst[] =
+{
+ {0xd8, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 4, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 5, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 7, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+
+ {0xd9, 0, 3, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 1, 0, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 2, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 3, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, decode_d9_4, RFLAGS_MASK_NONE},
+ {0xd9, 4, 0, X86_DECODE_CMD_INVL, 4, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 5, 3, X86_DECODE_CMD_FLDxx, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 5, 0, X86_DECODE_CMD_FLDCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ //
+ {0xd9, 7, 3, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 7, 0, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xda, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xda, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 6, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xda, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 7, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xda, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+
+ {0xdb, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, decode_db_4, RFLAGS_MASK_NONE},
+ {0xdb, 4, 0, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 5, 0, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 7, 0, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xdc, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 0, 0, X86_DECODE_CMD_FADD, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 1, 0, X86_DECODE_CMD_FMUL, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 4, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 4, 0, X86_DECODE_CMD_FSUB, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 5, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 5, 0, X86_DECODE_CMD_FSUB, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 6, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 6, 0, X86_DECODE_CMD_FDIV, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 7, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 7, 0, X86_DECODE_CMD_FDIV, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+
+ {0xdd, 0, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 2, 3, X86_DECODE_CMD_FST, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 2, 0, X86_DECODE_CMD_FST, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 3, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 4, 3, X86_DECODE_CMD_FUCOM, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 4, 0, X86_DECODE_CMD_FRSTOR, 8, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 7, 0, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 7, 3, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xde, 0, 3, X86_DECODE_CMD_FADD, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 0, 0, X86_DECODE_CMD_FADD, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 1, 3, X86_DECODE_CMD_FMUL, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 1, 0, X86_DECODE_CMD_FMUL, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 4, 3, X86_DECODE_CMD_FSUB, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 4, 0, X86_DECODE_CMD_FSUB, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 5, 3, X86_DECODE_CMD_FSUB, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 5, 0, X86_DECODE_CMD_FSUB, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 6, 3, X86_DECODE_CMD_FDIV, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 6, 0, X86_DECODE_CMD_FDIV, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 7, 3, X86_DECODE_CMD_FDIV, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 7, 0, X86_DECODE_CMD_FDIV, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+
+ {0xdf, 0, 0, X86_DECODE_CMD_FLD, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 2, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 2, 0, X86_DECODE_CMD_FST, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 3, 0, X86_DECODE_CMD_FST, 2, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 4, 3, X86_DECODE_CMD_FNSTSW, 2, false, true, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 5, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 7, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+};
+
+void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ addr_t ptr = 0;
+ x86_reg_segment seg = REG_SEG_DS;
+
+ if (!decode->modrm.mod && 6 == decode->modrm.rm) {
+ op->ptr = (uint16_t)decode->displacement;
+ goto calc_addr;
+ }
+
+ if (decode->displacement_size)
+ ptr = sign(decode->displacement, decode->displacement_size);
+
+ switch (decode->modrm.rm) {
+ case 0:
+ ptr += BX(cpu) + SI(cpu);
+ break;
+ case 1:
+ ptr += BX(cpu) + DI(cpu);
+ break;
+ case 2:
+ ptr += BP(cpu) + SI(cpu);
+ seg = REG_SEG_SS;
+ break;
+ case 3:
+ ptr += BP(cpu) + DI(cpu);
+ seg = REG_SEG_SS;
+ break;
+ case 4:
+ ptr += SI(cpu);
+ break;
+ case 5:
+ ptr += DI(cpu);
+ break;
+ case 6:
+ ptr += BP(cpu);
+ seg = REG_SEG_SS;
+ break;
+ case 7:
+ ptr += BX(cpu);
+ break;
+ }
+calc_addr:
+ if (X86_DECODE_CMD_LEA == decode->cmd)
+ op->ptr = (uint16_t)ptr;
+ else
+ op->ptr = decode_linear_addr(cpu, decode, (uint16_t)ptr, seg);
+}
+
+addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
+{
+ addr_t ptr = 0;
+ int which = 0;
+
+ if (is_extended)
+ reg |= REG_R8;
+
+
+ switch (size) {
+ case 1:
+ if (is_extended || reg < 4) {
+ which = 1;
+ ptr = (addr_t)&RL(cpu, reg);
+ } else {
+ which = 2;
+ ptr = (addr_t)&RH(cpu, reg - 4);
+ }
+ break;
+ default:
+ which = 3;
+ ptr = (addr_t)&RRX(cpu, reg);
+ break;
+ }
+ return ptr;
+}
+
+addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size)
+{
+ addr_t val = 0;
+ memcpy(&val, (void*)get_reg_ref(cpu, reg, is_extended, size), size);
+ return val;
+}
+
+static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode, x86_reg_segment *sel)
+{
+ addr_t base = 0;
+ addr_t scaled_index = 0;
+ int addr_size = decode->addressing_size;
+ int base_reg = decode->sib.base;
+ int index_reg = decode->sib.index;
+
+ *sel = REG_SEG_DS;
+
+ if (decode->modrm.mod || base_reg != REG_RBP) {
+ if (decode->rex.b)
+ base_reg |= REG_R8;
+ if (REG_RSP == base_reg || REG_RBP == base_reg)
+ *sel = REG_SEG_SS;
+ base = get_reg_val(cpu, decode->sib.base, decode->rex.b, addr_size);
+ }
+
+ if (decode->rex.x)
+ index_reg |= REG_R8;
+
+ if (index_reg != REG_RSP)
+ scaled_index = get_reg_val(cpu, index_reg, decode->rex.x, addr_size) << decode->sib.scale;
+ return base + scaled_index;
+}
+
+void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ x86_reg_segment seg = REG_SEG_DS;
+ addr_t ptr = 0;
+ int addr_size = decode->addressing_size;
+
+ if (decode->displacement_size)
+ ptr = sign(decode->displacement, decode->displacement_size);
+
+ if (4 == decode->modrm.rm) {
+ ptr += get_sib_val(cpu, decode, &seg);
+ }
+ else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
+ if (x86_is_long_mode(cpu))
+ ptr += RIP(cpu) + decode->len;
+ else
+ ptr = decode->displacement;
+ }
+ else {
+ if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm)
+ seg = REG_SEG_SS;
+ ptr += get_reg_val(cpu, decode->modrm.rm, decode->rex.b, addr_size);
+ }
+
+ if (X86_DECODE_CMD_LEA == decode->cmd)
+ op->ptr = (uint32_t)ptr;
+ else
+ op->ptr = decode_linear_addr(cpu, decode, (uint32_t)ptr, seg);
+}
+
+void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ x86_reg_segment seg = REG_SEG_DS;
+ int32_t offset = 0;
+ int mod = decode->modrm.mod;
+ int rm = decode->modrm.rm;
+ addr_t ptr;
+ int src = decode->modrm.rm;
+
+ if (decode->displacement_size)
+ offset = sign(decode->displacement, decode->displacement_size);
+
+ if (4 == rm)
+ ptr = get_sib_val(cpu, decode, &seg) + offset;
+ else if (0 == mod && 5 == rm)
+ ptr = RIP(cpu) + decode->len + (int32_t) offset;
+ else
+ ptr = get_reg_val(cpu, src, decode->rex.b, 8) + (int64_t) offset;
+
+ if (X86_DECODE_CMD_LEA == decode->cmd)
+ op->ptr = ptr;
+ else
+ op->ptr = decode_linear_addr(cpu, decode, ptr, seg);
+}
+
+
+void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+{
+ if (3 == decode->modrm.mod) {
+ op->reg = decode->modrm.reg;
+ op->type = X86_VAR_REG;
+ op->ptr = get_reg_ref(cpu, decode->modrm.rm, decode->rex.b, decode->operand_size);
+ return;
+ }
+
+ switch (decode->addressing_size) {
+ case 2:
+ calc_modrm_operand16(cpu, decode, op);
+ break;
+ case 4:
+ calc_modrm_operand32(cpu, decode, op);
+ break;
+ case 8:
+ calc_modrm_operand64(cpu, decode, op);
+ break;
+ default:
+ VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
+ break;
+ }
+}
+
+static void decode_prefix(CPUState *cpu, struct x86_decode *decode)
+{
+ while (1) {
+ uint8_t byte = decode_byte(cpu, decode);
+ switch (byte) {
+ case PREFIX_LOCK:
+ decode->lock = byte;
+ break;
+ case PREFIX_REPN:
+ case PREFIX_REP:
+ decode->rep = byte;
+ break;
+ case PREFIX_CS_SEG_OVEERIDE:
+ case PREFIX_SS_SEG_OVEERIDE:
+ case PREFIX_DS_SEG_OVEERIDE:
+ case PREFIX_ES_SEG_OVEERIDE:
+ case PREFIX_FS_SEG_OVEERIDE:
+ case PREFIX_GS_SEG_OVEERIDE:
+ decode->segment_override = byte;
+ break;
+ case PREFIX_OP_SIZE_OVERRIDE:
+ decode->op_size_override = byte;
+ break;
+ case PREFIX_ADDR_SIZE_OVERRIDE:
+ decode->addr_size_override = byte;
+ break;
+ case PREFIX_REX ... (PREFIX_REX + 0xf):
+ if (x86_is_long_mode(cpu)) {
+ decode->rex.rex = byte;
+ break;
+ }
+ // fall through when not in long mode
+ default:
+ decode->len--;
+ return;
+ }
+ }
+}
+
+void set_addressing_size(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->addressing_size = -1;
+ if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
+ if (decode->addr_size_override)
+ decode->addressing_size = 4;
+ else
+ decode->addressing_size = 2;
+ }
+ else if (!x86_is_long_mode(cpu)) {
+ // protected
+ struct vmx_segment cs;
+ vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
+ // check db
+ if ((cs.ar >> 14) & 1) {
+ if (decode->addr_size_override)
+ decode->addressing_size = 2;
+ else
+ decode->addressing_size = 4;
+ } else {
+ if (decode->addr_size_override)
+ decode->addressing_size = 4;
+ else
+ decode->addressing_size = 2;
+ }
+ } else {
+ // long
+ if (decode->addr_size_override)
+ decode->addressing_size = 4;
+ else
+ decode->addressing_size = 8;
+ }
+}
+
+void set_operand_size(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->operand_size = -1;
+ if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
+ if (decode->op_size_override)
+ decode->operand_size = 4;
+ else
+ decode->operand_size = 2;
+ }
+ else if (!x86_is_long_mode(cpu)) {
+ // protected
+ struct vmx_segment cs;
+ vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
+ // check db
+ if ((cs.ar >> 14) & 1) {
+ if (decode->op_size_override)
+ decode->operand_size = 2;
+ else
+ decode->operand_size = 4;
+ } else {
+ if (decode->op_size_override)
+ decode->operand_size = 4;
+ else
+ decode->operand_size = 2;
+ }
+ } else {
+ // long
+ if (decode->op_size_override)
+ decode->operand_size = 2;
+ else
+ decode->operand_size = 4;
+
+ if (decode->rex.w)
+ decode->operand_size = 8;
+ }
+}
+
+static void decode_sib(CPUState *cpu, struct x86_decode *decode)
+{
+ if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) && (decode->addressing_size != 2)) {
+ decode->sib.sib = decode_byte(cpu, decode);
+ decode->sib_present = true;
+ }
+}
+
+/* 16 bit modrm
+ * mod R/M
+ * 00 [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] [disp16] [BX]
+ * 01 [BX+SI+disp8] [BX+DI+disp8] [BP+SI+disp8] [BP+DI+disp8] [SI+disp8] [DI+disp8] [BP+disp8] [BX+disp8]
+ * 10 [BX+SI+disp16] [BX+DI+disp16] [BP+SI+disp16] [BP+DI+disp16] [SI+disp16] [DI+disp16] [BP+disp16] [BX+disp16]
+ * 11 - - - - - - - -
+ */
+int disp16_tbl[4][8] =
+ {{0, 0, 0, 0, 0, 0, 2, 0},
+ {1, 1, 1, 1, 1, 1, 1, 1},
+ {2, 2, 2, 2, 2, 2, 2, 2},
+ {0, 0, 0, 0, 0, 0, 0, 0}};
+
+/*
+ 32/64-bit modrm
+ Mod
+ 00 [r/m] [r/m] [r/m] [r/m] [SIB] [RIP/EIP1,2+disp32] [r/m] [r/m]
+ 01 [r/m+disp8] [r/m+disp8] [r/m+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8]
+ 10 [r/m+disp32] [r/m+disp32] [r/m+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32]
+ 11 - - - - - - - -
+ */
+int disp32_tbl[4][8] =
+ {{0, 0, 0, 0, -1, 4, 0, 0},
+ {1, 1, 1, 1, 1, 1, 1, 1},
+ {4, 4, 4, 4, 4, 4, 4, 4},
+ {0, 0, 0, 0, 0, 0, 0, 0}};
+
+static inline void decode_displacement(CPUState *cpu, struct x86_decode *decode)
+{
+ int addressing_size = decode->addressing_size;
+ int mod = decode->modrm.mod;
+ int rm = decode->modrm.rm;
+
+ decode->displacement_size = 0;
+ switch (addressing_size) {
+ case 2:
+ decode->displacement_size = disp16_tbl[mod][rm];
+ if (decode->displacement_size)
+ decode->displacement = (uint16_t)decode_bytes(cpu, decode, decode->displacement_size);
+ break;
+ case 4:
+ case 8:
+ if (-1 == disp32_tbl[mod][rm]) {
+ if (5 == decode->sib.base)
+ decode->displacement_size = 4;
+ }
+ else
+ decode->displacement_size = disp32_tbl[mod][rm];
+
+ if (decode->displacement_size)
+ decode->displacement = (uint32_t)decode_bytes(cpu, decode, decode->displacement_size);
+ break;
+ }
+}
+
+static inline void decode_modrm(CPUState *cpu, struct x86_decode *decode)
+{
+ decode->modrm.modrm = decode_byte(cpu, decode);
+ decode->is_modrm = true;
+
+ decode_sib(cpu, decode);
+ decode_displacement(cpu, decode);
+}
+
+static inline void decode_opcode_general(CPUState *cpu, struct x86_decode *decode, uint8_t opcode, struct decode_tbl *inst_decoder)
+{
+ decode->cmd = inst_decoder->cmd;
+ if (inst_decoder->operand_size)
+ decode->operand_size = inst_decoder->operand_size;
+ decode->flags_mask = inst_decoder->flags_mask;
+
+ if (inst_decoder->is_modrm)
+ decode_modrm(cpu, decode);
+ if (inst_decoder->decode_op1)
+ inst_decoder->decode_op1(cpu, decode, &decode->op[0]);
+ if (inst_decoder->decode_op2)
+ inst_decoder->decode_op2(cpu, decode, &decode->op[1]);
+ if (inst_decoder->decode_op3)
+ inst_decoder->decode_op3(cpu, decode, &decode->op[2]);
+ if (inst_decoder->decode_op4)
+ inst_decoder->decode_op4(cpu, decode, &decode->op[3]);
+ if (inst_decoder->decode_postfix)
+ inst_decoder->decode_postfix(cpu, decode);
+}
+
+static inline void decode_opcode_1(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
+{
+ struct decode_tbl *inst_decoder = &_decode_tbl1[opcode];
+ decode_opcode_general(cpu, decode, opcode, inst_decoder);
+}
+
+
+static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
+{
+ struct decode_tbl *inst_decoder = &_decode_tbl2[opcode];
+ decode_opcode_general(cpu, decode, opcode, inst_decoder);
+}
+
+static void decode_opcodes(CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t opcode;
+
+ opcode = decode_byte(cpu, decode);
+ decode->opcode[decode->opcode_len++] = opcode;
+ if (opcode != OPCODE_ESCAPE) {
+ decode_opcode_1(cpu, decode, opcode);
+ } else {
+ opcode = decode_byte(cpu, decode);
+ decode->opcode[decode->opcode_len++] = opcode;
+ decode_opcode_2(cpu, decode, opcode);
+ }
+}
+
+uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode)
+{
+ ZERO_INIT(*decode);
+
+ decode_prefix(cpu, decode);
+ set_addressing_size(cpu, decode);
+ set_operand_size(cpu, decode);
+
+ decode_opcodes(cpu, decode);
+
+ return decode->len;
+}
+
+void init_decoder(CPUState *cpu)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
+ memcpy(_decode_tbl1, &invl_inst, sizeof(invl_inst));
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
+ memcpy(_decode_tbl2, &invl_inst, sizeof(invl_inst));
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl3); i++)
+ memcpy(_decode_tbl3, &invl_inst, sizeof(invl_inst_x87));
+
+ for (i = 0; i < ARRAY_SIZE(_1op_inst); i++) {
+ _decode_tbl1[_1op_inst[i].opcode] = _1op_inst[i];
+ }
+ for (i = 0; i < ARRAY_SIZE(_2op_inst); i++) {
+ _decode_tbl2[_2op_inst[i].opcode] = _2op_inst[i];
+ }
+ for (i = 0; i < ARRAY_SIZE(_x87_inst); i++) {
+ int index = ((_x87_inst[i].opcode & 0xf) << 4) | ((_x87_inst[i].modrm_mod & 1) << 3) | _x87_inst[i].modrm_reg;
+ _decode_tbl3[index] = _x87_inst[i];
+ }
+}
+
+
+const char *decode_cmd_to_string(enum x86_decode_cmd cmd)
+{
+ static const char *cmds[] = {"INVL", "PUSH", "PUSH_SEG", "POP", "POP_SEG", "MOV", "MOVSX", "MOVZX", "CALL_NEAR",
+ "CALL_NEAR_ABS_INDIRECT", "CALL_FAR_ABS_INDIRECT", "CMD_CALL_FAR", "RET_NEAR", "RET_FAR", "ADD", "OR",
+ "ADC", "SBB", "AND", "SUB", "XOR", "CMP", "INC", "DEC", "TST", "NOT", "NEG", "JMP_NEAR", "JMP_NEAR_ABS_INDIRECT",
+ "JMP_FAR", "JMP_FAR_ABS_INDIRECT", "LEA", "JXX",
+ "JCXZ", "SETXX", "MOV_TO_SEG", "MOV_FROM_SEG", "CLI", "STI", "CLD", "STD", "STC",
+ "CLC", "OUT", "IN", "INS", "OUTS", "LIDT", "SIDT", "LGDT", "SGDT", "SMSW", "LMSW", "RDTSCP", "INVLPG", "MOV_TO_CR",
+ "MOV_FROM_CR", "MOV_TO_DR", "MOV_FROM_DR", "PUSHF", "POPF", "CPUID", "ROL", "ROR", "RCL", "RCR", "SHL", "SAL",
+ "SHR","SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL", "IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS",
+ "LODS", "STOS", "BSWAP", "XCHG", "RDTSC", "RDMSR", "WRMSR", "ENTER", "LEAVE", "BT", "BTS", "BTC", "BTR", "BSF",
+ "BSR", "IRET", "INT", "POPA", "PUSHA", "CWD", "CBW", "DAS", "AAD", "AAM", "AAS", "LOOP", "SLDT", "STR", "LLDT",
+ "LTR", "VERR", "VERW", "SAHF", "LAHF", "WBINVD", "LDS", "LSS", "LES", "LGS", "LFS", "CMC", "XLAT", "NOP", "CMOV",
+ "CLTS", "XADD", "HLT", "CMPXCHG8B", "CMPXCHG", "POPCNT",
+ "FNINIT", "FLD", "FLDxx", "FNSTCW", "FNSTSW", "FNSETPM", "FSAVE", "FRSTOR", "FXSAVE", "FXRSTOR", "FDIV", "FMUL",
+ "FSUB", "FADD", "EMMS", "MFENCE", "SFENCE", "LFENCE", "PREFETCH", "FST", "FABS", "FUCOM", "FUCOMI", "FLDCW",
+ "FXCH", "FCHS", "FCMOV", "FRNDINT", "FXAM", "LAST"};
+ return cmds[cmd];
+}
+
+addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg)
+{
+ switch (decode->segment_override) {
+ case PREFIX_CS_SEG_OVEERIDE:
+ seg = REG_SEG_CS;
+ break;
+ case PREFIX_SS_SEG_OVEERIDE:
+ seg = REG_SEG_SS;
+ break;
+ case PREFIX_DS_SEG_OVEERIDE:
+ seg = REG_SEG_DS;
+ break;
+ case PREFIX_ES_SEG_OVEERIDE:
+ seg = REG_SEG_ES;
+ break;
+ case PREFIX_FS_SEG_OVEERIDE:
+ seg = REG_SEG_FS;
+ break;
+ case PREFIX_GS_SEG_OVEERIDE:
+ seg = REG_SEG_GS;
+ break;
+ default:
+ break;
+ }
+ return linear_addr_size(cpu, addr, decode->addressing_size, seg);
+}
diff --git a/target/i386/hvf-utils/x86_decode.h b/target/i386/hvf-utils/x86_decode.h
new file mode 100644
index 0000000000..3a22d7d1a5
--- /dev/null
+++ b/target/i386/hvf-utils/x86_decode.h
@@ -0,0 +1,314 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <stdarg.h>
+#include "qemu-common.h"
+#include "x86.h"
+
+typedef enum x86_prefix {
+ // group 1
+ PREFIX_LOCK = 0xf0,
+ PREFIX_REPN = 0xf2,
+ PREFIX_REP = 0xf3,
+ // group 2
+ PREFIX_CS_SEG_OVEERIDE = 0x2e,
+ PREFIX_SS_SEG_OVEERIDE = 0x36,
+ PREFIX_DS_SEG_OVEERIDE = 0x3e,
+ PREFIX_ES_SEG_OVEERIDE = 0x26,
+ PREFIX_FS_SEG_OVEERIDE = 0x64,
+ PREFIX_GS_SEG_OVEERIDE = 0x65,
+ // group 3
+ PREFIX_OP_SIZE_OVERRIDE = 0x66,
+ // group 4
+ PREFIX_ADDR_SIZE_OVERRIDE = 0x67,
+
+ PREFIX_REX = 0x40,
+} x86_prefix;
+
+enum x86_decode_cmd {
+ X86_DECODE_CMD_INVL = 0,
+
+ X86_DECODE_CMD_PUSH,
+ X86_DECODE_CMD_PUSH_SEG,
+ X86_DECODE_CMD_POP,
+ X86_DECODE_CMD_POP_SEG,
+ X86_DECODE_CMD_MOV,
+ X86_DECODE_CMD_MOVSX,
+ X86_DECODE_CMD_MOVZX,
+ X86_DECODE_CMD_CALL_NEAR,
+ X86_DECODE_CMD_CALL_NEAR_ABS_INDIRECT,
+ X86_DECODE_CMD_CALL_FAR_ABS_INDIRECT,
+ X86_DECODE_CMD_CALL_FAR,
+ X86_DECODE_RET_NEAR,
+ X86_DECODE_RET_FAR,
+ X86_DECODE_CMD_ADD,
+ X86_DECODE_CMD_OR,
+ X86_DECODE_CMD_ADC,
+ X86_DECODE_CMD_SBB,
+ X86_DECODE_CMD_AND,
+ X86_DECODE_CMD_SUB,
+ X86_DECODE_CMD_XOR,
+ X86_DECODE_CMD_CMP,
+ X86_DECODE_CMD_INC,
+ X86_DECODE_CMD_DEC,
+ X86_DECODE_CMD_TST,
+ X86_DECODE_CMD_NOT,
+ X86_DECODE_CMD_NEG,
+ X86_DECODE_CMD_JMP_NEAR,
+ X86_DECODE_CMD_JMP_NEAR_ABS_INDIRECT,
+ X86_DECODE_CMD_JMP_FAR,
+ X86_DECODE_CMD_JMP_FAR_ABS_INDIRECT,
+ X86_DECODE_CMD_LEA,
+ X86_DECODE_CMD_JXX,
+ X86_DECODE_CMD_JCXZ,
+ X86_DECODE_CMD_SETXX,
+ X86_DECODE_CMD_MOV_TO_SEG,
+ X86_DECODE_CMD_MOV_FROM_SEG,
+ X86_DECODE_CMD_CLI,
+ X86_DECODE_CMD_STI,
+ X86_DECODE_CMD_CLD,
+ X86_DECODE_CMD_STD,
+ X86_DECODE_CMD_STC,
+ X86_DECODE_CMD_CLC,
+ X86_DECODE_CMD_OUT,
+ X86_DECODE_CMD_IN,
+ X86_DECODE_CMD_INS,
+ X86_DECODE_CMD_OUTS,
+ X86_DECODE_CMD_LIDT,
+ X86_DECODE_CMD_SIDT,
+ X86_DECODE_CMD_LGDT,
+ X86_DECODE_CMD_SGDT,
+ X86_DECODE_CMD_SMSW,
+ X86_DECODE_CMD_LMSW,
+ X86_DECODE_CMD_RDTSCP,
+ X86_DECODE_CMD_INVLPG,
+ X86_DECODE_CMD_MOV_TO_CR,
+ X86_DECODE_CMD_MOV_FROM_CR,
+ X86_DECODE_CMD_MOV_TO_DR,
+ X86_DECODE_CMD_MOV_FROM_DR,
+ X86_DECODE_CMD_PUSHF,
+ X86_DECODE_CMD_POPF,
+ X86_DECODE_CMD_CPUID,
+ X86_DECODE_CMD_ROL,
+ X86_DECODE_CMD_ROR,
+ X86_DECODE_CMD_RCL,
+ X86_DECODE_CMD_RCR,
+ X86_DECODE_CMD_SHL,
+ X86_DECODE_CMD_SAL,
+ X86_DECODE_CMD_SHR,
+ X86_DECODE_CMD_SHRD,
+ X86_DECODE_CMD_SHLD,
+ X86_DECODE_CMD_SAR,
+ X86_DECODE_CMD_DIV,
+ X86_DECODE_CMD_IDIV,
+ X86_DECODE_CMD_MUL,
+ X86_DECODE_CMD_IMUL_3,
+ X86_DECODE_CMD_IMUL_2,
+ X86_DECODE_CMD_IMUL_1,
+ X86_DECODE_CMD_MOVS,
+ X86_DECODE_CMD_CMPS,
+ X86_DECODE_CMD_SCAS,
+ X86_DECODE_CMD_LODS,
+ X86_DECODE_CMD_STOS,
+ X86_DECODE_CMD_BSWAP,
+ X86_DECODE_CMD_XCHG,
+ X86_DECODE_CMD_RDTSC,
+ X86_DECODE_CMD_RDMSR,
+ X86_DECODE_CMD_WRMSR,
+ X86_DECODE_CMD_ENTER,
+ X86_DECODE_CMD_LEAVE,
+ X86_DECODE_CMD_BT,
+ X86_DECODE_CMD_BTS,
+ X86_DECODE_CMD_BTC,
+ X86_DECODE_CMD_BTR,
+ X86_DECODE_CMD_BSF,
+ X86_DECODE_CMD_BSR,
+ X86_DECODE_CMD_IRET,
+ X86_DECODE_CMD_INT,
+ X86_DECODE_CMD_POPA,
+ X86_DECODE_CMD_PUSHA,
+ X86_DECODE_CMD_CWD,
+ X86_DECODE_CMD_CBW,
+ X86_DECODE_CMD_DAS,
+ X86_DECODE_CMD_AAD,
+ X86_DECODE_CMD_AAM,
+ X86_DECODE_CMD_AAS,
+ X86_DECODE_CMD_LOOP,
+ X86_DECODE_CMD_SLDT,
+ X86_DECODE_CMD_STR,
+ X86_DECODE_CMD_LLDT,
+ X86_DECODE_CMD_LTR,
+ X86_DECODE_CMD_VERR,
+ X86_DECODE_CMD_VERW,
+ X86_DECODE_CMD_SAHF,
+ X86_DECODE_CMD_LAHF,
+ X86_DECODE_CMD_WBINVD,
+ X86_DECODE_CMD_LDS,
+ X86_DECODE_CMD_LSS,
+ X86_DECODE_CMD_LES,
+ X86_DECODE_XMD_LGS,
+ X86_DECODE_CMD_LFS,
+ X86_DECODE_CMD_CMC,
+ X86_DECODE_CMD_XLAT,
+ X86_DECODE_CMD_NOP,
+ X86_DECODE_CMD_CMOV,
+ X86_DECODE_CMD_CLTS,
+ X86_DECODE_CMD_XADD,
+ X86_DECODE_CMD_HLT,
+ X86_DECODE_CMD_CMPXCHG8B,
+ X86_DECODE_CMD_CMPXCHG,
+ X86_DECODE_CMD_POPCNT,
+
+ X86_DECODE_CMD_FNINIT,
+ X86_DECODE_CMD_FLD,
+ X86_DECODE_CMD_FLDxx,
+ X86_DECODE_CMD_FNSTCW,
+ X86_DECODE_CMD_FNSTSW,
+ X86_DECODE_CMD_FNSETPM,
+ X86_DECODE_CMD_FSAVE,
+ X86_DECODE_CMD_FRSTOR,
+ X86_DECODE_CMD_FXSAVE,
+ X86_DECODE_CMD_FXRSTOR,
+ X86_DECODE_CMD_FDIV,
+ X86_DECODE_CMD_FMUL,
+ X86_DECODE_CMD_FSUB,
+ X86_DECODE_CMD_FADD,
+ X86_DECODE_CMD_EMMS,
+ X86_DECODE_CMD_MFENCE,
+ X86_DECODE_CMD_SFENCE,
+ X86_DECODE_CMD_LFENCE,
+ X86_DECODE_CMD_PREFETCH,
+ X86_DECODE_CMD_CLFLUSH,
+ X86_DECODE_CMD_FST,
+ X86_DECODE_CMD_FABS,
+ X86_DECODE_CMD_FUCOM,
+ X86_DECODE_CMD_FUCOMI,
+ X86_DECODE_CMD_FLDCW,
+ X86_DECODE_CMD_FXCH,
+ X86_DECODE_CMD_FCHS,
+ X86_DECODE_CMD_FCMOV,
+ X86_DECODE_CMD_FRNDINT,
+ X86_DECODE_CMD_FXAM,
+
+ X86_DECODE_CMD_LAST,
+};
+
+const char *decode_cmd_to_string(enum x86_decode_cmd cmd);
+
+typedef struct x86_modrm {
+ union {
+ uint8_t modrm;
+ struct {
+ uint8_t rm:3;
+ uint8_t reg:3;
+ uint8_t mod:2;
+ };
+ };
+} __attribute__ ((__packed__)) x86_modrm;
+
+typedef struct x86_sib {
+ union {
+ uint8_t sib;
+ struct {
+ uint8_t base:3;
+ uint8_t index:3;
+ uint8_t scale:2;
+ };
+ };
+} __attribute__ ((__packed__)) x86_sib;
+
+typedef struct x86_rex {
+ union {
+ uint8_t rex;
+ struct {
+ uint8_t b:1;
+ uint8_t x:1;
+ uint8_t r:1;
+ uint8_t w:1;
+ uint8_t unused:4;
+ };
+ };
+} __attribute__ ((__packed__)) x86_rex;
+
+typedef enum x86_var_type {
+ X86_VAR_IMMEDIATE,
+ X86_VAR_OFFSET,
+ X86_VAR_REG,
+ X86_VAR_RM,
+
+ // for floating point computations
+ X87_VAR_REG,
+ X87_VAR_FLOATP,
+ X87_VAR_INTP,
+ X87_VAR_BYTEP,
+} x86_var_type;
+
+typedef struct x86_decode_op {
+ enum x86_var_type type;
+ int size;
+
+ int reg;
+ addr_t val;
+
+ addr_t ptr;
+} x86_decode_op;
+
+typedef struct x86_decode {
+ int len;
+ uint8_t opcode[4];
+ uint8_t opcode_len;
+ enum x86_decode_cmd cmd;
+ int addressing_size;
+ int operand_size;
+ int lock;
+ int rep;
+ int op_size_override;
+ int addr_size_override;
+ int segment_override;
+ int control_change_inst;
+ bool fwait;
+ bool fpop_stack;
+ bool frev;
+
+ uint32_t displacement;
+ uint8_t displacement_size;
+ struct x86_rex rex;
+ bool is_modrm;
+ bool sib_present;
+ struct x86_sib sib;
+ struct x86_modrm modrm;
+ struct x86_decode_op op[4];
+ bool is_fpu;
+ addr_t flags_mask;
+
+} x86_decode;
+
+uint64_t sign(uint64_t val, int size);
+
+uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode);
+
+addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size);
+addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size);
+void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op);
+addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg);
+
+void init_decoder(CPUState* cpu);
diff --git a/target/i386/hvf-utils/x86_descr.c b/target/i386/hvf-utils/x86_descr.c
new file mode 100644
index 0000000000..c3b089aaa8
--- /dev/null
+++ b/target/i386/hvf-utils/x86_descr.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+
+#include "vmx.h"
+#include "x86_descr.h"
+
+#define VMX_SEGMENT_FIELD(seg) \
+ [REG_SEG_##seg] = { \
+ .selector = VMCS_GUEST_##seg##_SELECTOR, \
+ .base = VMCS_GUEST_##seg##_BASE, \
+ .limit = VMCS_GUEST_##seg##_LIMIT, \
+ .ar_bytes = VMCS_GUEST_##seg##_ACCESS_RIGHTS, \
+}
+
+static const struct vmx_segment_field {
+ int selector;
+ int base;
+ int limit;
+ int ar_bytes;
+} vmx_segment_fields[] = {
+ VMX_SEGMENT_FIELD(ES),
+ VMX_SEGMENT_FIELD(CS),
+ VMX_SEGMENT_FIELD(SS),
+ VMX_SEGMENT_FIELD(DS),
+ VMX_SEGMENT_FIELD(FS),
+ VMX_SEGMENT_FIELD(GS),
+ VMX_SEGMENT_FIELD(LDTR),
+ VMX_SEGMENT_FIELD(TR),
+};
+
+uint32_t vmx_read_segment_limit(CPUState *cpu, x86_reg_segment seg)
+{
+ return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit);
+}
+
+uint32_t vmx_read_segment_ar(CPUState *cpu, x86_reg_segment seg)
+{
+ return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes);
+}
+
+uint64_t vmx_read_segment_base(CPUState *cpu, x86_reg_segment seg)
+{
+ return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base);
+}
+
+x68_segment_selector vmx_read_segment_selector(CPUState *cpu, x86_reg_segment seg)
+{
+ x68_segment_selector sel;
+ sel.sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector);
+ return sel;
+}
+
+void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg)
+{
+ wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel);
+}
+
+void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg)
+{
+ desc->sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector);
+ desc->base = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base);
+ desc->limit = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit);
+ desc->ar = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes);
+}
+
+void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg)
+{
+ const struct vmx_segment_field *sf = &vmx_segment_fields[seg];
+
+ wvmcs(cpu->hvf_fd, sf->base, desc->base);
+ wvmcs(cpu->hvf_fd, sf->limit, desc->limit);
+ wvmcs(cpu->hvf_fd, sf->selector, desc->sel);
+ wvmcs(cpu->hvf_fd, sf->ar_bytes, desc->ar);
+}
+
+void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)
+{
+ vmx_desc->sel = selector.sel;
+ vmx_desc->base = x86_segment_base(desc);
+ vmx_desc->limit = x86_segment_limit(desc);
+
+ vmx_desc->ar = (selector.sel ? 0 : 1) << 16 |
+ desc->g << 15 |
+ desc->db << 14 |
+ desc->l << 13 |
+ desc->avl << 12 |
+ desc->p << 7 |
+ desc->dpl << 5 |
+ desc->s << 4 |
+ desc->type;
+}
+
+void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc)
+{
+ x86_set_segment_limit(desc, vmx_desc->limit);
+ x86_set_segment_base(desc, vmx_desc->base);
+
+ desc->type = vmx_desc->ar & 15;
+ desc->s = (vmx_desc->ar >> 4) & 1;
+ desc->dpl = (vmx_desc->ar >> 5) & 3;
+ desc->p = (vmx_desc->ar >> 7) & 1;
+ desc->avl = (vmx_desc->ar >> 12) & 1;
+ desc->l = (vmx_desc->ar >> 13) & 1;
+ desc->db = (vmx_desc->ar >> 14) & 1;
+ desc->g = (vmx_desc->ar >> 15) & 1;
+}
+
diff --git a/target/i386/hvf-utils/x86_descr.h b/target/i386/hvf-utils/x86_descr.h
new file mode 100644
index 0000000000..78fb1bc420
--- /dev/null
+++ b/target/i386/hvf-utils/x86_descr.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include "x86.h"
+
+typedef struct vmx_segment {
+ uint16_t sel;
+ uint64_t base;
+ uint64_t limit;
+ uint64_t ar;
+} vmx_segment;
+
+// deal with vmstate descriptors
+void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
+void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
+
+x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, x86_reg_segment seg);
+void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg);
+
+uint64_t vmx_read_segment_base(struct CPUState *cpu, x86_reg_segment seg);
+void vmx_write_segment_base(struct CPUState *cpu, x86_reg_segment seg, uint64_t base);
+
+void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc);
diff --git a/target/i386/hvf-utils/x86_emu.c b/target/i386/hvf-utils/x86_emu.c
new file mode 100644
index 0000000000..8b5efc76f0
--- /dev/null
+++ b/target/i386/hvf-utils/x86_emu.c
@@ -0,0 +1,1466 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2001-2012 The Bochs Project
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+/////////////////////////////////////////////////////////////////////////
+
+#include "qemu/osdep.h"
+
+#include "qemu-common.h"
+#include "x86_decode.h"
+#include "x86.h"
+#include "x86_emu.h"
+#include "x86_mmu.h"
+#include "vmcs.h"
+#include "vmx.h"
+
+static void print_debug(struct CPUState *cpu);
+void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count);
+
+#define EXEC_2OP_LOGIC_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
+{ \
+ fetch_operands(cpu, decode, 2, true, true, false); \
+ switch (decode->operand_size) { \
+ case 1: \
+ { \
+ uint8_t v1 = (uint8_t)decode->op[0].val; \
+ uint8_t v2 = (uint8_t)decode->op[1].val; \
+ uint8_t diff = v1 cmd v2; \
+ if (save_res) \
+ write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
+ FLAGS_FUNC##_8(diff); \
+ break; \
+ } \
+ case 2: \
+ { \
+ uint16_t v1 = (uint16_t)decode->op[0].val; \
+ uint16_t v2 = (uint16_t)decode->op[1].val; \
+ uint16_t diff = v1 cmd v2; \
+ if (save_res) \
+ write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
+ FLAGS_FUNC##_16(diff); \
+ break; \
+ } \
+ case 4: \
+ { \
+ uint32_t v1 = (uint32_t)decode->op[0].val; \
+ uint32_t v2 = (uint32_t)decode->op[1].val; \
+ uint32_t diff = v1 cmd v2; \
+ if (save_res) \
+ write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
+ FLAGS_FUNC##_32(diff); \
+ break; \
+ } \
+ default: \
+ VM_PANIC("bad size\n"); \
+ } \
+} \
+
+
+#define EXEC_2OP_ARITH_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
+{ \
+ fetch_operands(cpu, decode, 2, true, true, false); \
+ switch (decode->operand_size) { \
+ case 1: \
+ { \
+ uint8_t v1 = (uint8_t)decode->op[0].val; \
+ uint8_t v2 = (uint8_t)decode->op[1].val; \
+ uint8_t diff = v1 cmd v2; \
+ if (save_res) \
+ write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
+ FLAGS_FUNC##_8(v1, v2, diff); \
+ break; \
+ } \
+ case 2: \
+ { \
+ uint16_t v1 = (uint16_t)decode->op[0].val; \
+ uint16_t v2 = (uint16_t)decode->op[1].val; \
+ uint16_t diff = v1 cmd v2; \
+ if (save_res) \
+ write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
+ FLAGS_FUNC##_16(v1, v2, diff); \
+ break; \
+ } \
+ case 4: \
+ { \
+ uint32_t v1 = (uint32_t)decode->op[0].val; \
+ uint32_t v2 = (uint32_t)decode->op[1].val; \
+ uint32_t diff = v1 cmd v2; \
+ if (save_res) \
+ write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
+ FLAGS_FUNC##_32(v1, v2, diff); \
+ break; \
+ } \
+ default: \
+ VM_PANIC("bad size\n"); \
+ } \
+}
+
+addr_t read_reg(struct CPUState* cpu, int reg, int size)
+{
+ switch (size) {
+ case 1:
+ return cpu->hvf_x86->regs[reg].lx;
+ case 2:
+ return cpu->hvf_x86->regs[reg].rx;
+ case 4:
+ return cpu->hvf_x86->regs[reg].erx;
+ case 8:
+ return cpu->hvf_x86->regs[reg].rrx;
+ default:
+ VM_PANIC_ON("read_reg size");
+ }
+ return 0;
+}
+
+void write_reg(struct CPUState* cpu, int reg, addr_t val, int size)
+{
+ switch (size) {
+ case 1:
+ cpu->hvf_x86->regs[reg].lx = val;
+ break;
+ case 2:
+ cpu->hvf_x86->regs[reg].rx = val;
+ break;
+ case 4:
+ cpu->hvf_x86->regs[reg].rrx = (uint32_t)val;
+ break;
+ case 8:
+ cpu->hvf_x86->regs[reg].rrx = val;
+ break;
+ default:
+ VM_PANIC_ON("write_reg size");
+ }
+}
+
+addr_t read_val_from_reg(addr_t reg_ptr, int size)
+{
+ addr_t val;
+
+ switch (size) {
+ case 1:
+ val = *(uint8_t*)reg_ptr;
+ break;
+ case 2:
+ val = *(uint16_t*)reg_ptr;
+ break;
+ case 4:
+ val = *(uint32_t*)reg_ptr;
+ break;
+ case 8:
+ val = *(uint64_t*)reg_ptr;
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "read_val: Unknown size %d\n", size);
+ break;
+ }
+ return val;
+}
+
+void write_val_to_reg(addr_t reg_ptr, addr_t val, int size)
+{
+ switch (size) {
+ case 1:
+ *(uint8_t*)reg_ptr = val;
+ break;
+ case 2:
+ *(uint16_t*)reg_ptr = val;
+ break;
+ case 4:
+ *(uint64_t*)reg_ptr = (uint32_t)val;
+ break;
+ case 8:
+ *(uint64_t*)reg_ptr = val;
+ break;
+ default:
+ VM_PANIC("write_val: Unknown size\n");
+ break;
+ }
+}
+
+static bool is_host_reg(struct CPUState* cpu, addr_t ptr) {
+ return (ptr > (addr_t)cpu && ptr < (addr_t)cpu + sizeof(struct CPUState)) ||
+ (ptr > (addr_t)cpu->hvf_x86 && ptr < (addr_t)(cpu->hvf_x86 + sizeof(struct hvf_x86_state)));
+}
+
+void write_val_ext(struct CPUState* cpu, addr_t ptr, addr_t val, int size)
+{
+ if (is_host_reg(cpu, ptr)) {
+ write_val_to_reg(ptr, val, size);
+ return;
+ }
+ vmx_write_mem(cpu, ptr, &val, size);
+}
+
+uint8_t *read_mmio(struct CPUState* cpu, addr_t ptr, int bytes)
+{
+ vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, ptr, bytes);
+ return cpu->hvf_x86->mmio_buf;
+}
+
+addr_t read_val_ext(struct CPUState* cpu, addr_t ptr, int size)
+{
+ addr_t val;
+ uint8_t *mmio_ptr;
+
+ if (is_host_reg(cpu, ptr)) {
+ return read_val_from_reg(ptr, size);
+ }
+
+ mmio_ptr = read_mmio(cpu, ptr, size);
+ switch (size) {
+ case 1:
+ val = *(uint8_t*)mmio_ptr;
+ break;
+ case 2:
+ val = *(uint16_t*)mmio_ptr;
+ break;
+ case 4:
+ val = *(uint32_t*)mmio_ptr;
+ break;
+ case 8:
+ val = *(uint64_t*)mmio_ptr;
+ break;
+ default:
+ VM_PANIC("bad size\n");
+ break;
+ }
+ return val;
+}
+
+static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode, int n, bool val_op0, bool val_op1, bool val_op2)
+{
+ int i;
+ bool calc_val[3] = {val_op0, val_op1, val_op2};
+
+ for (i = 0; i < n; i++) {
+ switch (decode->op[i].type) {
+ case X86_VAR_IMMEDIATE:
+ break;
+ case X86_VAR_REG:
+ VM_PANIC_ON(!decode->op[i].ptr);
+ if (calc_val[i])
+ decode->op[i].val = read_val_from_reg(decode->op[i].ptr, decode->operand_size);
+ break;
+ case X86_VAR_RM:
+ calc_modrm_operand(cpu, decode, &decode->op[i]);
+ if (calc_val[i])
+ decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
+ break;
+ case X86_VAR_OFFSET:
+ decode->op[i].ptr = decode_linear_addr(cpu, decode, decode->op[i].ptr, REG_SEG_DS);
+ if (calc_val[i])
+ decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void exec_mov(struct CPUState *cpu, struct x86_decode *decode)
+{
+ fetch_operands(cpu, decode, 2, false, true, false);
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_add(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_or(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_LOGIC_CMD(cpu, decode, |, SET_FLAGS_OSZAPC_LOGIC, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_adc(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_ARITH_CMD(cpu, decode, +get_CF(cpu)+, SET_FLAGS_OSZAPC_ADD, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_sbb(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_ARITH_CMD(cpu, decode, -get_CF(cpu)-, SET_FLAGS_OSZAPC_SUB, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_and(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_LOGIC_CMD(cpu, decode, &, SET_FLAGS_OSZAPC_LOGIC, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_sub(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_xor(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_LOGIC_CMD(cpu, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_neg(struct CPUState *cpu, struct x86_decode *decode)
+{
+ //EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ int32_t val;
+ fetch_operands(cpu, decode, 2, true, true, false);
+
+ val = 0 - sign(decode->op[1].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[1].ptr, val, decode->operand_size);
+
+ if (4 == decode->operand_size) {
+ SET_FLAGS_OSZAPC_SUB_32(0, 0 - val, val);
+ }
+ else if (2 == decode->operand_size) {
+ SET_FLAGS_OSZAPC_SUB_16(0, 0 - val, val);
+ }
+ else if (1 == decode->operand_size) {
+ SET_FLAGS_OSZAPC_SUB_8(0, 0 - val, val);
+ } else {
+ VM_PANIC("bad op size\n");
+ }
+
+ //lflags_to_rflags(cpu);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_cmp(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_inc(struct CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[1].type = X86_VAR_IMMEDIATE;
+ decode->op[1].val = 0;
+
+ EXEC_2OP_ARITH_CMD(cpu, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_dec(struct CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[1].type = X86_VAR_IMMEDIATE;
+ decode->op[1].val = 0;
+
+ EXEC_2OP_ARITH_CMD(cpu, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_tst(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_LOGIC_CMD(cpu, decode, &, SET_FLAGS_OSZAPC_LOGIC, false);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_not(struct CPUState *cpu, struct x86_decode *decode)
+{
+ fetch_operands(cpu, decode, 1, true, false, false);
+
+ write_val_ext(cpu, decode->op[0].ptr, ~decode->op[0].val, decode->operand_size);
+ RIP(cpu) += decode->len;
+}
+
+void exec_movzx(struct CPUState *cpu, struct x86_decode *decode)
+{
+ int src_op_size;
+ int op_size = decode->operand_size;
+
+ fetch_operands(cpu, decode, 1, false, false, false);
+
+ if (0xb6 == decode->opcode[1])
+ src_op_size = 1;
+ else
+ src_op_size = 2;
+ decode->operand_size = src_op_size;
+ calc_modrm_operand(cpu, decode, &decode->op[1]);
+ decode->op[1].val = read_val_ext(cpu, decode->op[1].ptr, src_op_size);
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_out(struct CPUState *cpu, struct x86_decode *decode)
+{
+ switch (decode->opcode[0]) {
+ case 0xe6:
+ hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 1, 1, 1);
+ break;
+ case 0xe7:
+ hvf_handle_io(cpu, decode->op[0].val, &RAX(cpu), 1, decode->operand_size, 1);
+ break;
+ case 0xee:
+ hvf_handle_io(cpu, DX(cpu), &AL(cpu), 1, 1, 1);
+ break;
+ case 0xef:
+ hvf_handle_io(cpu, DX(cpu), &RAX(cpu), 1, decode->operand_size, 1);
+ break;
+ default:
+ VM_PANIC("Bad out opcode\n");
+ break;
+ }
+ RIP(cpu) += decode->len;
+}
+
+static void exec_in(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t val = 0;
+ switch (decode->opcode[0]) {
+ case 0xe4:
+ hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 0, 1, 1);
+ break;
+ case 0xe5:
+ hvf_handle_io(cpu, decode->op[0].val, &val, 0, decode->operand_size, 1);
+ if (decode->operand_size == 2)
+ AX(cpu) = val;
+ else
+ RAX(cpu) = (uint32_t)val;
+ break;
+ case 0xec:
+ hvf_handle_io(cpu, DX(cpu), &AL(cpu), 0, 1, 1);
+ break;
+ case 0xed:
+ hvf_handle_io(cpu, DX(cpu), &val, 0, decode->operand_size, 1);
+ if (decode->operand_size == 2)
+ AX(cpu) = val;
+ else
+ RAX(cpu) = (uint32_t)val;
+
+ break;
+ default:
+ VM_PANIC("Bad in opcode\n");
+ break;
+ }
+
+ RIP(cpu) += decode->len;
+}
+
+static inline void string_increment_reg(struct CPUState * cpu, int reg, struct x86_decode *decode)
+{
+ addr_t val = read_reg(cpu, reg, decode->addressing_size);
+ if (cpu->hvf_x86->rflags.df)
+ val -= decode->operand_size;
+ else
+ val += decode->operand_size;
+ write_reg(cpu, reg, val, decode->addressing_size);
+}
+
+static inline void string_rep(struct CPUState * cpu, struct x86_decode *decode, void (*func)(struct CPUState *cpu, struct x86_decode *ins), int rep)
+{
+ addr_t rcx = read_reg(cpu, REG_RCX, decode->addressing_size);
+ while (rcx--) {
+ func(cpu, decode);
+ write_reg(cpu, REG_RCX, rcx, decode->addressing_size);
+ if ((PREFIX_REP == rep) && !get_ZF(cpu))
+ break;
+ if ((PREFIX_REPN == rep) && get_ZF(cpu))
+ break;
+ }
+}
+
+static void exec_ins_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+
+ hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 0, decode->operand_size, 1);
+ vmx_write_mem(cpu, addr, cpu->hvf_x86->mmio_buf, decode->operand_size);
+
+ string_increment_reg(cpu, REG_RDI, decode);
+}
+
+static void exec_ins(struct CPUState *cpu, struct x86_decode *decode)
+{
+ if (decode->rep)
+ string_rep(cpu, decode, exec_ins_single, 0);
+ else
+ exec_ins_single(cpu, decode);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_outs_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
+
+ vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, addr, decode->operand_size);
+ hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 1, decode->operand_size, 1);
+
+ string_increment_reg(cpu, REG_RSI, decode);
+}
+
+static void exec_outs(struct CPUState *cpu, struct x86_decode *decode)
+{
+ if (decode->rep)
+ string_rep(cpu, decode, exec_outs_single, 0);
+ else
+ exec_outs_single(cpu, decode);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_movs_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t src_addr;
+ addr_t dst_addr;
+ addr_t val;
+
+ src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
+ dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+
+ val = read_val_ext(cpu, src_addr, decode->operand_size);
+ write_val_ext(cpu, dst_addr, val, decode->operand_size);
+
+ string_increment_reg(cpu, REG_RSI, decode);
+ string_increment_reg(cpu, REG_RDI, decode);
+}
+
+static void exec_movs(struct CPUState *cpu, struct x86_decode *decode)
+{
+ if (decode->rep) {
+ string_rep(cpu, decode, exec_movs_single, 0);
+ }
+ else
+ exec_movs_single(cpu, decode);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_cmps_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t src_addr;
+ addr_t dst_addr;
+
+ src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
+ dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+
+ decode->op[0].type = X86_VAR_IMMEDIATE;
+ decode->op[0].val = read_val_ext(cpu, src_addr, decode->operand_size);
+ decode->op[1].type = X86_VAR_IMMEDIATE;
+ decode->op[1].val = read_val_ext(cpu, dst_addr, decode->operand_size);
+
+ EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+
+ string_increment_reg(cpu, REG_RSI, decode);
+ string_increment_reg(cpu, REG_RDI, decode);
+}
+
+static void exec_cmps(struct CPUState *cpu, struct x86_decode *decode)
+{
+ if (decode->rep) {
+ string_rep(cpu, decode, exec_cmps_single, decode->rep);
+ }
+ else
+ exec_cmps_single(cpu, decode);
+ RIP(cpu) += decode->len;
+}
+
+
+static void exec_stos_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t addr;
+ addr_t val;
+
+ addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+ val = read_reg(cpu, REG_RAX, decode->operand_size);
+ vmx_write_mem(cpu, addr, &val, decode->operand_size);
+
+ string_increment_reg(cpu, REG_RDI, decode);
+}
+
+
+static void exec_stos(struct CPUState *cpu, struct x86_decode *decode)
+{
+ if (decode->rep) {
+ string_rep(cpu, decode, exec_stos_single, 0);
+ }
+ else
+ exec_stos_single(cpu, decode);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_scas_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t addr;
+
+ addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+ decode->op[1].type = X86_VAR_IMMEDIATE;
+ vmx_read_mem(cpu, &decode->op[1].val, addr, decode->operand_size);
+
+ EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ string_increment_reg(cpu, REG_RDI, decode);
+}
+
+static void exec_scas(struct CPUState *cpu, struct x86_decode *decode)
+{
+ decode->op[0].type = X86_VAR_REG;
+ decode->op[0].reg = REG_RAX;
+ if (decode->rep) {
+ string_rep(cpu, decode, exec_scas_single, decode->rep);
+ }
+ else
+ exec_scas_single(cpu, decode);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_lods_single(struct CPUState *cpu, struct x86_decode *decode)
+{
+ addr_t addr;
+ addr_t val = 0;
+
+ addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
+ vmx_read_mem(cpu, &val, addr, decode->operand_size);
+ write_reg(cpu, REG_RAX, val, decode->operand_size);
+
+ string_increment_reg(cpu, REG_RSI, decode);
+}
+
+static void exec_lods(struct CPUState *cpu, struct x86_decode *decode)
+{
+ if (decode->rep) {
+ string_rep(cpu, decode, exec_lods_single, 0);
+ }
+ else
+ exec_lods_single(cpu, decode);
+
+ RIP(cpu) += decode->len;
+}
+
+#define MSR_IA32_UCODE_REV 0x00000017
+
+void simulate_rdmsr(struct CPUState *cpu)
+{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ uint32_t msr = ECX(cpu);
+ uint64_t val = 0;
+
+ switch (msr) {
+ case MSR_IA32_TSC:
+ val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET);
+ break;
+ case MSR_IA32_APICBASE:
+ val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
+ break;
+ case MSR_IA32_UCODE_REV:
+ val = (0x100000000ULL << 32) | 0x100000000ULL;
+ break;
+ case MSR_EFER:
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
+ break;
+ case MSR_FSBASE:
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE);
+ break;
+ case MSR_GSBASE:
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE);
+ break;
+ case MSR_KERNELGSBASE:
+ val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE);
+ break;
+ case MSR_STAR:
+ abort();
+ break;
+ case MSR_LSTAR:
+ abort();
+ break;
+ case MSR_CSTAR:
+ abort();
+ break;
+ case MSR_IA32_MISC_ENABLE:
+ val = env->msr_ia32_misc_enable;
+ break;
+ case MSR_MTRRphysBase(0):
+ case MSR_MTRRphysBase(1):
+ case MSR_MTRRphysBase(2):
+ case MSR_MTRRphysBase(3):
+ case MSR_MTRRphysBase(4):
+ case MSR_MTRRphysBase(5):
+ case MSR_MTRRphysBase(6):
+ case MSR_MTRRphysBase(7):
+ val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base;
+ break;
+ case MSR_MTRRphysMask(0):
+ case MSR_MTRRphysMask(1):
+ case MSR_MTRRphysMask(2):
+ case MSR_MTRRphysMask(3):
+ case MSR_MTRRphysMask(4):
+ case MSR_MTRRphysMask(5):
+ case MSR_MTRRphysMask(6):
+ case MSR_MTRRphysMask(7):
+ val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask;
+ break;
+ case MSR_MTRRfix64K_00000:
+ val = env->mtrr_fixed[0];
+ break;
+ case MSR_MTRRfix16K_80000:
+ case MSR_MTRRfix16K_A0000:
+ val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1];
+ break;
+ case MSR_MTRRfix4K_C0000:
+ case MSR_MTRRfix4K_C8000:
+ case MSR_MTRRfix4K_D0000:
+ case MSR_MTRRfix4K_D8000:
+ case MSR_MTRRfix4K_E0000:
+ case MSR_MTRRfix4K_E8000:
+ case MSR_MTRRfix4K_F0000:
+ case MSR_MTRRfix4K_F8000:
+ val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3];
+ break;
+ case MSR_MTRRdefType:
+ val = env->mtrr_deftype;
+ break;
+ default:
+ // fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr);
+ val = 0;
+ break;
+ }
+
+ RAX(cpu) = (uint32_t)val;
+ RDX(cpu) = (uint32_t)(val >> 32);
+}
+
+static void exec_rdmsr(struct CPUState *cpu, struct x86_decode *decode)
+{
+ simulate_rdmsr(cpu);
+ RIP(cpu) += decode->len;
+}
+
+void simulate_wrmsr(struct CPUState *cpu)
+{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ uint32_t msr = ECX(cpu);
+ uint64_t data = ((uint64_t)EDX(cpu) << 32) | EAX(cpu);
+
+ switch (msr) {
+ case MSR_IA32_TSC:
+ // if (!osx_is_sierra())
+ // wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp());
+ //hv_vm_sync_tsc(data);
+ break;
+ case MSR_IA32_APICBASE:
+ cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
+ break;
+ case MSR_FSBASE:
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data);
+ break;
+ case MSR_GSBASE:
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data);
+ break;
+ case MSR_KERNELGSBASE:
+ wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data);
+ break;
+ case MSR_STAR:
+ abort();
+ break;
+ case MSR_LSTAR:
+ abort();
+ break;
+ case MSR_CSTAR:
+ abort();
+ break;
+ case MSR_EFER:
+ cpu->hvf_x86->efer.efer = data;
+ //printf("new efer %llx\n", EFER(cpu));
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);
+ if (data & EFER_NXE)
+ hv_vcpu_invalidate_tlb(cpu->hvf_fd);
+ break;
+ case MSR_MTRRphysBase(0):
+ case MSR_MTRRphysBase(1):
+ case MSR_MTRRphysBase(2):
+ case MSR_MTRRphysBase(3):
+ case MSR_MTRRphysBase(4):
+ case MSR_MTRRphysBase(5):
+ case MSR_MTRRphysBase(6):
+ case MSR_MTRRphysBase(7):
+ env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base = data;
+ break;
+ case MSR_MTRRphysMask(0):
+ case MSR_MTRRphysMask(1):
+ case MSR_MTRRphysMask(2):
+ case MSR_MTRRphysMask(3):
+ case MSR_MTRRphysMask(4):
+ case MSR_MTRRphysMask(5):
+ case MSR_MTRRphysMask(6):
+ case MSR_MTRRphysMask(7):
+ env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask = data;
+ break;
+ case MSR_MTRRfix64K_00000:
+ env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix64K_00000] = data;
+ break;
+ case MSR_MTRRfix16K_80000:
+ case MSR_MTRRfix16K_A0000:
+ env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1] = data;
+ break;
+ case MSR_MTRRfix4K_C0000:
+ case MSR_MTRRfix4K_C8000:
+ case MSR_MTRRfix4K_D0000:
+ case MSR_MTRRfix4K_D8000:
+ case MSR_MTRRfix4K_E0000:
+ case MSR_MTRRfix4K_E8000:
+ case MSR_MTRRfix4K_F0000:
+ case MSR_MTRRfix4K_F8000:
+ env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3] = data;
+ break;
+ case MSR_MTRRdefType:
+ env->mtrr_deftype = data;
+ break;
+ default:
+ break;
+ }
+
+ /* Related to support known hypervisor interface */
+ // if (g_hypervisor_iface)
+ // g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
+
+ //printf("write msr %llx\n", RCX(cpu));
+}
+
+static void exec_wrmsr(struct CPUState *cpu, struct x86_decode *decode)
+{
+ simulate_wrmsr(cpu);
+ RIP(cpu) += decode->len;
+}
+
+/*
+ * flag:
+ * 0 - bt, 1 - btc, 2 - bts, 3 - btr
+ */
+static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
+{
+ int32_t displacement;
+ uint8_t index;
+ bool cf;
+ int mask = (4 == decode->operand_size) ? 0x1f : 0xf;
+
+ VM_PANIC_ON(decode->rex.rex);
+
+ fetch_operands(cpu, decode, 2, false, true, false);
+ index = decode->op[1].val & mask;
+
+ if (decode->op[0].type != X86_VAR_REG) {
+ if (4 == decode->operand_size) {
+ displacement = ((int32_t) (decode->op[1].val & 0xffffffe0)) / 32;
+ decode->op[0].ptr += 4 * displacement;
+ } else if (2 == decode->operand_size) {
+ displacement = ((int16_t) (decode->op[1].val & 0xfff0)) / 16;
+ decode->op[0].ptr += 2 * displacement;
+ } else {
+ VM_PANIC("bt 64bit\n");
+ }
+ }
+ decode->op[0].val = read_val_ext(cpu, decode->op[0].ptr, decode->operand_size);
+ cf = (decode->op[0].val >> index) & 0x01;
+
+ switch (flag) {
+ case 0:
+ set_CF(cpu, cf);
+ return;
+ case 1:
+ decode->op[0].val ^= (1u << index);
+ break;
+ case 2:
+ decode->op[0].val |= (1u << index);
+ break;
+ case 3:
+ decode->op[0].val &= ~(1u << index);
+ break;
+ }
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[0].val, decode->operand_size);
+ set_CF(cpu, cf);
+}
+
+static void exec_bt(struct CPUState *cpu, struct x86_decode *decode)
+{
+ do_bt(cpu, decode, 0);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_btc(struct CPUState *cpu, struct x86_decode *decode)
+{
+ do_bt(cpu, decode, 1);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_btr(struct CPUState *cpu, struct x86_decode *decode)
+{
+ do_bt(cpu, decode, 3);
+ RIP(cpu) += decode->len;
+}
+
+static void exec_bts(struct CPUState *cpu, struct x86_decode *decode)
+{
+ do_bt(cpu, decode, 2);
+ RIP(cpu) += decode->len;
+}
+
+void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t count;
+ int of = 0, cf = 0;
+
+ fetch_operands(cpu, decode, 2, true, true, false);
+
+ count = decode->op[1].val;
+ count &= 0x1f; // count is masked to 5 bits
+ if (!count)
+ goto exit;
+
+ switch (decode->operand_size) {
+ case 1:
+ {
+ uint8_t res = 0;
+ if (count <= 8) {
+ res = (decode->op[0].val << count);
+ cf = (decode->op[0].val >> (8 - count)) & 0x1;
+ of = cf ^ (res >> 7);
+ }
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ SET_FLAGS_OSZAPC_LOGIC_8(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 2:
+ {
+ uint16_t res = 0;
+
+ /* from bochs */
+ if (count <= 16) {
+ res = (decode->op[0].val << count);
+ cf = (decode->op[0].val >> (16 - count)) & 0x1;
+ of = cf ^ (res >> 15); // of = cf ^ result15
+ }
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ SET_FLAGS_OSZAPC_LOGIC_16(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 4:
+ {
+ uint32_t res = decode->op[0].val << count;
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ SET_FLAGS_OSZAPC_LOGIC_32(res);
+ cf = (decode->op[0].val >> (32 - count)) & 0x1;
+ of = cf ^ (res >> 31); // of = cf ^ result31
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ default:
+ abort();
+ }
+
+exit:
+ //lflags_to_rflags(cpu);
+ RIP(cpu) += decode->len;
+}
+
+void exec_movsx(struct CPUState *cpu, struct x86_decode *decode)
+{
+ int src_op_size;
+ int op_size = decode->operand_size;
+
+ fetch_operands(cpu, decode, 2, false, false, false);
+
+ if (0xbe == decode->opcode[1])
+ src_op_size = 1;
+ else
+ src_op_size = 2;
+
+ decode->operand_size = src_op_size;
+ calc_modrm_operand(cpu, decode, &decode->op[1]);
+ decode->op[1].val = sign(read_val_ext(cpu, decode->op[1].ptr, src_op_size), src_op_size);
+
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
+
+ RIP(cpu) += decode->len;
+}
+
+void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t count;
+
+ fetch_operands(cpu, decode, 2, true, true, false);
+ count = decode->op[1].val;
+
+ switch (decode->operand_size) {
+ case 1:
+ {
+ uint32_t bit6, bit7;
+ uint8_t res;
+
+ if ((count & 0x07) == 0) {
+ if (count & 0x18) {
+ bit6 = ((uint8_t)decode->op[0].val >> 6) & 1;
+ bit7 = ((uint8_t)decode->op[0].val >> 7) & 1;
+ SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
+ }
+ } else {
+ count &= 0x7; /* use only bottom 3 bits */
+ res = ((uint8_t)decode->op[0].val >> count) | ((uint8_t)decode->op[0].val << (8 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ bit6 = (res >> 6) & 1;
+ bit7 = (res >> 7) & 1;
+ /* set eflags: ROR count affects the following flags: C, O */
+ SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
+ }
+ break;
+ }
+ case 2:
+ {
+ uint32_t bit14, bit15;
+ uint16_t res;
+
+ if ((count & 0x0f) == 0) {
+ if (count & 0x10) {
+ bit14 = ((uint16_t)decode->op[0].val >> 14) & 1;
+ bit15 = ((uint16_t)decode->op[0].val >> 15) & 1;
+ // of = result14 ^ result15
+ SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
+ }
+ } else {
+ count &= 0x0f; // use only 4 LSB's
+ res = ((uint16_t)decode->op[0].val >> count) | ((uint16_t)decode->op[0].val << (16 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+
+ bit14 = (res >> 14) & 1;
+ bit15 = (res >> 15) & 1;
+ // of = result14 ^ result15
+ SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
+ }
+ break;
+ }
+ case 4:
+ {
+ uint32_t bit31, bit30;
+ uint32_t res;
+
+ count &= 0x1f;
+ if (count) {
+ res = ((uint32_t)decode->op[0].val >> count) | ((uint32_t)decode->op[0].val << (32 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+
+ bit31 = (res >> 31) & 1;
+ bit30 = (res >> 30) & 1;
+ // of = result30 ^ result31
+ SET_FLAGS_OxxxxC(cpu, bit30 ^ bit31, bit31);
+ }
+ break;
+ }
+ }
+ RIP(cpu) += decode->len;
+}
+
+void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t count;
+
+ fetch_operands(cpu, decode, 2, true, true, false);
+ count = decode->op[1].val;
+
+ switch (decode->operand_size) {
+ case 1:
+ {
+ uint32_t bit0, bit7;
+ uint8_t res;
+
+ if ((count & 0x07) == 0) {
+ if (count & 0x18) {
+ bit0 = ((uint8_t)decode->op[0].val & 1);
+ bit7 = ((uint8_t)decode->op[0].val >> 7);
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
+ }
+ } else {
+ count &= 0x7; // use only lowest 3 bits
+ res = ((uint8_t)decode->op[0].val << count) | ((uint8_t)decode->op[0].val >> (8 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ /* set eflags:
+ * ROL count affects the following flags: C, O
+ */
+ bit0 = (res & 1);
+ bit7 = (res >> 7);
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
+ }
+ break;
+ }
+ case 2:
+ {
+ uint32_t bit0, bit15;
+ uint16_t res;
+
+ if ((count & 0x0f) == 0) {
+ if (count & 0x10) {
+ bit0 = ((uint16_t)decode->op[0].val & 0x1);
+ bit15 = ((uint16_t)decode->op[0].val >> 15);
+ // of = cf ^ result15
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
+ }
+ } else {
+ count &= 0x0f; // only use bottom 4 bits
+ res = ((uint16_t)decode->op[0].val << count) | ((uint16_t)decode->op[0].val >> (16 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ bit0 = (res & 0x1);
+ bit15 = (res >> 15);
+ // of = cf ^ result15
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
+ }
+ break;
+ }
+ case 4:
+ {
+ uint32_t bit0, bit31;
+ uint32_t res;
+
+ count &= 0x1f;
+ if (count) {
+ res = ((uint32_t)decode->op[0].val << count) | ((uint32_t)decode->op[0].val >> (32 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ bit0 = (res & 0x1);
+ bit31 = (res >> 31);
+ // of = cf ^ result31
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit31, bit0);
+ }
+ break;
+ }
+ }
+ RIP(cpu) += decode->len;
+}
+
+
+void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t count;
+ int of = 0, cf = 0;
+
+ fetch_operands(cpu, decode, 2, true, true, false);
+ count = decode->op[1].val & 0x1f;
+
+ switch(decode->operand_size) {
+ case 1:
+ {
+ uint8_t op1_8 = decode->op[0].val;
+ uint8_t res;
+ count %= 9;
+ if (!count)
+ break;
+
+ if (1 == count)
+ res = (op1_8 << 1) | get_CF(cpu);
+ else
+ res = (op1_8 << count) | (get_CF(cpu) << (count - 1)) | (op1_8 >> (9 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+
+ cf = (op1_8 >> (8 - count)) & 0x01;
+ of = cf ^ (res >> 7); // of = cf ^ result7
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 2:
+ {
+ uint16_t res;
+ uint16_t op1_16 = decode->op[0].val;
+
+ count %= 17;
+ if (!count)
+ break;
+
+ if (1 == count)
+ res = (op1_16 << 1) | get_CF(cpu);
+ else if (count == 16)
+ res = (get_CF(cpu) << 15) | (op1_16 >> 1);
+ else // 2..15
+ res = (op1_16 << count) | (get_CF(cpu) << (count - 1)) | (op1_16 >> (17 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+
+ cf = (op1_16 >> (16 - count)) & 0x1;
+ of = cf ^ (res >> 15); // of = cf ^ result15
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 4:
+ {
+ uint32_t res;
+ uint32_t op1_32 = decode->op[0].val;
+
+ if (!count)
+ break;
+
+ if (1 == count)
+ res = (op1_32 << 1) | get_CF(cpu);
+ else
+ res = (op1_32 << count) | (get_CF(cpu) << (count - 1)) | (op1_32 >> (33 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+
+ cf = (op1_32 >> (32 - count)) & 0x1;
+ of = cf ^ (res >> 31); // of = cf ^ result31
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ }
+ RIP(cpu) += decode->len;
+}
+
+void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
+{
+ uint8_t count;
+ int of = 0, cf = 0;
+
+ fetch_operands(cpu, decode, 2, true, true, false);
+ count = decode->op[1].val & 0x1f;
+
+ switch(decode->operand_size) {
+ case 1:
+ {
+ uint8_t op1_8 = decode->op[0].val;
+ uint8_t res;
+
+ count %= 9;
+ if (!count)
+ break;
+ res = (op1_8 >> count) | (get_CF(cpu) << (8 - count)) | (op1_8 << (9 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+
+ cf = (op1_8 >> (count - 1)) & 0x1;
+ of = (((res << 1) ^ res) >> 7) & 0x1; // of = result6 ^ result7
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 2:
+ {
+ uint16_t op1_16 = decode->op[0].val;
+ uint16_t res;
+
+ count %= 17;
+ if (!count)
+ break;
+ res = (op1_16 >> count) | (get_CF(cpu) << (16 - count)) | (op1_16 << (17 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+
+ cf = (op1_16 >> (count - 1)) & 0x1;
+ of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; // of = result15 ^ result14
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 4:
+ {
+ uint32_t res;
+ uint32_t op1_32 = decode->op[0].val;
+
+ if (!count)
+ break;
+
+ if (1 == count)
+ res = (op1_32 >> 1) | (get_CF(cpu) << 31);
+ else
+ res = (op1_32 >> count) | (get_CF(cpu) << (32 - count)) | (op1_32 << (33 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+
+ cf = (op1_32 >> (count - 1)) & 0x1;
+ of = ((res << 1) ^ res) >> 31; // of = result30 ^ result31
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ }
+ RIP(cpu) += decode->len;
+}
+
+static void exec_xchg(struct CPUState *cpu, struct x86_decode *decode)
+{
+ fetch_operands(cpu, decode, 2, true, true, false);
+
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
+
+ RIP(cpu) += decode->len;
+}
+
+static void exec_xadd(struct CPUState *cpu, struct x86_decode *decode)
+{
+ EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
+ write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
+
+ RIP(cpu) += decode->len;
+}
+
+static struct cmd_handler {
+ enum x86_decode_cmd cmd;
+ void (*handler)(struct CPUState *cpu, struct x86_decode *ins);
+} handlers[] = {
+ {X86_DECODE_CMD_INVL, NULL,},
+ {X86_DECODE_CMD_MOV, exec_mov},
+ {X86_DECODE_CMD_ADD, exec_add},
+ {X86_DECODE_CMD_OR, exec_or},
+ {X86_DECODE_CMD_ADC, exec_adc},
+ {X86_DECODE_CMD_SBB, exec_sbb},
+ {X86_DECODE_CMD_AND, exec_and},
+ {X86_DECODE_CMD_SUB, exec_sub},
+ {X86_DECODE_CMD_NEG, exec_neg},
+ {X86_DECODE_CMD_XOR, exec_xor},
+ {X86_DECODE_CMD_CMP, exec_cmp},
+ {X86_DECODE_CMD_INC, exec_inc},
+ {X86_DECODE_CMD_DEC, exec_dec},
+ {X86_DECODE_CMD_TST, exec_tst},
+ {X86_DECODE_CMD_NOT, exec_not},
+ {X86_DECODE_CMD_MOVZX, exec_movzx},
+ {X86_DECODE_CMD_OUT, exec_out},
+ {X86_DECODE_CMD_IN, exec_in},
+ {X86_DECODE_CMD_INS, exec_ins},
+ {X86_DECODE_CMD_OUTS, exec_outs},
+ {X86_DECODE_CMD_RDMSR, exec_rdmsr},
+ {X86_DECODE_CMD_WRMSR, exec_wrmsr},
+ {X86_DECODE_CMD_BT, exec_bt},
+ {X86_DECODE_CMD_BTR, exec_btr},
+ {X86_DECODE_CMD_BTC, exec_btc},
+ {X86_DECODE_CMD_BTS, exec_bts},
+ {X86_DECODE_CMD_SHL, exec_shl},
+ {X86_DECODE_CMD_ROL, exec_rol},
+ {X86_DECODE_CMD_ROR, exec_ror},
+ {X86_DECODE_CMD_RCR, exec_rcr},
+ {X86_DECODE_CMD_RCL, exec_rcl},
+ /*{X86_DECODE_CMD_CPUID, exec_cpuid},*/
+ {X86_DECODE_CMD_MOVS, exec_movs},
+ {X86_DECODE_CMD_CMPS, exec_cmps},
+ {X86_DECODE_CMD_STOS, exec_stos},
+ {X86_DECODE_CMD_SCAS, exec_scas},
+ {X86_DECODE_CMD_LODS, exec_lods},
+ {X86_DECODE_CMD_MOVSX, exec_movsx},
+ {X86_DECODE_CMD_XCHG, exec_xchg},
+ {X86_DECODE_CMD_XADD, exec_xadd},
+};
+
+static struct cmd_handler _cmd_handler[X86_DECODE_CMD_LAST];
+
+static void init_cmd_handler(CPUState *cpu)
+{
+ int i;
+ for (i = 0; i < ARRAY_SIZE(handlers); i++)
+ _cmd_handler[handlers[i].cmd] = handlers[i];
+}
+
+static void print_debug(struct CPUState *cpu)
+{
+ printf("%llx: eax %llx ebx %llx ecx %llx edx %llx esi %llx edi %llx ebp %llx esp %llx flags %llx\n", RIP(cpu), RAX(cpu), RBX(cpu), RCX(cpu), RDX(cpu), RSI(cpu), RDI(cpu), RBP(cpu), RSP(cpu), EFLAGS(cpu));
+}
+
+void load_regs(struct CPUState *cpu)
+{
+ int i = 0;
+ RRX(cpu, REG_RAX) = rreg(cpu->hvf_fd, HV_X86_RAX);
+ RRX(cpu, REG_RBX) = rreg(cpu->hvf_fd, HV_X86_RBX);
+ RRX(cpu, REG_RCX) = rreg(cpu->hvf_fd, HV_X86_RCX);
+ RRX(cpu, REG_RDX) = rreg(cpu->hvf_fd, HV_X86_RDX);
+ RRX(cpu, REG_RSI) = rreg(cpu->hvf_fd, HV_X86_RSI);
+ RRX(cpu, REG_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI);
+ RRX(cpu, REG_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP);
+ RRX(cpu, REG_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP);
+ for (i = 8; i < 16; i++)
+ RRX(cpu, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
+
+ RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
+ rflags_to_lflags(cpu);
+ RIP(cpu) = rreg(cpu->hvf_fd, HV_X86_RIP);
+
+ //print_debug(cpu);
+}
+
+void store_regs(struct CPUState *cpu)
+{
+ int i = 0;
+ wreg(cpu->hvf_fd, HV_X86_RAX, RAX(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RBX, RBX(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RCX, RCX(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RDX, RDX(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RSI, RSI(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RDI, RDI(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RBP, RBP(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RSP, RSP(cpu));
+ for (i = 8; i < 16; i++)
+ wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(cpu, i));
+
+ lflags_to_rflags(cpu);
+ wreg(cpu->hvf_fd, HV_X86_RFLAGS, RFLAGS(cpu));
+ macvm_set_rip(cpu, RIP(cpu));
+
+ //print_debug(cpu);
+}
+
+bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins)
+{
+ //if (hvf_vcpu_id(cpu))
+ //printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu), decode_cmd_to_string(ins->cmd));
+
+ if (0 && ins->is_fpu) {
+ VM_PANIC("emulate fpu\n");
+ } else {
+ if (!_cmd_handler[ins->cmd].handler) {
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0],
+ ins->opcode_len > 1 ? ins->opcode[1] : 0);
+ RIP(cpu) += ins->len;
+ return true;
+ }
+
+ VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler, "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0);
+ _cmd_handler[ins->cmd].handler(cpu, ins);
+ }
+ return true;
+}
+
+void init_emu(struct CPUState *cpu)
+{
+ init_cmd_handler(cpu);
+}
diff --git a/target/i386/hvf-utils/x86_emu.h b/target/i386/hvf-utils/x86_emu.h
new file mode 100644
index 0000000000..c56b2798fa
--- /dev/null
+++ b/target/i386/hvf-utils/x86_emu.h
@@ -0,0 +1,16 @@
+#ifndef __X86_EMU_H__
+#define __X86_EMU_H__
+
+#include "x86.h"
+#include "x86_decode.h"
+
+void init_emu(struct CPUState *cpu);
+bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins);
+
+void load_regs(struct CPUState *cpu);
+void store_regs(struct CPUState *cpu);
+
+void simulate_rdmsr(struct CPUState *cpu);
+void simulate_wrmsr(struct CPUState *cpu);
+
+#endif
diff --git a/target/i386/hvf-utils/x86_flags.c b/target/i386/hvf-utils/x86_flags.c
new file mode 100644
index 0000000000..ca876d03dd
--- /dev/null
+++ b/target/i386/hvf-utils/x86_flags.c
@@ -0,0 +1,317 @@
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2001-2012 The Bochs Project
+// Copyright (C) 2017 Google Inc.
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+/////////////////////////////////////////////////////////////////////////
+/*
+ * flags functions
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+
+#include "cpu.h"
+#include "x86_flags.h"
+#include "x86.h"
+
+void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf)
+{
+ uint32_t temp_po = new_of ^ new_cf;
+ cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PO | LF_MASK_CF);
+ cpu->hvf_x86->lflags.auxbits |= (temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF);
+}
+
+void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+{
+ SET_FLAGS_OSZAPC_SUB_32(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+{
+ SET_FLAGS_OSZAPC_SUB_16(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+{
+ SET_FLAGS_OSZAPC_SUB_8(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+{
+ SET_FLAGS_OSZAPC_ADD_32(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+{
+ SET_FLAGS_OSZAPC_ADD_16(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+{
+ SET_FLAGS_OSZAPC_ADD_8(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+{
+ SET_FLAGS_OSZAP_SUB_32(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+{
+ SET_FLAGS_OSZAP_SUB_16(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+{
+ SET_FLAGS_OSZAP_SUB_8(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+{
+ SET_FLAGS_OSZAP_ADD_32(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+{
+ SET_FLAGS_OSZAP_ADD_16(v1, v2, diff);
+}
+
+void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+{
+ SET_FLAGS_OSZAP_ADD_8(v1, v2, diff);
+}
+
+
+void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff)
+{
+ SET_FLAGS_OSZAPC_LOGIC_32(diff);
+}
+
+void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff)
+{
+ SET_FLAGS_OSZAPC_LOGIC_16(diff);
+}
+
+void SET_FLAGS_OSZAPC_LOGIC8(struct CPUState *cpu, uint8_t diff)
+{
+ SET_FLAGS_OSZAPC_LOGIC_8(diff);
+}
+
+void SET_FLAGS_SHR32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
+{
+ int cf = (v >> (count - 1)) & 0x1;
+ int of = (((res << 1) ^ res) >> 31);
+
+ SET_FLAGS_OSZAPC_LOGIC_32(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+}
+
+void SET_FLAGS_SHR16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
+{
+ int cf = (v >> (count - 1)) & 0x1;
+ int of = (((res << 1) ^ res) >> 15);
+
+ SET_FLAGS_OSZAPC_LOGIC_16(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+}
+
+void SET_FLAGS_SHR8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
+{
+ int cf = (v >> (count - 1)) & 0x1;
+ int of = (((res << 1) ^ res) >> 7);
+
+ SET_FLAGS_OSZAPC_LOGIC_8(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+}
+
+void SET_FLAGS_SAR32(struct CPUState *cpu, int32_t v, int count, uint32_t res)
+{
+ int cf = (v >> (count - 1)) & 0x1;
+
+ SET_FLAGS_OSZAPC_LOGIC_32(res);
+ SET_FLAGS_OxxxxC(cpu, 0, cf);
+}
+
+void SET_FLAGS_SAR16(struct CPUState *cpu, int16_t v, int count, uint16_t res)
+{
+ int cf = (v >> (count - 1)) & 0x1;
+
+ SET_FLAGS_OSZAPC_LOGIC_16(res);
+ SET_FLAGS_OxxxxC(cpu, 0, cf);
+}
+
+void SET_FLAGS_SAR8(struct CPUState *cpu, int8_t v, int count, uint8_t res)
+{
+ int cf = (v >> (count - 1)) & 0x1;
+
+ SET_FLAGS_OSZAPC_LOGIC_8(res);
+ SET_FLAGS_OxxxxC(cpu, 0, cf);
+}
+
+
+void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
+{
+ int of, cf;
+
+ cf = (v >> (32 - count)) & 0x1;
+ of = cf ^ (res >> 31);
+
+ SET_FLAGS_OSZAPC_LOGIC_32(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+}
+
+void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
+{
+ int of = 0, cf = 0;
+
+ if (count <= 16) {
+ cf = (v >> (16 - count)) & 0x1;
+ of = cf ^ (res >> 15);
+ }
+
+ SET_FLAGS_OSZAPC_LOGIC_16(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+}
+
+void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
+{
+ int of = 0, cf = 0;
+
+ if (count <= 8) {
+ cf = (v >> (8 - count)) & 0x1;
+ of = cf ^ (res >> 7);
+ }
+
+ SET_FLAGS_OSZAPC_LOGIC_8(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+}
+
+bool get_PF(struct CPUState *cpu)
+{
+ uint32_t temp = (255 & cpu->hvf_x86->lflags.result);
+ temp = temp ^ (255 & (cpu->hvf_x86->lflags.auxbits >> LF_BIT_PDB));
+ temp = (temp ^ (temp >> 4)) & 0x0F;
+ return (0x9669U >> temp) & 1;
+}
+
+void set_PF(struct CPUState *cpu, bool val)
+{
+ uint32_t temp = (255 & cpu->hvf_x86->lflags.result) ^ (!val);
+ cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PDB);
+ cpu->hvf_x86->lflags.auxbits |= (temp << LF_BIT_PDB);
+}
+
+bool _get_OF(struct CPUState *cpu)
+{
+ return ((cpu->hvf_x86->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
+}
+
+bool get_OF(struct CPUState *cpu)
+{
+ return _get_OF(cpu);
+}
+
+bool _get_CF(struct CPUState *cpu)
+{
+ return (cpu->hvf_x86->lflags.auxbits >> LF_BIT_CF) & 1;
+}
+
+bool get_CF(struct CPUState *cpu)
+{
+ return _get_CF(cpu);
+}
+
+void set_OF(struct CPUState *cpu, bool val)
+{
+ SET_FLAGS_OxxxxC(cpu, val, _get_CF(cpu));
+}
+
+void set_CF(struct CPUState *cpu, bool val)
+{
+ SET_FLAGS_OxxxxC(cpu, _get_OF(cpu), (val));
+}
+
+bool get_AF(struct CPUState *cpu)
+{
+ return (cpu->hvf_x86->lflags.auxbits >> LF_BIT_AF) & 1;
+}
+
+void set_AF(struct CPUState *cpu, bool val)
+{
+ cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_AF);
+ cpu->hvf_x86->lflags.auxbits |= (val) << LF_BIT_AF;
+}
+
+bool get_ZF(struct CPUState *cpu)
+{
+ return !cpu->hvf_x86->lflags.result;
+}
+
+void set_ZF(struct CPUState *cpu, bool val)
+{
+ if (val) {
+ cpu->hvf_x86->lflags.auxbits ^= (((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
+ // merge the parity bits into the Parity Delta Byte
+ uint32_t temp_pdb = (255 & cpu->hvf_x86->lflags.result);
+ cpu->hvf_x86->lflags.auxbits ^= (temp_pdb << LF_BIT_PDB);
+ // now zero the .result value
+ cpu->hvf_x86->lflags.result = 0;
+ } else
+ cpu->hvf_x86->lflags.result |= (1 << 8);
+}
+
+bool get_SF(struct CPUState *cpu)
+{
+ return ((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) ^ (cpu->hvf_x86->lflags.auxbits >> LF_BIT_SD)) & 1;
+}
+
+void set_SF(struct CPUState *cpu, bool val)
+{
+ bool temp_sf = get_SF(cpu);
+ cpu->hvf_x86->lflags.auxbits ^= (temp_sf ^ val) << LF_BIT_SD;
+}
+
+void set_OSZAPC(struct CPUState *cpu, uint32_t flags32)
+{
+ set_OF(cpu, cpu->hvf_x86->rflags.of);
+ set_SF(cpu, cpu->hvf_x86->rflags.sf);
+ set_ZF(cpu, cpu->hvf_x86->rflags.zf);
+ set_AF(cpu, cpu->hvf_x86->rflags.af);
+ set_PF(cpu, cpu->hvf_x86->rflags.pf);
+ set_CF(cpu, cpu->hvf_x86->rflags.cf);
+}
+
+void lflags_to_rflags(struct CPUState *cpu)
+{
+ cpu->hvf_x86->rflags.cf = get_CF(cpu);
+ cpu->hvf_x86->rflags.pf = get_PF(cpu);
+ cpu->hvf_x86->rflags.af = get_AF(cpu);
+ cpu->hvf_x86->rflags.zf = get_ZF(cpu);
+ cpu->hvf_x86->rflags.sf = get_SF(cpu);
+ cpu->hvf_x86->rflags.of = get_OF(cpu);
+}
+
+void rflags_to_lflags(struct CPUState *cpu)
+{
+ cpu->hvf_x86->lflags.auxbits = cpu->hvf_x86->lflags.result = 0;
+ set_OF(cpu, cpu->hvf_x86->rflags.of);
+ set_SF(cpu, cpu->hvf_x86->rflags.sf);
+ set_ZF(cpu, cpu->hvf_x86->rflags.zf);
+ set_AF(cpu, cpu->hvf_x86->rflags.af);
+ set_PF(cpu, cpu->hvf_x86->rflags.pf);
+ set_CF(cpu, cpu->hvf_x86->rflags.cf);
+}
diff --git a/target/i386/hvf-utils/x86_flags.h b/target/i386/hvf-utils/x86_flags.h
new file mode 100644
index 0000000000..f963f8ad1b
--- /dev/null
+++ b/target/i386/hvf-utils/x86_flags.h
@@ -0,0 +1,218 @@
+/////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2001-2012 The Bochs Project
+// Copyright (C) 2017 Google Inc.
+//
+// This library is free software; you can redistribute it and/or
+// modify it under the terms of the GNU Lesser General Public
+// License as published by the Free Software Foundation; either
+// version 2 of the License, or (at your option) any later version.
+//
+// This library is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Lesser General Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with this library; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
+/////////////////////////////////////////////////////////////////////////
+/*
+ * x86 eflags functions
+ */
+#ifndef __X86_FLAGS_H__
+#define __X86_FLAGS_H__
+
+#include "x86_gen.h"
+
+/* this is basically bocsh code */
+
+typedef struct lazy_flags {
+ addr_t result;
+ addr_t auxbits;
+} lazy_flags;
+
+#define LF_SIGN_BIT 31
+
+#define LF_BIT_SD (0) /* lazy Sign Flag Delta */
+#define LF_BIT_AF (3) /* lazy Adjust flag */
+#define LF_BIT_PDB (8) /* lazy Parity Delta Byte (8 bits) */
+#define LF_BIT_CF (31) /* lazy Carry Flag */
+#define LF_BIT_PO (30) /* lazy Partial Overflow = CF ^ OF */
+
+#define LF_MASK_SD (0x01 << LF_BIT_SD)
+#define LF_MASK_AF (0x01 << LF_BIT_AF)
+#define LF_MASK_PDB (0xFF << LF_BIT_PDB)
+#define LF_MASK_CF (0x01 << LF_BIT_CF)
+#define LF_MASK_PO (0x01 << LF_BIT_PO)
+
+#define ADD_COUT_VEC(op1, op2, result) \
+ (((op1) & (op2)) | (((op1) | (op2)) & (~(result))))
+
+#define SUB_COUT_VEC(op1, op2, result) \
+ (((~(op1)) & (op2)) | (((~(op1)) ^ (op2)) & (result)))
+
+#define GET_ADD_OVERFLOW(op1, op2, result, mask) \
+ ((((op1) ^ (result)) & ((op2) ^ (result))) & (mask))
+
+// *******************
+// OSZAPC
+// *******************
+
+/* size, carries, result */
+#define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \
+ addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
+ (((lf_carries) >> (size - 2)) << LF_BIT_PO); \
+ cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
+ if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
+ else VM_PANIC("unimplemented"); \
+ cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)temp; \
+}
+
+/* carries, result */
+#define SET_FLAGS_OSZAPC_8(carries, result) \
+ SET_FLAGS_OSZAPC_SIZE(8, carries, result)
+#define SET_FLAGS_OSZAPC_16(carries, result) \
+ SET_FLAGS_OSZAPC_SIZE(16, carries, result)
+#define SET_FLAGS_OSZAPC_32(carries, result) \
+ SET_FLAGS_OSZAPC_SIZE(32, carries, result)
+
+/* result */
+#define SET_FLAGS_OSZAPC_LOGIC_8(result_8) \
+ SET_FLAGS_OSZAPC_8(0, (result_8))
+#define SET_FLAGS_OSZAPC_LOGIC_16(result_16) \
+ SET_FLAGS_OSZAPC_16(0, (result_16))
+#define SET_FLAGS_OSZAPC_LOGIC_32(result_32) \
+ SET_FLAGS_OSZAPC_32(0, (result_32))
+#define SET_FLAGS_OSZAPC_LOGIC_SIZE(size, result) { \
+ if (32 == size) {SET_FLAGS_OSZAPC_LOGIC_32(result);} \
+ else if (16 == size) {SET_FLAGS_OSZAPC_LOGIC_16(result);} \
+ else if (8 == size) {SET_FLAGS_OSZAPC_LOGIC_8(result);} \
+ else VM_PANIC("unimplemented"); \
+}
+
+/* op1, op2, result */
+#define SET_FLAGS_OSZAPC_ADD_8(op1_8, op2_8, sum_8) \
+ SET_FLAGS_OSZAPC_8(ADD_COUT_VEC((op1_8), (op2_8), (sum_8)), (sum_8))
+#define SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16) \
+ SET_FLAGS_OSZAPC_16(ADD_COUT_VEC((op1_16), (op2_16), (sum_16)), (sum_16))
+#define SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32) \
+ SET_FLAGS_OSZAPC_32(ADD_COUT_VEC((op1_32), (op2_32), (sum_32)), (sum_32))
+
+/* op1, op2, result */
+#define SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8) \
+ SET_FLAGS_OSZAPC_8(SUB_COUT_VEC((op1_8), (op2_8), (diff_8)), (diff_8))
+#define SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16) \
+ SET_FLAGS_OSZAPC_16(SUB_COUT_VEC((op1_16), (op2_16), (diff_16)), (diff_16))
+#define SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32) \
+ SET_FLAGS_OSZAPC_32(SUB_COUT_VEC((op1_32), (op2_32), (diff_32)), (diff_32))
+
+// *******************
+// OSZAP
+// *******************
+/* size, carries, result */
+#define SET_FLAGS_OSZAP_SIZE(size, lf_carries, lf_result) { \
+ addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
+ (((lf_carries) >> (size - 2)) << LF_BIT_PO); \
+ if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
+ else VM_PANIC("unimplemented"); \
+ cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
+ addr_t delta_c = (cpu->hvf_x86->lflags.auxbits ^ temp) & LF_MASK_CF; \
+ delta_c ^= (delta_c >> 1); \
+ cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)(temp ^ delta_c); \
+}
+
+/* carries, result */
+#define SET_FLAGS_OSZAP_8(carries, result) \
+ SET_FLAGS_OSZAP_SIZE(8, carries, result)
+#define SET_FLAGS_OSZAP_16(carries, result) \
+ SET_FLAGS_OSZAP_SIZE(16, carries, result)
+#define SET_FLAGS_OSZAP_32(carries, result) \
+ SET_FLAGS_OSZAP_SIZE(32, carries, result)
+
+/* op1, op2, result */
+#define SET_FLAGS_OSZAP_ADD_8(op1_8, op2_8, sum_8) \
+ SET_FLAGS_OSZAP_8(ADD_COUT_VEC((op1_8), (op2_8), (sum_8)), (sum_8))
+#define SET_FLAGS_OSZAP_ADD_16(op1_16, op2_16, sum_16) \
+ SET_FLAGS_OSZAP_16(ADD_COUT_VEC((op1_16), (op2_16), (sum_16)), (sum_16))
+#define SET_FLAGS_OSZAP_ADD_32(op1_32, op2_32, sum_32) \
+ SET_FLAGS_OSZAP_32(ADD_COUT_VEC((op1_32), (op2_32), (sum_32)), (sum_32))
+
+/* op1, op2, result */
+#define SET_FLAGS_OSZAP_SUB_8(op1_8, op2_8, diff_8) \
+ SET_FLAGS_OSZAP_8(SUB_COUT_VEC((op1_8), (op2_8), (diff_8)), (diff_8))
+#define SET_FLAGS_OSZAP_SUB_16(op1_16, op2_16, diff_16) \
+ SET_FLAGS_OSZAP_16(SUB_COUT_VEC((op1_16), (op2_16), (diff_16)), (diff_16))
+#define SET_FLAGS_OSZAP_SUB_32(op1_32, op2_32, diff_32) \
+ SET_FLAGS_OSZAP_32(SUB_COUT_VEC((op1_32), (op2_32), (diff_32)), (diff_32))
+
+// *******************
+// OSZAxC
+// *******************
+/* size, carries, result */
+#define SET_FLAGS_OSZAxC_LOGIC_SIZE(size, lf_result) { \
+ bool saved_PF = getB_PF(); \
+ SET_FLAGS_OSZAPC_SIZE(size, (int##size##_t)(0), lf_result); \
+ set_PF(saved_PF); \
+}
+
+/* result */
+#define SET_FLAGS_OSZAxC_LOGIC_32(result_32) \
+ SET_FLAGS_OSZAxC_LOGIC_SIZE(32, (result_32))
+
+void lflags_to_rflags(struct CPUState *cpu);
+void rflags_to_lflags(struct CPUState *cpu);
+
+bool get_PF(struct CPUState *cpu);
+void set_PF(struct CPUState *cpu, bool val);
+bool get_CF(struct CPUState *cpu);
+void set_CF(struct CPUState *cpu, bool val);
+bool get_AF(struct CPUState *cpu);
+void set_AF(struct CPUState *cpu, bool val);
+bool get_ZF(struct CPUState *cpu);
+void set_ZF(struct CPUState *cpu, bool val);
+bool get_SF(struct CPUState *cpu);
+void set_SF(struct CPUState *cpu, bool val);
+bool get_OF(struct CPUState *cpu);
+void set_OF(struct CPUState *cpu, bool val);
+void set_OSZAPC(struct CPUState *cpu, uint32_t flags32);
+
+void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf);
+
+void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
+void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
+void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
+
+void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
+void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
+void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
+
+void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
+void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
+void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
+
+void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
+void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
+void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
+
+void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff);
+void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff);
+void SET_FLAGS_OSZAPC_LOGIC8(struct CPUState *cpu, uint8_t diff);
+
+void SET_FLAGS_SHR32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
+void SET_FLAGS_SHR16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
+void SET_FLAGS_SHR8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
+
+void SET_FLAGS_SAR32(struct CPUState *cpu, int32_t v, int count, uint32_t res);
+void SET_FLAGS_SAR16(struct CPUState *cpu, int16_t v, int count, uint16_t res);
+void SET_FLAGS_SAR8(struct CPUState *cpu, int8_t v, int count, uint8_t res);
+
+void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
+void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
+void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
+
+#endif /* __X86_FLAGS_H__ */
diff --git a/target/i386/hvf-utils/x86_gen.h b/target/i386/hvf-utils/x86_gen.h
new file mode 100644
index 0000000000..770ee80100
--- /dev/null
+++ b/target/i386/hvf-utils/x86_gen.h
@@ -0,0 +1,36 @@
+#ifndef __X86_GEN_H__
+#define __X86_GEN_H__
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "qemu-common.h"
+
+typedef uint64_t addr_t;
+
+#define VM_PANIC(x) {\
+ printf("%s\n", x); \
+ abort(); \
+}
+
+#define VM_PANIC_ON(x) {\
+ if (x) { \
+ printf("%s\n", #x); \
+ abort(); \
+ } \
+}
+
+#define VM_PANIC_EX(...) {\
+ printf(__VA_ARGS__); \
+ abort(); \
+}
+
+#define VM_PANIC_ON_EX(x, ...) {\
+ if (x) { \
+ printf(__VA_ARGS__); \
+ abort(); \
+ } \
+}
+
+#define ZERO_INIT(obj) memset((void *) &obj, 0, sizeof(obj))
+
+#endif
diff --git a/target/i386/hvf-utils/x86_mmu.c b/target/i386/hvf-utils/x86_mmu.c
new file mode 100644
index 0000000000..00fae735be
--- /dev/null
+++ b/target/i386/hvf-utils/x86_mmu.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+
+#include "qemu-common.h"
+#include "x86.h"
+#include "x86_mmu.h"
+#include "string.h"
+#include "vmcs.h"
+#include "vmx.h"
+
+#include "memory.h"
+#include "exec/address-spaces.h"
+
+#define pte_present(pte) (pte & PT_PRESENT)
+#define pte_write_access(pte) (pte & PT_WRITE)
+#define pte_user_access(pte) (pte & PT_USER)
+#define pte_exec_access(pte) (!(pte & PT_NX))
+
+#define pte_large_page(pte) (pte & PT_PS)
+#define pte_global_access(pte) (pte & PT_GLOBAL)
+
+#define PAE_CR3_MASK (~0x1fllu)
+#define LEGACY_CR3_MASK (0xffffffff)
+
+#define LEGACY_PTE_PAGE_MASK (0xffffffffllu << 12)
+#define PAE_PTE_PAGE_MASK ((-1llu << 12) & ((1llu << 52) - 1))
+#define PAE_PTE_LARGE_PAGE_MASK ((-1llu << (21)) & ((1llu << 52) - 1))
+
+struct gpt_translation {
+ addr_t gva;
+ addr_t gpa;
+ int err_code;
+ uint64_t pte[5];
+ bool write_access;
+ bool user_access;
+ bool exec_access;
+};
+
+static int gpt_top_level(struct CPUState *cpu, bool pae)
+{
+ if (!pae)
+ return 2;
+ if (x86_is_long_mode(cpu))
+ return 4;
+
+ return 3;
+}
+
+static inline int gpt_entry(addr_t addr, int level, bool pae)
+{
+ int level_shift = pae ? 9 : 10;
+ return (addr >> (level_shift * (level - 1) + 12)) & ((1 << level_shift) - 1);
+}
+
+static inline int pte_size(bool pae)
+{
+ return pae ? 8 : 4;
+}
+
+
+static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool pae)
+{
+ int index;
+ uint64_t pte = 0;
+ addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
+ addr_t gpa = pt->pte[level] & page_mask;
+
+ if (level == 3 && !x86_is_long_mode(cpu))
+ gpa = pt->pte[level];
+
+ index = gpt_entry(pt->gva, level, pae);
+ address_space_rw(&address_space_memory, gpa + index * pte_size(pae), MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0);
+
+ pt->pte[level - 1] = pte;
+
+ return true;
+}
+
+/* test page table entry */
+static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae)
+{
+ uint64_t pte = pt->pte[level];
+
+ if (pt->write_access)
+ pt->err_code |= MMU_PAGE_WT;
+ if (pt->user_access)
+ pt->err_code |= MMU_PAGE_US;
+ if (pt->exec_access)
+ pt->err_code |= MMU_PAGE_NX;
+
+ if (!pte_present(pte)) {
+ addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
+ return false;
+ }
+
+ if (pae && !x86_is_long_mode(cpu) && 2 == level)
+ goto exit;
+
+ if (1 == level && pte_large_page(pte)) {
+ pt->err_code |= MMU_PAGE_PT;
+ *is_large = true;
+ }
+ if (!level)
+ pt->err_code |= MMU_PAGE_PT;
+
+ addr_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
+ /* check protection */
+ if (cr0 & CR0_WP) {
+ if (pt->write_access && !pte_write_access(pte)) {
+ return false;
+ }
+ }
+
+ if (pt->user_access && !pte_user_access(pte)) {
+ return false;
+ }
+
+ if (pae && pt->exec_access && !pte_exec_access(pte)) {
+ return false;
+ }
+
+exit:
+ /* TODO: check reserved bits */
+ return true;
+}
+
+static inline uint64_t pse_pte_to_page(uint64_t pte)
+{
+ return ((pte & 0x1fe000) << 19) | (pte & 0xffc00000);
+}
+
+static inline uint64_t large_page_gpa(struct gpt_translation *pt, bool pae)
+{
+ VM_PANIC_ON(!pte_large_page(pt->pte[1]))
+ /* 2Mb large page */
+ if (pae)
+ return (pt->pte[1] & PAE_PTE_LARGE_PAGE_MASK) | (pt->gva & 0x1fffff);
+
+ /* 4Mb large page */
+ return pse_pte_to_page(pt->pte[1]) | (pt->gva & 0x3fffff);
+}
+
+
+
+static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code, struct gpt_translation* pt, bool pae)
+{
+ int top_level, level;
+ bool is_large = false;
+ addr_t cr3 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3);
+ addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
+
+ memset(pt, 0, sizeof(*pt));
+ top_level = gpt_top_level(cpu, pae);
+
+ pt->pte[top_level] = pae ? (cr3 & PAE_CR3_MASK) : (cr3 & LEGACY_CR3_MASK);
+ pt->gva = addr;
+ pt->user_access = (err_code & MMU_PAGE_US);
+ pt->write_access = (err_code & MMU_PAGE_WT);
+ pt->exec_access = (err_code & MMU_PAGE_NX);
+
+ for (level = top_level; level > 0; level--) {
+ get_pt_entry(cpu, pt, level, pae);
+
+ if (!test_pt_entry(cpu, pt, level - 1, &is_large, pae)) {
+ return false;
+ }
+
+ if (is_large)
+ break;
+ }
+
+ if (!is_large)
+ pt->gpa = (pt->pte[0] & page_mask) | (pt->gva & 0xfff);
+ else
+ pt->gpa = large_page_gpa(pt, pae);
+
+ return true;
+}
+
+
+bool mmu_gva_to_gpa(struct CPUState *cpu, addr_t gva, addr_t *gpa)
+{
+ bool res;
+ struct gpt_translation pt;
+ int err_code = 0;
+
+ if (!x86_is_paging_mode(cpu)) {
+ *gpa = gva;
+ return true;
+ }
+
+ res = walk_gpt(cpu, gva, err_code, &pt, x86_is_pae_enabled(cpu));
+ if (res) {
+ *gpa = pt.gpa;
+ return true;
+ }
+
+ return false;
+}
+
+void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes)
+{
+ addr_t gpa;
+
+ while (bytes > 0) {
+ // copy page
+ int copy = MIN(bytes, 0x1000 - (gva & 0xfff));
+
+ if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
+ } else {
+ address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 1);
+ }
+
+ bytes -= copy;
+ gva += copy;
+ data += copy;
+ }
+}
+
+void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes)
+{
+ addr_t gpa;
+
+ while (bytes > 0) {
+ // copy page
+ int copy = MIN(bytes, 0x1000 - (gva & 0xfff));
+
+ if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
+ }
+ address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 0);
+
+ bytes -= copy;
+ gva += copy;
+ data += copy;
+ }
+}
diff --git a/target/i386/hvf-utils/x86_mmu.h b/target/i386/hvf-utils/x86_mmu.h
new file mode 100644
index 0000000000..c31bf28982
--- /dev/null
+++ b/target/i386/hvf-utils/x86_mmu.h
@@ -0,0 +1,28 @@
+#ifndef __X86_MMU_H__
+#define __X86_MMU_H__
+
+#include "x86_gen.h"
+
+#define PT_PRESENT (1 << 0)
+#define PT_WRITE (1 << 1)
+#define PT_USER (1 << 2)
+#define PT_WT (1 << 3)
+#define PT_CD (1 << 4)
+#define PT_ACCESSED (1 << 5)
+#define PT_DIRTY (1 << 6)
+#define PT_PS (1 << 7)
+#define PT_GLOBAL (1 << 8)
+#define PT_NX (1llu << 63)
+
+// error codes
+#define MMU_PAGE_PT (1 << 0)
+#define MMU_PAGE_WT (1 << 1)
+#define MMU_PAGE_US (1 << 2)
+#define MMU_PAGE_NX (1 << 3)
+
+bool mmu_gva_to_gpa(struct CPUState *cpu, addr_t gva, addr_t *gpa);
+
+void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes);
+void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes);
+
+#endif /* __X86_MMU_H__ */
diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c
new file mode 100644
index 0000000000..d5668df37f
--- /dev/null
+++ b/target/i386/hvf-utils/x86hvf.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (C) 2016 Veertu Inc,
+ * Copyright (C) 2017 Google Inc,
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+
+#include "x86hvf.h"
+#include "vmx.h"
+#include "vmcs.h"
+#include "cpu.h"
+#include "x86_descr.h"
+#include "x86_decode.h"
+
+#include "hw/i386/apic_internal.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <Hypervisor/hv.h>
+#include <Hypervisor/hv_vmx.h>
+#include <stdint.h>
+
+void hvf_cpu_synchronize_state(struct CPUState* cpu_state);
+
+void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr)
+{
+ vmx_seg->sel = qseg->selector;
+ vmx_seg->base = qseg->base;
+ vmx_seg->limit = qseg->limit;
+
+ if (!qseg->selector && !x86_is_real(cpu) && !is_tr) {
+ // the TR register is usable after processor reset despite having a null selector
+ vmx_seg->ar = 1 << 16;
+ return;
+ }
+ vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf;
+ vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15;
+ vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14;
+ vmx_seg->ar |= ((qseg->flags >> DESC_L_SHIFT) & 1) << 13;
+ vmx_seg->ar |= ((qseg->flags >> DESC_AVL_SHIFT) & 1) << 12;
+ vmx_seg->ar |= ((qseg->flags >> DESC_P_SHIFT) & 1) << 7;
+ vmx_seg->ar |= ((qseg->flags >> DESC_DPL_SHIFT) & 3) << 5;
+ vmx_seg->ar |= ((qseg->flags >> DESC_S_SHIFT) & 1) << 4;
+}
+
+void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg)
+{
+ qseg->limit = vmx_seg->limit;
+ qseg->base = vmx_seg->base;
+ qseg->selector = vmx_seg->sel;
+ qseg->flags = ((vmx_seg->ar & 0xf) << DESC_TYPE_SHIFT) |
+ (((vmx_seg->ar >> 4) & 1) << DESC_S_SHIFT) |
+ (((vmx_seg->ar >> 5) & 3) << DESC_DPL_SHIFT) |
+ (((vmx_seg->ar >> 7) & 1) << DESC_P_SHIFT) |
+ (((vmx_seg->ar >> 12) & 1) << DESC_AVL_SHIFT) |
+ (((vmx_seg->ar >> 13) & 1) << DESC_L_SHIFT) |
+ (((vmx_seg->ar >> 14) & 1) << DESC_B_SHIFT) |
+ (((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT);
+}
+
+void hvf_put_xsave(CPUState *cpu_state)
+{
+
+ int x;
+ struct hvf_xsave_buf *xsave;
+
+ xsave = X86_CPU(cpu_state)->env.kvm_xsave_buf;
+ memset(xsave, 0, sizeof(*xsave));
+
+ memcpy(&xsave->data[4], &X86_CPU(cpu_state)->env.fpdp, sizeof(X86_CPU(cpu_state)->env.fpdp));
+ memcpy(&xsave->data[2], &X86_CPU(cpu_state)->env.fpip, sizeof(X86_CPU(cpu_state)->env.fpip));
+ memcpy(&xsave->data[8], &X86_CPU(cpu_state)->env.fpregs, sizeof(X86_CPU(cpu_state)->env.fpregs));
+ memcpy(&xsave->data[144], &X86_CPU(cpu_state)->env.ymmh_regs, sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
+ memcpy(&xsave->data[288], &X86_CPU(cpu_state)->env.zmmh_regs, sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
+ memcpy(&xsave->data[272], &X86_CPU(cpu_state)->env.opmask_regs, sizeof(X86_CPU(cpu_state)->env.opmask_regs));
+ memcpy(&xsave->data[240], &X86_CPU(cpu_state)->env.bnd_regs, sizeof(X86_CPU(cpu_state)->env.bnd_regs));
+ memcpy(&xsave->data[256], &X86_CPU(cpu_state)->env.bndcs_regs, sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
+ memcpy(&xsave->data[416], &X86_CPU(cpu_state)->env.hi16_zmm_regs, sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
+
+ xsave->data[0] = (uint16_t)X86_CPU(cpu_state)->env.fpuc;
+ xsave->data[0] |= (X86_CPU(cpu_state)->env.fpus << 16);
+ xsave->data[0] |= (X86_CPU(cpu_state)->env.fpstt & 7) << 11;
+
+ for (x = 0; x < 8; ++x)
+ xsave->data[1] |= ((!X86_CPU(cpu_state)->env.fptags[x]) << x);
+ xsave->data[1] |= (uint32_t)(X86_CPU(cpu_state)->env.fpop << 16);
+
+ memcpy(&xsave->data[40], &X86_CPU(cpu_state)->env.xmm_regs, sizeof(X86_CPU(cpu_state)->env.xmm_regs));
+
+ xsave->data[6] = X86_CPU(cpu_state)->env.mxcsr;
+ *(uint64_t *)&xsave->data[128] = X86_CPU(cpu_state)->env.xstate_bv;
+
+ if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, xsave->data, 4096)){
+ abort();
+ }
+}
+
+void vmx_update_tpr(CPUState *cpu);
+void hvf_put_segments(CPUState *cpu_state)
+{
+ CPUX86State *env = &X86_CPU(cpu_state)->env;
+ struct vmx_segment seg;
+
+ wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
+ wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
+
+ wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
+ wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
+
+ //wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]);
+ wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]);
+ vmx_update_tpr(cpu_state);
+ wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer);
+
+ macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]);
+ macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]);
+
+ hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_CS);
+
+ hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_DS);
+
+ hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_ES);
+
+ hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_SS);
+
+ hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_FS);
+
+ hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_GS);
+
+ hvf_set_segment(cpu_state, &seg, &env->tr, true);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_TR);
+
+ hvf_set_segment(cpu_state, &seg, &env->ldt, false);
+ vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR);
+
+ hv_vcpu_flush(cpu_state->hvf_fd);
+}
+
+void hvf_put_msrs(CPUState *cpu_state)
+{
+ CPUX86State *env = &X86_CPU(cpu_state)->env;
+
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
+
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star);
+
+#ifdef TARGET_X86_64
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_CSTAR, env->cstar);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, env->kernelgsbase);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FMASK, env->fmask);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_LSTAR, env->lstar);
+#endif
+
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base);
+
+ // if (!osx_is_sierra())
+ // wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());
+ hv_vm_sync_tsc(env->tsc);
+}
+
+
+void hvf_get_xsave(CPUState *cpu_state)
+{
+ int x;
+ struct hvf_xsave_buf *xsave;
+
+ xsave = X86_CPU(cpu_state)->env.kvm_xsave_buf;
+
+ if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, xsave->data, 4096)) {
+ abort();
+ }
+
+ memcpy(&X86_CPU(cpu_state)->env.fpdp, &xsave->data[4], sizeof(X86_CPU(cpu_state)->env.fpdp));
+ memcpy(&X86_CPU(cpu_state)->env.fpip, &xsave->data[2], sizeof(X86_CPU(cpu_state)->env.fpip));
+ memcpy(&X86_CPU(cpu_state)->env.fpregs, &xsave->data[8], sizeof(X86_CPU(cpu_state)->env.fpregs));
+ memcpy(&X86_CPU(cpu_state)->env.ymmh_regs, &xsave->data[144], sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
+ memcpy(&X86_CPU(cpu_state)->env.zmmh_regs, &xsave->data[288], sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
+ memcpy(&X86_CPU(cpu_state)->env.opmask_regs, &xsave->data[272], sizeof(X86_CPU(cpu_state)->env.opmask_regs));
+ memcpy(&X86_CPU(cpu_state)->env.bnd_regs, &xsave->data[240], sizeof(X86_CPU(cpu_state)->env.bnd_regs));
+ memcpy(&X86_CPU(cpu_state)->env.bndcs_regs, &xsave->data[256], sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
+ memcpy(&X86_CPU(cpu_state)->env.hi16_zmm_regs, &xsave->data[416], sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
+
+
+ X86_CPU(cpu_state)->env.fpuc = (uint16_t)xsave->data[0];
+ X86_CPU(cpu_state)->env.fpus = (uint16_t)(xsave->data[0] >> 16);
+ X86_CPU(cpu_state)->env.fpstt = (X86_CPU(cpu_state)->env.fpus >> 11) & 7;
+ X86_CPU(cpu_state)->env.fpop = (uint16_t)(xsave->data[1] >> 16);
+
+ for (x = 0; x < 8; ++x)
+ X86_CPU(cpu_state)->env.fptags[x] =
+ ((((uint16_t)xsave->data[1] >> x) & 1) == 0);
+
+ memcpy(&X86_CPU(cpu_state)->env.xmm_regs, &xsave->data[40], sizeof(X86_CPU(cpu_state)->env.xmm_regs));
+
+ X86_CPU(cpu_state)->env.mxcsr = xsave->data[6];
+ X86_CPU(cpu_state)->env.xstate_bv = *(uint64_t *)&xsave->data[128];
+}
+
+void hvf_get_segments(CPUState *cpu_state)
+{
+ CPUX86State *env = &X86_CPU(cpu_state)->env;
+
+ struct vmx_segment seg;
+
+ env->interrupt_injected = -1;
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_CS);
+ hvf_get_segment(&env->segs[R_CS], &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_DS);
+ hvf_get_segment(&env->segs[R_DS], &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_ES);
+ hvf_get_segment(&env->segs[R_ES], &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_FS);
+ hvf_get_segment(&env->segs[R_FS], &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_GS);
+ hvf_get_segment(&env->segs[R_GS], &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_SS);
+ hvf_get_segment(&env->segs[R_SS], &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_TR);
+ hvf_get_segment(&env->tr, &seg);
+
+ vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR);
+ hvf_get_segment(&env->ldt, &seg);
+
+ env->idt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT);
+ env->idt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE);
+ env->gdt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
+ env->gdt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE);
+
+ env->cr[0] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR0);
+ env->cr[2] = 0;
+ env->cr[3] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3);
+ env->cr[4] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4);
+
+ env->efer = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER);
+}
+
+void hvf_get_msrs(CPUState *cpu_state)
+{
+ CPUX86State *env = &X86_CPU(cpu_state)->env;
+ uint64_t tmp;
+
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp);
+ env->sysenter_cs = tmp;
+
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp);
+ env->sysenter_esp = tmp;
+
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, &tmp);
+ env->sysenter_eip = tmp;
+
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_STAR, &env->star);
+
+#ifdef TARGET_X86_64
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_CSTAR, &env->cstar);
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, &env->kernelgsbase);
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_FMASK, &env->fmask);
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_LSTAR, &env->lstar);
+#endif
+
+ hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp);
+
+ env->tsc = rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET);
+}
+
+int hvf_put_registers(CPUState *cpu_state)
+{
+ X86CPU *x86cpu = X86_CPU(cpu_state);
+ CPUX86State *env = &x86cpu->env;
+
+ wreg(cpu_state->hvf_fd, HV_X86_RAX, env->regs[R_EAX]);
+ wreg(cpu_state->hvf_fd, HV_X86_RBX, env->regs[R_EBX]);
+ wreg(cpu_state->hvf_fd, HV_X86_RCX, env->regs[R_ECX]);
+ wreg(cpu_state->hvf_fd, HV_X86_RDX, env->regs[R_EDX]);
+ wreg(cpu_state->hvf_fd, HV_X86_RBP, env->regs[R_EBP]);
+ wreg(cpu_state->hvf_fd, HV_X86_RSP, env->regs[R_ESP]);
+ wreg(cpu_state->hvf_fd, HV_X86_RSI, env->regs[R_ESI]);
+ wreg(cpu_state->hvf_fd, HV_X86_RDI, env->regs[R_EDI]);
+ wreg(cpu_state->hvf_fd, HV_X86_R8, env->regs[8]);
+ wreg(cpu_state->hvf_fd, HV_X86_R9, env->regs[9]);
+ wreg(cpu_state->hvf_fd, HV_X86_R10, env->regs[10]);
+ wreg(cpu_state->hvf_fd, HV_X86_R11, env->regs[11]);
+ wreg(cpu_state->hvf_fd, HV_X86_R12, env->regs[12]);
+ wreg(cpu_state->hvf_fd, HV_X86_R13, env->regs[13]);
+ wreg(cpu_state->hvf_fd, HV_X86_R14, env->regs[14]);
+ wreg(cpu_state->hvf_fd, HV_X86_R15, env->regs[15]);
+ wreg(cpu_state->hvf_fd, HV_X86_RFLAGS, env->eflags);
+ wreg(cpu_state->hvf_fd, HV_X86_RIP, env->eip);
+
+ wreg(cpu_state->hvf_fd, HV_X86_XCR0, env->xcr0);
+
+ hvf_put_xsave(cpu_state);
+
+ hvf_put_segments(cpu_state);
+
+ hvf_put_msrs(cpu_state);
+
+ wreg(cpu_state->hvf_fd, HV_X86_DR0, env->dr[0]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR1, env->dr[1]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR2, env->dr[2]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR3, env->dr[3]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR4, env->dr[4]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR5, env->dr[5]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR6, env->dr[6]);
+ wreg(cpu_state->hvf_fd, HV_X86_DR7, env->dr[7]);
+
+ return 0;
+}
+
+int hvf_get_registers(CPUState *cpu_state)
+{
+ X86CPU *x86cpu = X86_CPU(cpu_state);
+ CPUX86State *env = &x86cpu->env;
+
+
+ env->regs[R_EAX] = rreg(cpu_state->hvf_fd, HV_X86_RAX);
+ env->regs[R_EBX] = rreg(cpu_state->hvf_fd, HV_X86_RBX);
+ env->regs[R_ECX] = rreg(cpu_state->hvf_fd, HV_X86_RCX);
+ env->regs[R_EDX] = rreg(cpu_state->hvf_fd, HV_X86_RDX);
+ env->regs[R_EBP] = rreg(cpu_state->hvf_fd, HV_X86_RBP);
+ env->regs[R_ESP] = rreg(cpu_state->hvf_fd, HV_X86_RSP);
+ env->regs[R_ESI] = rreg(cpu_state->hvf_fd, HV_X86_RSI);
+ env->regs[R_EDI] = rreg(cpu_state->hvf_fd, HV_X86_RDI);
+ env->regs[8] = rreg(cpu_state->hvf_fd, HV_X86_R8);
+ env->regs[9] = rreg(cpu_state->hvf_fd, HV_X86_R9);
+ env->regs[10] = rreg(cpu_state->hvf_fd, HV_X86_R10);
+ env->regs[11] = rreg(cpu_state->hvf_fd, HV_X86_R11);
+ env->regs[12] = rreg(cpu_state->hvf_fd, HV_X86_R12);
+ env->regs[13] = rreg(cpu_state->hvf_fd, HV_X86_R13);
+ env->regs[14] = rreg(cpu_state->hvf_fd, HV_X86_R14);
+ env->regs[15] = rreg(cpu_state->hvf_fd, HV_X86_R15);
+
+ env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
+ env->eip = rreg(cpu_state->hvf_fd, HV_X86_RIP);
+
+ hvf_get_xsave(cpu_state);
+ env->xcr0 = rreg(cpu_state->hvf_fd, HV_X86_XCR0);
+
+ hvf_get_segments(cpu_state);
+ hvf_get_msrs(cpu_state);
+
+ env->dr[0] = rreg(cpu_state->hvf_fd, HV_X86_DR0);
+ env->dr[1] = rreg(cpu_state->hvf_fd, HV_X86_DR1);
+ env->dr[2] = rreg(cpu_state->hvf_fd, HV_X86_DR2);
+ env->dr[3] = rreg(cpu_state->hvf_fd, HV_X86_DR3);
+ env->dr[4] = rreg(cpu_state->hvf_fd, HV_X86_DR4);
+ env->dr[5] = rreg(cpu_state->hvf_fd, HV_X86_DR5);
+ env->dr[6] = rreg(cpu_state->hvf_fd, HV_X86_DR6);
+ env->dr[7] = rreg(cpu_state->hvf_fd, HV_X86_DR7);
+
+ return 0;
+}
+
+static void vmx_set_int_window_exiting(CPUState *cpu)
+{
+ uint64_t val;
+ val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
+}
+
+void vmx_clear_int_window_exiting(CPUState *cpu)
+{
+ uint64_t val;
+ val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
+}
+
+#define NMI_VEC 2
+
+void hvf_inject_interrupts(CPUState *cpu_state)
+{
+ X86CPU *x86cpu = X86_CPU(cpu_state);
+ int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
+
+ uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);
+ uint64_t info = 0;
+
+ if (idt_info & VMCS_IDT_VEC_VALID) {
+ uint8_t vector = idt_info & 0xff;
+ uint64_t intr_type = idt_info & VMCS_INTR_T_MASK;
+ info = idt_info;
+
+ uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON);
+ if (intr_type == VMCS_INTR_T_NMI && reason != EXIT_REASON_TASK_SWITCH) {
+ allow_nmi = 1;
+ vmx_clear_nmi_blocking(cpu_state);
+ }
+
+ if ((allow_nmi || intr_type != VMCS_INTR_T_NMI)) {
+ info &= ~(1 << 12); /* clear undefined bit */
+ if (intr_type == VMCS_INTR_T_SWINTR ||
+ intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||
+ intr_type == VMCS_INTR_T_SWEXCEPTION) {
+ uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
+ }
+ if (vector == EXCEPTION_BP || vector == EXCEPTION_OF) {
+ /*
+ * VT-x requires #BP and #OF to be injected as software
+ * exceptions.
+ */
+ info &= ~VMCS_INTR_T_MASK;
+ info |= VMCS_INTR_T_SWEXCEPTION;
+ uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
+ }
+
+ uint64_t err = 0;
+ if (idt_info & VMCS_INTR_DEL_ERRCODE) {
+ err = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR);
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err);
+ }
+ //printf("reinject %lx err %d\n", info, err);
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
+ };
+ }
+
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {
+ if (allow_nmi && !(info & VMCS_INTR_VALID)) {
+ cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | NMI_VEC;
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
+ } else {
+ vmx_set_nmi_window_exiting(cpu_state);
+ }
+ }
+
+ if (cpu_state->hvf_x86->interruptable && (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (EFLAGS(cpu_state) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
+ int line = cpu_get_pic_interrupt(&x86cpu->env);
+ cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ if (line >= 0)
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
+ }
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD)
+ vmx_set_int_window_exiting(cpu_state);
+}
+
+int hvf_process_events(CPUState *cpu_state)
+{
+ X86CPU *cpu = X86_CPU(cpu_state);
+ CPUX86State *env = &cpu->env;
+
+ EFLAGS(cpu_state) = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
+
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
+ hvf_cpu_synchronize_state(cpu_state);
+ do_cpu_init(cpu);
+ }
+
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) {
+ cpu_state->interrupt_request &= ~CPU_INTERRUPT_POLL;
+ apic_poll_irq(cpu->apic_state);
+ }
+ if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu_state) & IF_MASK)) ||
+ (cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) {
+ cpu_state->halted = 0;
+ }
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) {
+ hvf_cpu_synchronize_state(cpu_state);
+ do_cpu_sipi(cpu);
+ }
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) {
+ cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR;
+ hvf_cpu_synchronize_state(cpu_state);
+ apic_handle_tpr_access_report(cpu->apic_state, env->eip,
+ env->tpr_access_type);
+ }
+ return cpu_state->halted;
+}
+
diff --git a/target/i386/hvf-utils/x86hvf.h b/target/i386/hvf-utils/x86hvf.h
new file mode 100644
index 0000000000..b4cb4c4d26
--- /dev/null
+++ b/target/i386/hvf-utils/x86hvf.h
@@ -0,0 +1,19 @@
+#ifndef X86HVF_H
+#define X86HVF_H
+#include "cpu.h"
+#include "x86_descr.h"
+
+int hvf_process_events(CPUState *);
+int hvf_put_registers(CPUState *);
+int hvf_get_registers(CPUState *);
+void hvf_inject_interrupts(CPUState *);
+void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr);
+void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg);
+void hvf_put_xsave(CPUState *cpu_state);
+void hvf_put_segments(CPUState *cpu_state);
+void hvf_put_msrs(CPUState *cpu_state);
+void hvf_get_xsave(CPUState *cpu_state);
+void hvf_get_msrs(CPUState *cpu_state);
+void vmx_clear_int_window_exiting(CPUState *cpu);
+void hvf_get_segments(CPUState *cpu_state);
+#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 03/14] hvf: add conditional macros around hvf code in cpus.c
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:19 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 04/14] hvf: add fields to CPUState and CPUX86State; add definitions Sergio Andres Gomez Del Real
` (13 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit surrounds the hvf parts of cpus.c with conditional macros so
that they are rightly ignored on other platforms.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
cpus.c | 147 +++++++++++++++++++++++++++++++++++----------------
include/sysemu/hvf.h | 5 +-
2 files changed, 105 insertions(+), 47 deletions(-)
diff --git a/cpus.c b/cpus.c
index a2cd9dfa5d..6754ce17cc 100644
--- a/cpus.c
+++ b/cpus.c
@@ -37,6 +37,7 @@
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
#include "sysemu/hax.h"
+#include "sysemu/hvf.h"
#include "qmp-commands.h"
#include "exec/exec-all.h"
@@ -81,6 +82,9 @@ static unsigned int throttle_percentage;
#define CPU_THROTTLE_PCT_MAX 99
#define CPU_THROTTLE_TIMESLICE_NS 10000000
+/* For temporary buffers for forming a name */
+#define VCPU_THREAD_NAME_SIZE 16
+
bool cpu_is_stopped(CPUState *cpu)
{
return cpu->stopped || !runstate_is_running();
@@ -900,6 +904,11 @@ void cpu_synchronize_all_states(void)
CPU_FOREACH(cpu) {
cpu_synchronize_state(cpu);
+#ifdef CONFIG_HVF
+ if (hvf_enabled()) {
+ hvf_cpu_synchronize_state(cpu);
+ }
+#endif
}
}
@@ -909,6 +918,11 @@ void cpu_synchronize_all_post_reset(void)
CPU_FOREACH(cpu) {
cpu_synchronize_post_reset(cpu);
+#ifdef CONFIG_HVF
+ if (hvf_enabled()) {
+ hvf_cpu_synchronize_post_reset(cpu);
+ }
+#endif
}
}
@@ -918,6 +932,11 @@ void cpu_synchronize_all_post_init(void)
CPU_FOREACH(cpu) {
cpu_synchronize_post_init(cpu);
+#ifdef CONFIG_HVF
+ if (hvf_enabled()) {
+ hvf_cpu_synchronize_post_init(cpu);
+ }
+#endif
}
}
@@ -1098,6 +1117,80 @@ static void qemu_kvm_wait_io_event(CPUState *cpu)
qemu_wait_io_event_common(cpu);
}
+#ifdef CONFIG_HVF
+static void qemu_hvf_wait_io_event(CPUState *cpu)
+{
+ while (cpu_thread_is_idle(cpu)) {
+ qemu_cond_wait(cpu->halt_cond, &qemu_global_mutex);
+ }
+ qemu_wait_io_event_common(cpu);
+}
+
+/* The HVF-specific vCPU thread function. This one should only run when the host
+ * CPU supports the VMX "unrestricted guest" feature. */
+static void *qemu_hvf_cpu_thread_fn(void *arg)
+{
+ CPUState *cpu = arg;
+
+ int r;
+
+ assert(hvf_enabled());
+
+ rcu_register_thread();
+
+ qemu_mutex_lock_iothread();
+ qemu_thread_get_self(cpu->thread);
+
+ cpu->thread_id = qemu_get_thread_id();
+ cpu->can_do_io = 1;
+ current_cpu = cpu;
+
+ hvf_init_vcpu(cpu);
+
+ /* signal CPU creation */
+ cpu->created = true;
+ qemu_cond_signal(&qemu_cpu_cond);
+
+ do {
+ if (cpu_can_run(cpu)) {
+ r = hvf_vcpu_exec(cpu);
+ if (r == EXCP_DEBUG) {
+ cpu_handle_guest_debug(cpu);
+ }
+ }
+ qemu_hvf_wait_io_event(cpu);
+ } while (!cpu->unplug || cpu_can_run(cpu));
+
+ hvf_vcpu_destroy(cpu);
+ cpu->created = false;
+ qemu_cond_signal(&qemu_cpu_cond);
+ qemu_mutex_unlock_iothread();
+ return NULL;
+}
+
+static void qemu_hvf_start_vcpu(CPUState *cpu)
+{
+ char thread_name[VCPU_THREAD_NAME_SIZE];
+
+ /* HVF currently does not support TCG, and only runs in
+ * unrestricted-guest mode. */
+ assert(hvf_enabled());
+
+ cpu->thread = g_malloc0(sizeof(QemuThread));
+ cpu->halt_cond = g_malloc0(sizeof(QemuCond));
+ qemu_cond_init(cpu->halt_cond);
+
+ snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/HVF",
+ cpu->cpu_index);
+ qemu_thread_create(cpu->thread, thread_name, qemu_hvf_cpu_thread_fn,
+ cpu, QEMU_THREAD_JOINABLE);
+ while (!cpu->created) {
+ qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex);
+ }
+}
+
+#endif
+
static void *qemu_kvm_cpu_thread_fn(void *arg)
{
CPUState *cpu = arg;
@@ -1434,48 +1527,6 @@ static void *qemu_hax_cpu_thread_fn(void *arg)
return NULL;
}
-/* The HVF-specific vCPU thread function. This one should only run when the host
- * CPU supports the VMX "unrestricted guest" feature. */
-static void *qemu_hvf_cpu_thread_fn(void *arg)
-{
- CPUState *cpu = arg;
-
- int r;
-
- assert(hvf_enabled());
-
- rcu_register_thread();
-
- qemu_mutex_lock_iothread();
- qemu_thread_get_self(cpu->thread);
-
- cpu->thread_id = qemu_get_thread_id();
- cpu->can_do_io = 1;
- current_cpu = cpu;
-
- hvf_init_vcpu(cpu);
-
- /* signal CPU creation */
- cpu->created = true;
- qemu_cond_signal(&qemu_cpu_cond);
-
- do {
- if (cpu_can_run(cpu)) {
- r = hvf_vcpu_exec(cpu);
- if (r == EXCP_DEBUG) {
- cpu_handle_guest_debug(cpu);
- }
- }
- qemu_hvf_wait_io_event(cpu);
- } while (!cpu->unplug || cpu_can_run(cpu));
-
- hvf_vcpu_destroy(cpu);
- cpu->created = false;
- qemu_cond_signal(&qemu_cpu_cond);
- qemu_mutex_unlock_iothread();
- return NULL;
-}
-
#ifdef _WIN32
static void CALLBACK dummy_apc_func(ULONG_PTR unused)
{
@@ -1564,6 +1615,11 @@ static void qemu_cpu_kick_thread(CPUState *cpu)
fprintf(stderr, "qemu:%s: %s", __func__, strerror(err));
exit(1);
}
+#ifdef CONFIG_HVF
+ if (hvf_enabled()) {
+ cpu_exit(cpu);
+ }
+#endif
#else /* _WIN32 */
if (!qemu_cpu_is_self(cpu)) {
if (!QueueUserAPC(dummy_apc_func, cpu->hThread, 0)) {
@@ -1698,9 +1754,6 @@ void cpu_remove_sync(CPUState *cpu)
}
}
-/* For temporary buffers for forming a name */
-#define VCPU_THREAD_NAME_SIZE 16
-
static void qemu_tcg_init_vcpu(CPUState *cpu)
{
char thread_name[VCPU_THREAD_NAME_SIZE];
@@ -1816,6 +1869,10 @@ void qemu_init_vcpu(CPUState *cpu)
qemu_kvm_start_vcpu(cpu);
} else if (hax_enabled()) {
qemu_hax_start_vcpu(cpu);
+#ifdef CONFIG_HVF
+ } else if (hvf_enabled()) {
+ qemu_hvf_start_vcpu(cpu);
+#endif
} else if (tcg_enabled()) {
qemu_tcg_init_vcpu(cpu);
} else {
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index b96bd5e8ba..5e2b5f8f76 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -20,10 +20,12 @@
#include "qemu/bitops.h"
#include "exec/memory.h"
#include "sysemu/accel.h"
+
+#ifdef CONFIG_HVF
#include <Hypervisor/hv.h>
#include <Hypervisor/hv_vmx.h>
#include <Hypervisor/hv_error.h>
-
+#endif
typedef struct hvf_slot {
uint64_t start;
@@ -85,7 +87,6 @@ void __hvf_cpu_synchronize_state(CPUState *, run_on_cpu_data);
void __hvf_cpu_synchronize_post_reset(CPUState *, run_on_cpu_data);
void vmx_update_tpr(CPUState *);
void update_apic_tpr(CPUState *);
-int apic_get_highest_priority_irr(DeviceState *);
int hvf_put_registers(CPUState *);
#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 04/14] hvf: add fields to CPUState and CPUX86State; add definitions
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (2 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 03/14] hvf: add conditional macros around hvf code in cpus.c Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:31 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 05/14] hvf: use new helper functions for put/get xsave Sergio Andres Gomez Del Real
` (12 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit adds some fields specific to hvf in CPUState and
CPUX86State. It also adds some handy #defines.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
include/qom/cpu.h | 8 ++++++++
target/i386/cpu.h | 23 +++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 25eefea7ab..c46eb61240 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -407,6 +407,14 @@ struct CPUState {
* unnecessary flushes.
*/
uint16_t pending_tlb_flush;
+
+ // HVF
+ bool hvf_vcpu_dirty;
+ uint64_t hvf_fd; // fd of vcpu created by HVF
+ // Supporting data structures for VMCS capabilities
+ // and x86 emulation state
+ struct hvf_vcpu_caps* hvf_caps;
+ struct hvf_x86_state* hvf_x86;
};
QTAILQ_HEAD(CPUTailQ, CPUState);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 051867399b..7d90f08b98 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -82,15 +82,19 @@
#define R_GS 5
/* segment descriptor fields */
+#define DESC_G_SHIFT 23
#define DESC_G_MASK (1 << 23)
#define DESC_B_SHIFT 22
#define DESC_B_MASK (1 << DESC_B_SHIFT)
#define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
#define DESC_L_MASK (1 << DESC_L_SHIFT)
+#define DESC_AVL_SHIFT 20
#define DESC_AVL_MASK (1 << 20)
+#define DESC_P_SHIFT 15
#define DESC_P_MASK (1 << 15)
#define DESC_DPL_SHIFT 13
#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
+#define DESC_S_SHIFT 12
#define DESC_S_MASK (1 << 12)
#define DESC_TYPE_SHIFT 8
#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
@@ -631,6 +635,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
+#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
#define CPUID_7_0_ECX_UMIP (1U << 2)
#define CPUID_7_0_ECX_PKU (1U << 3)
@@ -806,6 +811,20 @@ typedef struct SegmentCache {
float64 _d_##n[(bits)/64]; \
}
+typedef union {
+ uint8_t _b[16];
+ uint16_t _w[8];
+ uint32_t _l[4];
+ uint64_t _q[2];
+} XMMReg;
+
+typedef union {
+ uint8_t _b[32];
+ uint16_t _w[16];
+ uint32_t _l[8];
+ uint64_t _q[4];
+} YMMReg;
+
typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
typedef MMREG_UNION(MMXReg, 64) MMXReg;
@@ -1041,7 +1060,11 @@ typedef struct CPUX86State {
ZMMReg xmm_t0;
MMXReg mmx_t0;
+ XMMReg ymmh_regs[CPU_NB_REGS];
+
uint64_t opmask_regs[NB_OPMASK_REGS];
+ YMMReg zmmh_regs[CPU_NB_REGS];
+ ZMMReg hi16_zmm_regs[CPU_NB_REGS];
/* sysenter registers */
uint32_t sysenter_cs;
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 05/14] hvf: use new helper functions for put/get xsave
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (3 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 04/14] hvf: add fields to CPUState and CPUX86State; add definitions Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 06/14] hvf: add compilation rules to Makefile.objs Sergio Andres Gomez Del Real
` (11 subsequent siblings)
16 siblings, 0 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit makes use of the helper functions for handling xsave in
xsave_helper.c, which are shared with kvm.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
target/i386/hvf-utils/x86hvf.c | 63 ++++++------------------------------------
1 file changed, 8 insertions(+), 55 deletions(-)
diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c
index d5668df37f..5c1d5ece36 100644
--- a/target/i386/hvf-utils/x86hvf.c
+++ b/target/i386/hvf-utils/x86hvf.c
@@ -76,36 +76,13 @@ void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg)
void hvf_put_xsave(CPUState *cpu_state)
{
- int x;
struct hvf_xsave_buf *xsave;
-
+
xsave = X86_CPU(cpu_state)->env.kvm_xsave_buf;
- memset(xsave, 0, sizeof(*xsave));
-
- memcpy(&xsave->data[4], &X86_CPU(cpu_state)->env.fpdp, sizeof(X86_CPU(cpu_state)->env.fpdp));
- memcpy(&xsave->data[2], &X86_CPU(cpu_state)->env.fpip, sizeof(X86_CPU(cpu_state)->env.fpip));
- memcpy(&xsave->data[8], &X86_CPU(cpu_state)->env.fpregs, sizeof(X86_CPU(cpu_state)->env.fpregs));
- memcpy(&xsave->data[144], &X86_CPU(cpu_state)->env.ymmh_regs, sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
- memcpy(&xsave->data[288], &X86_CPU(cpu_state)->env.zmmh_regs, sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
- memcpy(&xsave->data[272], &X86_CPU(cpu_state)->env.opmask_regs, sizeof(X86_CPU(cpu_state)->env.opmask_regs));
- memcpy(&xsave->data[240], &X86_CPU(cpu_state)->env.bnd_regs, sizeof(X86_CPU(cpu_state)->env.bnd_regs));
- memcpy(&xsave->data[256], &X86_CPU(cpu_state)->env.bndcs_regs, sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
- memcpy(&xsave->data[416], &X86_CPU(cpu_state)->env.hi16_zmm_regs, sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
-
- xsave->data[0] = (uint16_t)X86_CPU(cpu_state)->env.fpuc;
- xsave->data[0] |= (X86_CPU(cpu_state)->env.fpus << 16);
- xsave->data[0] |= (X86_CPU(cpu_state)->env.fpstt & 7) << 11;
-
- for (x = 0; x < 8; ++x)
- xsave->data[1] |= ((!X86_CPU(cpu_state)->env.fptags[x]) << x);
- xsave->data[1] |= (uint32_t)(X86_CPU(cpu_state)->env.fpop << 16);
-
- memcpy(&xsave->data[40], &X86_CPU(cpu_state)->env.xmm_regs, sizeof(X86_CPU(cpu_state)->env.xmm_regs));
-
- xsave->data[6] = X86_CPU(cpu_state)->env.mxcsr;
- *(uint64_t *)&xsave->data[128] = X86_CPU(cpu_state)->env.xstate_bv;
-
- if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, xsave->data, 4096)){
+
+ x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave);
+
+ if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, xsave->data, 4096)) {
abort();
}
}
@@ -185,39 +162,15 @@ void hvf_put_msrs(CPUState *cpu_state)
void hvf_get_xsave(CPUState *cpu_state)
{
- int x;
struct hvf_xsave_buf *xsave;
-
+
xsave = X86_CPU(cpu_state)->env.kvm_xsave_buf;
-
+
if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, xsave->data, 4096)) {
abort();
}
- memcpy(&X86_CPU(cpu_state)->env.fpdp, &xsave->data[4], sizeof(X86_CPU(cpu_state)->env.fpdp));
- memcpy(&X86_CPU(cpu_state)->env.fpip, &xsave->data[2], sizeof(X86_CPU(cpu_state)->env.fpip));
- memcpy(&X86_CPU(cpu_state)->env.fpregs, &xsave->data[8], sizeof(X86_CPU(cpu_state)->env.fpregs));
- memcpy(&X86_CPU(cpu_state)->env.ymmh_regs, &xsave->data[144], sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
- memcpy(&X86_CPU(cpu_state)->env.zmmh_regs, &xsave->data[288], sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
- memcpy(&X86_CPU(cpu_state)->env.opmask_regs, &xsave->data[272], sizeof(X86_CPU(cpu_state)->env.opmask_regs));
- memcpy(&X86_CPU(cpu_state)->env.bnd_regs, &xsave->data[240], sizeof(X86_CPU(cpu_state)->env.bnd_regs));
- memcpy(&X86_CPU(cpu_state)->env.bndcs_regs, &xsave->data[256], sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
- memcpy(&X86_CPU(cpu_state)->env.hi16_zmm_regs, &xsave->data[416], sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
-
-
- X86_CPU(cpu_state)->env.fpuc = (uint16_t)xsave->data[0];
- X86_CPU(cpu_state)->env.fpus = (uint16_t)(xsave->data[0] >> 16);
- X86_CPU(cpu_state)->env.fpstt = (X86_CPU(cpu_state)->env.fpus >> 11) & 7;
- X86_CPU(cpu_state)->env.fpop = (uint16_t)(xsave->data[1] >> 16);
-
- for (x = 0; x < 8; ++x)
- X86_CPU(cpu_state)->env.fptags[x] =
- ((((uint16_t)xsave->data[1] >> x) & 1) == 0);
-
- memcpy(&X86_CPU(cpu_state)->env.xmm_regs, &xsave->data[40], sizeof(X86_CPU(cpu_state)->env.xmm_regs));
-
- X86_CPU(cpu_state)->env.mxcsr = xsave->data[6];
- X86_CPU(cpu_state)->env.xstate_bv = *(uint64_t *)&xsave->data[128];
+ x86_cpu_xrstor_all_areas(X86_CPU(cpu_state), xsave);
}
void hvf_get_segments(CPUState *cpu_state)
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 06/14] hvf: add compilation rules to Makefile.objs
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (4 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 05/14] hvf: use new helper functions for put/get xsave Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:34 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 07/14] hvf: run hvf code through checkpatch.pl and fix style issues Sergio Andres Gomez Del Real
` (10 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit adds to target/i386/Makefile.objs the necessary rules so
that the new files for hvf are compiled by the build system.
It also adds handling of the -enable-hvf argument in the main function
in vl.c.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
target/i386/Makefile.objs | 1 +
vl.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target/i386/Makefile.objs b/target/i386/Makefile.objs
index 6a26e9d9f0..0bef89c099 100644
--- a/target/i386/Makefile.objs
+++ b/target/i386/Makefile.objs
@@ -12,4 +12,5 @@ obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-windows.o
endif
ifdef CONFIG_DARWIN
obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-darwin.o
+obj-$(CONFIG_HVF) += hvf-utils/ hvf-all.o
endif
diff --git a/vl.c b/vl.c
index 8e247cc2a2..de7d2a3858 100644
--- a/vl.c
+++ b/vl.c
@@ -3751,6 +3751,13 @@ int main(int argc, char **argv, char **envp)
olist = qemu_find_opts("machine");
qemu_opts_parse_noisily(olist, "accel=hax", false);
break;
+#if defined(__APPLE__)
+ case QEMU_OPTION_enable_hvf:
+ olist = qemu_find_opts("machine");
+ qemu_opts_parse_noisily(olist, "accel=hvf", false);
+ hvf_disable(0);
+ break;
+#endif
case QEMU_OPTION_M:
case QEMU_OPTION_machine:
olist = qemu_find_opts("machine");
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 07/14] hvf: run hvf code through checkpatch.pl and fix style issues
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (5 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 06/14] hvf: add compilation rules to Makefile.objs Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:35 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 08/14] apic: add function to apic that will be used by hvf Sergio Andres Gomez Del Real
` (9 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
include/sysemu/hvf.h | 22 +-
target/i386/hvf-all.c | 793 ++++++------
target/i386/hvf-i386.h | 2 +-
target/i386/hvf-utils/vmcs.h | 484 ++++----
target/i386/hvf-utils/vmx.h | 92 +-
target/i386/hvf-utils/x86.c | 86 +-
target/i386/hvf-utils/x86.h | 112 +-
target/i386/hvf-utils/x86_cpuid.c | 337 ++---
target/i386/hvf-utils/x86_cpuid.h | 7 +-
target/i386/hvf-utils/x86_decode.c | 2402 ++++++++++++++++++++++--------------
target/i386/hvf-utils/x86_decode.h | 30 +-
target/i386/hvf-utils/x86_descr.h | 29 +-
target/i386/hvf-utils/x86_emu.c | 1337 ++++++++++----------
target/i386/hvf-utils/x86_emu.h | 15 +
target/i386/hvf-utils/x86_flags.c | 52 +-
target/i386/hvf-utils/x86_flags.h | 101 +-
target/i386/hvf-utils/x86_mmu.c | 85 +-
target/i386/hvf-utils/x86_mmu.h | 6 +-
target/i386/hvf-utils/x86hvf.c | 106 +-
target/i386/hvf-utils/x86hvf.h | 5 +-
20 files changed, 3437 insertions(+), 2666 deletions(-)
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index 5e2b5f8f76..f9a5a9c5d3 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -49,7 +49,6 @@ struct hvf_vcpu_caps {
uint64_t vmx_cap_preemption_timer;
};
-int __hvf_set_memory(hvf_slot *);
void hvf_set_phys_mem(MemoryRegionSection *, bool);
void hvf_handle_io(CPUArchState *, uint16_t, void *,
int, int, int);
@@ -58,16 +57,16 @@ hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);
/* Returns 1 if HVF is available and enabled, 0 otherwise. */
int hvf_enabled(void);
-/* Disable HVF if |disable| is 1, otherwise, enable it iff it is supported by the host CPU.
- * Use hvf_enabled() after this to get the result. */
+/* Disable HVF if |disable| is 1, otherwise, enable it iff it is supported by
+ * the host CPU. Use hvf_enabled() after this to get the result. */
void hvf_disable(int disable);
-/* Returns non-0 if the host CPU supports the VMX "unrestricted guest" feature which
- * allows the virtual CPU to directly run in "real mode". If true, this allows QEMU to run
- * several vCPU threads in parallel (see cpus.c). Otherwise, only a a single TCG thread
- * can run, and it will call HVF to run the current instructions, except in case of
- * "real mode" (paging disabled, typically at boot time), or MMIO operations. */
-// int hvf_ug_platform(void); does not apply to HVF; assume we must be in UG mode
+/* Returns non-0 if the host CPU supports the VMX "unrestricted guest" feature
+ * which allows the virtual CPU to directly run in "real mode". If true, this
+ * allows QEMU to run several vCPU threads in parallel (see cpus.c). Otherwise,
+ * only a a single TCG thread can run, and it will call HVF to run the current
+ * instructions, except in case of "real mode" (paging disabled, typically at
+ * boot time), or MMIO operations. */
int hvf_sync_vcpus(void);
@@ -81,13 +80,12 @@ void _hvf_cpu_synchronize_post_init(CPUState *, run_on_cpu_data);
void hvf_vcpu_destroy(CPUState *);
void hvf_raise_event(CPUState *);
-// void hvf_reset_vcpu_state(void *opaque);
+/* void hvf_reset_vcpu_state(void *opaque); */
void vmx_reset_vcpu(CPUState *);
-void __hvf_cpu_synchronize_state(CPUState *, run_on_cpu_data);
-void __hvf_cpu_synchronize_post_reset(CPUState *, run_on_cpu_data);
void vmx_update_tpr(CPUState *);
void update_apic_tpr(CPUState *);
int hvf_put_registers(CPUState *);
+void vmx_clear_int_window_exiting(CPUState *cpu);
#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
index 06cd8429eb..88b5281975 100644
--- a/target/i386/hvf-all.c
+++ b/target/i386/hvf-all.c
@@ -34,44 +34,47 @@ static int hvf_disabled = 1;
static void assert_hvf_ok(hv_return_t ret)
{
- if (ret == HV_SUCCESS)
+ if (ret == HV_SUCCESS) {
return;
+ }
switch (ret) {
- case HV_ERROR:
- fprintf(stderr, "Error: HV_ERROR\n");
- break;
- case HV_BUSY:
- fprintf(stderr, "Error: HV_BUSY\n");
- break;
- case HV_BAD_ARGUMENT:
- fprintf(stderr, "Error: HV_BAD_ARGUMENT\n");
- break;
- case HV_NO_RESOURCES:
- fprintf(stderr, "Error: HV_NO_RESOURCES\n");
- break;
- case HV_NO_DEVICE:
- fprintf(stderr, "Error: HV_NO_DEVICE\n");
- break;
- case HV_UNSUPPORTED:
- fprintf(stderr, "Error: HV_UNSUPPORTED\n");
- break;
- default:
- fprintf(stderr, "Unknown Error\n");
+ case HV_ERROR:
+ fprintf(stderr, "Error: HV_ERROR\n");
+ break;
+ case HV_BUSY:
+ fprintf(stderr, "Error: HV_BUSY\n");
+ break;
+ case HV_BAD_ARGUMENT:
+ fprintf(stderr, "Error: HV_BAD_ARGUMENT\n");
+ break;
+ case HV_NO_RESOURCES:
+ fprintf(stderr, "Error: HV_NO_RESOURCES\n");
+ break;
+ case HV_NO_DEVICE:
+ fprintf(stderr, "Error: HV_NO_DEVICE\n");
+ break;
+ case HV_UNSUPPORTED:
+ fprintf(stderr, "Error: HV_UNSUPPORTED\n");
+ break;
+ default:
+ fprintf(stderr, "Unknown Error\n");
}
abort();
}
-// Memory slots/////////////////////////////////////////////////////////////////
-
-hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t end) {
+/* Memory slots */
+hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t end)
+{
hvf_slot *slot;
int x;
for (x = 0; x < hvf_state->num_slots; ++x) {
slot = &hvf_state->slots[x];
- if (slot->size && start < (slot->start + slot->size) && end > slot->start)
+ if (slot->size && start < (slot->start + slot->size) &&
+ end > slot->start) {
return slot;
+ }
}
return NULL;
}
@@ -84,13 +87,12 @@ struct mac_slot {
};
struct mac_slot mac_slots[32];
-#define ALIGN(x, y) (((x)+(y)-1) & ~((y)-1))
+#define ALIGN(x, y) (((x) + (y) - 1) & ~((y) - 1))
-int __hvf_set_memory(hvf_slot *slot)
+static int do_hvf_set_memory(hvf_slot *slot)
{
struct mac_slot *macslot;
hv_memory_flags_t flags;
- pthread_rwlock_wrlock(&mem_lock);
hv_return_t ret;
macslot = &mac_slots[slot->slot_id];
@@ -104,7 +106,6 @@ int __hvf_set_memory(hvf_slot *slot)
}
if (!slot->size) {
- pthread_rwlock_unlock(&mem_lock);
return 0;
}
@@ -115,16 +116,17 @@ int __hvf_set_memory(hvf_slot *slot)
macslot->size = slot->size;
ret = hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, flags);
assert_hvf_ok(ret);
- pthread_rwlock_unlock(&mem_lock);
return 0;
}
-void hvf_set_phys_mem(MemoryRegionSection* section, bool add)
+void hvf_set_phys_mem(MemoryRegionSection *section, bool add)
{
hvf_slot *mem;
MemoryRegion *area = section->mr;
- if (!memory_region_is_ram(area)) return;
+ if (!memory_region_is_ram(area)) {
+ return;
+ }
mem = hvf_find_overlap_slot(
section->offset_within_address_space,
@@ -132,29 +134,34 @@ void hvf_set_phys_mem(MemoryRegionSection* section, bool add)
if (mem && add) {
if (mem->size == int128_get64(section->size) &&
- mem->start == section->offset_within_address_space &&
- mem->mem == (memory_region_get_ram_ptr(area) + section->offset_within_region))
- return; // Same region was attempted to register, go away.
+ mem->start == section->offset_within_address_space &&
+ mem->mem == (memory_region_get_ram_ptr(area) +
+ section->offset_within_region)) {
+ return; /* Same region was attempted to register, go away. */
+ }
}
- // Region needs to be reset. set the size to 0 and remap it.
+ /* Region needs to be reset. set the size to 0 and remap it. */
if (mem) {
mem->size = 0;
- if (__hvf_set_memory(mem)) {
+ if (do_hvf_set_memory(mem)) {
fprintf(stderr, "Failed to reset overlapping slot\n");
abort();
}
}
- if (!add) return;
+ if (!add) {
+ return;
+ }
- // Now make a new slot.
+ /* Now make a new slot. */
int x;
for (x = 0; x < hvf_state->num_slots; ++x) {
mem = &hvf_state->slots[x];
- if (!mem->size)
+ if (!mem->size) {
break;
+ }
}
if (x == hvf_state->num_slots) {
@@ -166,36 +173,26 @@ void hvf_set_phys_mem(MemoryRegionSection* section, bool add)
mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region;
mem->start = section->offset_within_address_space;
- if (__hvf_set_memory(mem)) {
+ if (do_hvf_set_memory(mem)) {
fprintf(stderr, "Error registering new memory slot\n");
abort();
}
}
-/* return -1 if no bit is set */
-static int get_highest_priority_int(uint32_t *tab)
-{
- int i;
- for (i = 7; i >= 0; i--) {
- if (tab[i] != 0) {
- return i * 32 + apic_fls_bit(tab[i]);
- }
- }
- return -1;
-}
-
void vmx_update_tpr(CPUState *cpu)
{
- // TODO: need integrate APIC handling
+ /* TODO: need integrate APIC handling */
X86CPU *x86_cpu = X86_CPU(cpu);
int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
wreg(cpu->hvf_fd, HV_X86_TPR, tpr);
- if (irr == -1)
+ if (irr == -1) {
wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
- else
- wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4);
+ } else {
+ wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 :
+ irr >> 4);
+ }
}
void update_apic_tpr(CPUState *cpu)
@@ -207,7 +204,7 @@ void update_apic_tpr(CPUState *cpu)
#define VECTORING_INFO_VECTOR_MASK 0xff
-// TODO: taskswitch handling
+/* TODO: taskswitch handling */
static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
{
/* CR3 and ldt selector are not saved intentionally */
@@ -247,13 +244,20 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
RSI(cpu) = tss->esi;
RDI(cpu) = tss->edi;
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS);
- vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}},
+ REG_SEG_LDTR);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}},
+ REG_SEG_ES);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}},
+ REG_SEG_CS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}},
+ REG_SEG_SS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}},
+ REG_SEG_DS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}},
+ REG_SEG_FS);
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}},
+ REG_SEG_GS);
#if 0
load_segment(cpu, REG_SEG_LDTR, tss->ldt);
@@ -266,8 +270,10 @@ static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
#endif
}
-static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
- uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
+static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel,
+ x68_segment_selector old_tss_sel,
+ uint64_t old_tss_base,
+ struct x86_segment_descriptor *new_desc)
{
struct x86_tss_segment32 tss_seg;
uint32_t new_tss_base = x86_segment_base(new_desc);
@@ -277,19 +283,22 @@ static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segme
vmx_read_mem(cpu, &tss_seg, old_tss_base, sizeof(tss_seg));
save_state_to_tss32(cpu, &tss_seg);
- vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset);
+ vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset -
+ eip_offset);
vmx_read_mem(cpu, &tss_seg, new_tss_base, sizeof(tss_seg));
if (old_tss_sel.sel != 0xffff) {
tss_seg.prev_tss = old_tss_sel.sel;
- vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss));
+ vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss,
+ sizeof(tss_seg.prev_tss));
}
load_state_from_tss32(cpu, &tss_seg);
return 0;
}
-static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
+static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
+ int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
{
uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP);
if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
@@ -320,12 +329,14 @@ static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
dpl = task_gate_desc.dpl;
x68_segment_selector cs = vmx_read_segment_selector(cpu, REG_SEG_CS);
- if (tss_sel.rpl > dpl || cs.rpl > dpl)
- ;//DPRINTF("emulate_gp");
+ if (tss_sel.rpl > dpl || cs.rpl > dpl) {
+ VM_PANIC("emulate_gp");
+ }
}
desc_limit = x86_segment_limit(&next_tss_desc);
- if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) {
+ if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
+ desc_limit < 0x2b)) {
VM_PANIC("emulate_ts");
}
@@ -334,22 +345,27 @@ static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
x86_write_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
}
- if (reason == TSR_IRET)
+ if (reason == TSR_IRET) {
EFLAGS(cpu) &= ~RFLAGS_NT;
+ }
- if (reason != TSR_CALL && reason != TSR_IDT_GATE)
+ if (reason != TSR_CALL && reason != TSR_IDT_GATE) {
old_tss_sel.sel = 0xffff;
+ }
if (reason != TSR_IRET) {
next_tss_desc.type |= (1 << 1); /* set busy flag */
x86_write_segment_descriptor(cpu, &next_tss_desc, tss_sel);
}
- if (next_tss_desc.type & 8)
- ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
- else
- //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
+ if (next_tss_desc.type & 8) {
+ ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base,
+ &next_tss_desc);
+ } else {
+ /*ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base,
+ * &next_tss_desc);*/
VM_PANIC("task_switch_16");
+ }
macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS);
x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
@@ -361,7 +377,7 @@ static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
hv_vcpu_flush(cpu->hvf_fd);
}
-static void hvf_handle_interrupt(CPUState * cpu, int mask)
+static void hvf_handle_interrupt(CPUState *cpu, int mask)
{
cpu->interrupt_request |= mask;
if (!qemu_cpu_is_self(cpu)) {
@@ -369,7 +385,7 @@ static void hvf_handle_interrupt(CPUState * cpu, int mask)
}
}
-void hvf_handle_io(CPUArchState * env, uint16_t port, void* buffer,
+void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer,
int direction, int size, int count)
{
int i;
@@ -382,24 +398,26 @@ void hvf_handle_io(CPUArchState * env, uint16_t port, void* buffer,
ptr += size;
}
}
-//
-// TODO: synchronize vcpu state
-void __hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
+
+/* TODO: synchronize vcpu state */
+static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
{
- CPUState *cpu_state = cpu;//(CPUState *)data;
- if (cpu_state->hvf_vcpu_dirty == 0)
+ CPUState *cpu_state = cpu;
+ if (cpu_state->hvf_vcpu_dirty == 0) {
hvf_get_registers(cpu_state);
+ }
cpu_state->hvf_vcpu_dirty = 1;
}
void hvf_cpu_synchronize_state(CPUState *cpu_state)
{
- if (cpu_state->hvf_vcpu_dirty == 0)
- run_on_cpu(cpu_state, __hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
+ if (cpu_state->hvf_vcpu_dirty == 0) {
+ run_on_cpu(cpu_state, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
+ }
}
-void __hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
+static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
{
CPUState *cpu_state = cpu;
hvf_put_registers(cpu_state);
@@ -408,7 +426,7 @@ void __hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
void hvf_cpu_synchronize_post_reset(CPUState *cpu_state)
{
- run_on_cpu(cpu_state, __hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
+ run_on_cpu(cpu_state, do_hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
}
void _hvf_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
@@ -422,44 +440,45 @@ void hvf_cpu_synchronize_post_init(CPUState *cpu_state)
{
run_on_cpu(cpu_state, _hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
}
-
-// TODO: ept fault handlig
-void vmx_clear_int_window_exiting(CPUState *cpu);
+
+/* TODO: ept fault handlig */
static bool ept_emulation_fault(uint64_t ept_qual)
{
- int read, write;
-
- /* EPT fault on an instruction fetch doesn't make sense here */
- if (ept_qual & EPT_VIOLATION_INST_FETCH)
- return false;
-
- /* EPT fault must be a read fault or a write fault */
- read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
- write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
- if ((read | write) == 0)
- return false;
-
- /*
- * The EPT violation must have been caused by accessing a
- * guest-physical address that is a translation of a guest-linear
- * address.
- */
- if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
- (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
- return false;
- }
-
- return true;
+ int read, write;
+
+ /* EPT fault on an instruction fetch doesn't make sense here */
+ if (ept_qual & EPT_VIOLATION_INST_FETCH) {
+ return false;
+ }
+
+ /* EPT fault must be a read fault or a write fault */
+ read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
+ write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
+ if ((read | write) == 0) {
+ return false;
+ }
+
+ /*
+ * The EPT violation must have been caused by accessing a
+ * guest-physical address that is a translation of a guest-linear
+ * address.
+ */
+ if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
+ (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
+ return false;
+ }
+
+ return true;
}
-static void hvf_region_add(MemoryListener * listener,
- MemoryRegionSection * section)
+static void hvf_region_add(MemoryListener *listener,
+ MemoryRegionSection *section)
{
hvf_set_phys_mem(section, true);
}
-static void hvf_region_del(MemoryListener * listener,
- MemoryRegionSection * section)
+static void hvf_region_del(MemoryListener *listener,
+ MemoryRegionSection *section)
{
hvf_set_phys_mem(section, false);
}
@@ -470,70 +489,69 @@ static MemoryListener hvf_memory_listener = {
.region_del = hvf_region_del,
};
-static MemoryListener hvf_io_listener = {
- .priority = 10,
-};
-
void vmx_reset_vcpu(CPUState *cpu) {
+ /* TODO: this shouldn't be needed; there is already a call to
+ * cpu_synchronize_all_post_reset in vl.c
+ */
wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, 0);
macvm_set_cr0(cpu->hvf_fd, 0x60000010);
-
+
wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK);
wvmcs(cpu->hvf_fd, VMCS_CR4_SHADOW, 0x0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_CR4, CR4_VMXE_MASK);
-
- // set VMCS guest state fields
+
+ /* set VMCS guest state fields */
wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_SELECTOR, 0xf000);
wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_LIMIT, 0xffff);
wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_ACCESS_RIGHTS, 0x9b);
wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_BASE, 0xffff0000);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_LIMIT, 0xffff);
wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_ACCESS_RIGHTS, 0x93);
wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_LIMIT, 0xffff);
wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_ACCESS_RIGHTS, 0x93);
wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_LIMIT, 0xffff);
wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_ACCESS_RIGHTS, 0x93);
wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_LIMIT, 0xffff);
wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_ACCESS_RIGHTS, 0x93);
wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_LIMIT, 0xffff);
wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_ACCESS_RIGHTS, 0x93);
wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x10000);
wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_SELECTOR, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_LIMIT, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_ACCESS_RIGHTS, 0x83);
wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE, 0);
-
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT, 0);
wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE, 0);
-
- //wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);
+
+ /*wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);*/
wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, 0x0);
-
+
wreg(cpu->hvf_fd, HV_X86_RIP, 0xfff0);
wreg(cpu->hvf_fd, HV_X86_RDX, 0x623);
wreg(cpu->hvf_fd, HV_X86_RFLAGS, 0x2);
@@ -544,9 +562,10 @@ void vmx_reset_vcpu(CPUState *cpu) {
wreg(cpu->hvf_fd, HV_X86_RSI, 0x0);
wreg(cpu->hvf_fd, HV_X86_RDI, 0x0);
wreg(cpu->hvf_fd, HV_X86_RBP, 0x0);
-
- for (int i = 0; i < 8; i++)
- wreg(cpu->hvf_fd, HV_X86_R8+i, 0x0);
+
+ for (int i = 0; i < 8; i++) {
+ wreg(cpu->hvf_fd, HV_X86_R8 + i, 0x0);
+ }
hv_vm_sync_tsc(0);
cpu->halted = 0;
@@ -554,7 +573,7 @@ void vmx_reset_vcpu(CPUState *cpu) {
hv_vcpu_flush(cpu->hvf_fd);
}
-void hvf_vcpu_destroy(CPUState* cpu)
+void hvf_vcpu_destroy(CPUState *cpu)
{
hv_return_t ret = hv_vcpu_destroy((hv_vcpuid_t)cpu->hvf_fd);
assert_hvf_ok(ret);
@@ -564,11 +583,12 @@ static void dummy_signal(int sig)
{
}
-int hvf_init_vcpu(CPUState * cpu) {
+int hvf_init_vcpu(CPUState *cpu)
+{
X86CPU *x86cpu;
-
- // init cpu signals
+
+ /* init cpu signals */
sigset_t set;
struct sigaction sigact;
@@ -584,42 +604,55 @@ int hvf_init_vcpu(CPUState * cpu) {
init_decoder(cpu);
init_cpuid(cpu);
- cpu->hvf_caps = (struct hvf_vcpu_caps*)g_malloc0(sizeof(struct hvf_vcpu_caps));
- cpu->hvf_x86 = (struct hvf_x86_state*)g_malloc0(sizeof(struct hvf_x86_state));
+ cpu->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
+ cpu->hvf_x86 = (struct hvf_x86_state *)g_malloc0(sizeof(struct hvf_x86_state));
r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);
cpu->hvf_vcpu_dirty = 1;
assert_hvf_ok(r);
- if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &cpu->hvf_caps->vmx_cap_pinbased))
- abort();
- if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cpu->hvf_caps->vmx_cap_procbased))
- abort();
- if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cpu->hvf_caps->vmx_cap_procbased2))
- abort();
- if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cpu->hvf_caps->vmx_cap_entry))
- abort();
-
- /* set VMCS control fields */
- wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));
- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,
- VMCS_PRI_PROC_BASED_CTLS_HLT |
- VMCS_PRI_PROC_BASED_CTLS_MWAIT |
- VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
- VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
- VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
- wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,
- cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
-
- wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry, 0));
- wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
+ if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED,
+ &cpu->hvf_caps->vmx_cap_pinbased)) {
+ abort();
+ }
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED,
+ &cpu->hvf_caps->vmx_cap_procbased)) {
+ abort();
+ }
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2,
+ &cpu->hvf_caps->vmx_cap_procbased2)) {
+ abort();
+ }
+ if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY,
+ &cpu->hvf_caps->vmx_cap_entry)) {
+ abort();
+ }
+
+ /* set VMCS control fields */
+ wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS,
+ cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS,
+ cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,
+ VMCS_PRI_PROC_BASED_CTLS_HLT |
+ VMCS_PRI_PROC_BASED_CTLS_MWAIT |
+ VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
+ VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
+ VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
+ wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,
+ cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,
+ VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
+
+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry,
+ 0));
+ wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
vmx_reset_vcpu(cpu);
x86cpu = X86_CPU(cpu);
- x86cpu->env.kvm_xsave_buf = qemu_memalign(4096, sizeof(struct hvf_xsave_buf));
+ x86cpu->env.kvm_xsave_buf = qemu_memalign(4096,
+ sizeof(struct hvf_xsave_buf));
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1);
@@ -629,7 +662,7 @@ int hvf_init_vcpu(CPUState * cpu) {
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1);
- //hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);
+ /*hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);*/
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1);
hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1);
@@ -637,12 +670,18 @@ int hvf_init_vcpu(CPUState * cpu) {
return 0;
}
-int hvf_enabled() { return !hvf_disabled; }
-void hvf_disable(int shouldDisable) {
+int hvf_enabled()
+{
+ return !hvf_disabled;
+}
+
+void hvf_disable(int shouldDisable)
+{
hvf_disabled = shouldDisable;
}
-int hvf_vcpu_exec(CPUState* cpu) {
+int hvf_vcpu_exec(CPUState *cpu)
+{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
int ret = 0;
@@ -662,7 +701,8 @@ int hvf_vcpu_exec(CPUState* cpu) {
cpu->hvf_x86->interruptable =
!(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
- (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
+ (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
+ VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
hvf_inject_interrupts(cpu);
vmx_update_tpr(cpu);
@@ -680,14 +720,13 @@ int hvf_vcpu_exec(CPUState* cpu) {
/* handle VMEXIT */
uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON);
uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);
- uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd,
+ VMCS_EXIT_INSTRUCTION_LENGTH);
uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
rip = rreg(cpu->hvf_fd, HV_X86_RIP);
RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
env->eflags = RFLAGS(cpu);
- trace_hvf_vm_exit(exit_reason, exit_qual);
-
qemu_mutex_lock_iothread();
update_apic_tpr(cpu);
@@ -695,239 +734,226 @@ int hvf_vcpu_exec(CPUState* cpu) {
ret = 0;
switch (exit_reason) {
- case EXIT_REASON_HLT: {
- macvm_set_rip(cpu, rip + ins_len);
- if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu) & IF_MASK))
- && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
- !(idtvec_info & VMCS_IDT_VEC_VALID)) {
- cpu->halted = 1;
- ret = EXCP_HLT;
- }
- ret = EXCP_INTERRUPT;
- break;
- }
- case EXIT_REASON_MWAIT: {
- ret = EXCP_INTERRUPT;
- break;
+ case EXIT_REASON_HLT: {
+ macvm_set_rip(cpu, rip + ins_len);
+ if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (EFLAGS(cpu) & IF_MASK))
+ && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
+ !(idtvec_info & VMCS_IDT_VEC_VALID)) {
+ cpu->halted = 1;
+ ret = EXCP_HLT;
}
- /* Need to check if MMIO or unmmaped fault */
- case EXIT_REASON_EPT_FAULT:
- {
- hvf_slot *slot;
- addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
- trace_hvf_vm_exit_gpa(gpa);
-
- if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && (exit_qual & EXIT_QUAL_NMIUDTI) != 0)
- vmx_set_nmi_blocking(cpu);
-
- slot = hvf_find_overlap_slot(gpa, gpa);
- // mmio
- if (ept_emulation_fault(exit_qual) && !slot) {
- struct x86_decode decode;
-
- load_regs(cpu);
- cpu->hvf_x86->fetch_rip = rip;
-
- decode_instruction(cpu, &decode);
- exec_instruction(cpu, &decode);
- store_regs(cpu);
- break;
- }
-#ifdef DIRTY_VGA_TRACKING
- if (slot) {
- bool read = exit_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
- bool write = exit_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
- if (!read && !write)
- break;
- int flags = HV_MEMORY_READ | HV_MEMORY_EXEC;
- if (write) flags |= HV_MEMORY_WRITE;
-
- pthread_rwlock_wrlock(&mem_lock);
- if (write)
- mark_slot_page_dirty(slot, gpa);
- hv_vm_protect(gpa & ~0xfff, 4096, flags);
- pthread_rwlock_unlock(&mem_lock);
- }
-#endif
- break;
+ ret = EXCP_INTERRUPT;
+ break;
+ }
+ case EXIT_REASON_MWAIT: {
+ ret = EXCP_INTERRUPT;
+ break;
+ }
+ /* Need to check if MMIO or unmmaped fault */
+ case EXIT_REASON_EPT_FAULT:
+ {
+ hvf_slot *slot;
+ addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
+
+ if (((idtvec_info & VMCS_IDT_VEC_VALID) == 0) &&
+ ((exit_qual & EXIT_QUAL_NMIUDTI) != 0)) {
+ vmx_set_nmi_blocking(cpu);
}
- case EXIT_REASON_INOUT:
- {
- uint32_t in = (exit_qual & 8) != 0;
- uint32_t size = (exit_qual & 7) + 1;
- uint32_t string = (exit_qual & 16) != 0;
- uint32_t port = exit_qual >> 16;
- //uint32_t rep = (exit_qual & 0x20) != 0;
-#if 1
- if (!string && in) {
- uint64_t val = 0;
- load_regs(cpu);
- hvf_handle_io(env, port, &val, 0, size, 1);
- if (size == 1) AL(cpu) = val;
- else if (size == 2) AX(cpu) = val;
- else if (size == 4) RAX(cpu) = (uint32_t)val;
- else VM_PANIC("size");
- RIP(cpu) += ins_len;
- store_regs(cpu);
- break;
- } else if (!string && !in) {
- RAX(cpu) = rreg(cpu->hvf_fd, HV_X86_RAX);
- hvf_handle_io(env, port, &RAX(cpu), 1, size, 1);
- macvm_set_rip(cpu, rip + ins_len);
- break;
- }
-#endif
+ slot = hvf_find_overlap_slot(gpa, gpa);
+ /* mmio */
+ if (ept_emulation_fault(exit_qual) && !slot) {
struct x86_decode decode;
load_regs(cpu);
cpu->hvf_x86->fetch_rip = rip;
decode_instruction(cpu, &decode);
- VM_PANIC_ON(ins_len != decode.len);
exec_instruction(cpu, &decode);
store_regs(cpu);
-
- break;
- }
- case EXIT_REASON_CPUID: {
- uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
- uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX);
- uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
- uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
-
- get_cpuid_func(cpu, rax, rcx, &rax, &rbx, &rcx, &rdx);
-
- wreg(cpu->hvf_fd, HV_X86_RAX, rax);
- wreg(cpu->hvf_fd, HV_X86_RBX, rbx);
- wreg(cpu->hvf_fd, HV_X86_RCX, rcx);
- wreg(cpu->hvf_fd, HV_X86_RDX, rdx);
-
- macvm_set_rip(cpu, rip + ins_len);
- break;
- }
- case EXIT_REASON_XSETBV: {
- X86CPU *x86_cpu = X86_CPU(cpu);
- CPUX86State *env = &x86_cpu->env;
- uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
- uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
- uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
-
- if (ecx) {
- macvm_set_rip(cpu, rip + ins_len);
- break;
- }
- env->xcr0 = ((uint64_t)edx << 32) | eax;
- wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1);
- macvm_set_rip(cpu, rip + ins_len);
- break;
- }
- case EXIT_REASON_INTR_WINDOW:
- vmx_clear_int_window_exiting(cpu);
- ret = EXCP_INTERRUPT;
- break;
- case EXIT_REASON_NMI_WINDOW:
- vmx_clear_nmi_window_exiting(cpu);
- ret = EXCP_INTERRUPT;
- break;
- case EXIT_REASON_EXT_INTR:
- /* force exit and allow io handling */
- ret = EXCP_INTERRUPT;
- break;
- case EXIT_REASON_RDMSR:
- case EXIT_REASON_WRMSR:
- {
- load_regs(cpu);
- if (exit_reason == EXIT_REASON_RDMSR)
- simulate_rdmsr(cpu);
- else
- simulate_wrmsr(cpu);
- RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
- store_regs(cpu);
break;
}
- case EXIT_REASON_CR_ACCESS: {
- int cr;
- int reg;
+#ifdef DIRTY_VGA_TRACKING
+ /* TODO: handle dirty page tracking */
+#endif
+ break;
+ }
+ case EXIT_REASON_INOUT:
+ {
+ uint32_t in = (exit_qual & 8) != 0;
+ uint32_t size = (exit_qual & 7) + 1;
+ uint32_t string = (exit_qual & 16) != 0;
+ uint32_t port = exit_qual >> 16;
+ /*uint32_t rep = (exit_qual & 0x20) != 0;*/
+#if 1
+ if (!string && in) {
+ uint64_t val = 0;
load_regs(cpu);
- cr = exit_qual & 15;
- reg = (exit_qual >> 8) & 15;
-
- switch (cr) {
- case 0x0: {
- macvm_set_cr0(cpu->hvf_fd, RRX(cpu, reg));
- break;
- }
- case 4: {
- macvm_set_cr4(cpu->hvf_fd, RRX(cpu, reg));
- break;
- }
- case 8: {
- X86CPU *x86_cpu = X86_CPU(cpu);
- if (exit_qual & 0x10) {
- RRX(cpu, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
- }
- else {
- int tpr = RRX(cpu, reg);
- cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
- ret = EXCP_INTERRUPT;
- }
- break;
- }
- default:
- fprintf(stderr, "Unrecognized CR %d\n", cr);
- abort();
+ hvf_handle_io(env, port, &val, 0, size, 1);
+ if (size == 1) {
+ AL(cpu) = val;
+ } else if (size == 2) {
+ AX(cpu) = val;
+ } else if (size == 4) {
+ RAX(cpu) = (uint32_t)val;
+ } else {
+ VM_PANIC("size");
}
RIP(cpu) += ins_len;
store_regs(cpu);
break;
+ } else if (!string && !in) {
+ RAX(cpu) = rreg(cpu->hvf_fd, HV_X86_RAX);
+ hvf_handle_io(env, port, &RAX(cpu), 1, size, 1);
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
}
- case EXIT_REASON_APIC_ACCESS: { // TODO
- struct x86_decode decode;
+#endif
+ struct x86_decode decode;
- load_regs(cpu);
- cpu->hvf_x86->fetch_rip = rip;
+ load_regs(cpu);
+ cpu->hvf_x86->fetch_rip = rip;
- decode_instruction(cpu, &decode);
- exec_instruction(cpu, &decode);
- store_regs(cpu);
+ decode_instruction(cpu, &decode);
+ VM_PANIC_ON(ins_len != decode.len);
+ exec_instruction(cpu, &decode);
+ store_regs(cpu);
+
+ break;
+ }
+ case EXIT_REASON_CPUID: {
+ uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
+ uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX);
+ uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
+ uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
+
+ cpu_x86_cpuid(cpu, rax, rcx, &rax, &rbx, &rcx, &rdx);
+
+ wreg(cpu->hvf_fd, HV_X86_RAX, rax);
+ wreg(cpu->hvf_fd, HV_X86_RBX, rbx);
+ wreg(cpu->hvf_fd, HV_X86_RCX, rcx);
+ wreg(cpu->hvf_fd, HV_X86_RDX, rdx);
+
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ }
+ case EXIT_REASON_XSETBV: {
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
+ uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
+ uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
+
+ if (ecx) {
+ macvm_set_rip(cpu, rip + ins_len);
break;
}
- case EXIT_REASON_TPR: {
- ret = 1;
- break;
+ env->xcr0 = ((uint64_t)edx << 32) | eax;
+ wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1);
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ }
+ case EXIT_REASON_INTR_WINDOW:
+ vmx_clear_int_window_exiting(cpu);
+ ret = EXCP_INTERRUPT;
+ break;
+ case EXIT_REASON_NMI_WINDOW:
+ vmx_clear_nmi_window_exiting(cpu);
+ ret = EXCP_INTERRUPT;
+ break;
+ case EXIT_REASON_EXT_INTR:
+ /* force exit and allow io handling */
+ ret = EXCP_INTERRUPT;
+ break;
+ case EXIT_REASON_RDMSR:
+ case EXIT_REASON_WRMSR:
+ {
+ load_regs(cpu);
+ if (exit_reason == EXIT_REASON_RDMSR) {
+ simulate_rdmsr(cpu);
+ } else {
+ simulate_wrmsr(cpu);
}
- case EXIT_REASON_TASK_SWITCH: {
- uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
- x68_segment_selector sel = {.sel = exit_qual & 0xffff};
- vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
- vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo & VMCS_INTR_T_MASK);
+ RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ store_regs(cpu);
+ break;
+ }
+ case EXIT_REASON_CR_ACCESS: {
+ int cr;
+ int reg;
+
+ load_regs(cpu);
+ cr = exit_qual & 15;
+ reg = (exit_qual >> 8) & 15;
+
+ switch (cr) {
+ case 0x0: {
+ macvm_set_cr0(cpu->hvf_fd, RRX(cpu, reg));
break;
}
- case EXIT_REASON_TRIPLE_FAULT: {
- //addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
- usleep(1000 * 100);
- ret = EXCP_INTERRUPT;
+ case 4: {
+ macvm_set_cr4(cpu->hvf_fd, RRX(cpu, reg));
break;
}
- case EXIT_REASON_RDPMC:
- wreg(cpu->hvf_fd, HV_X86_RAX, 0);
- wreg(cpu->hvf_fd, HV_X86_RDX, 0);
- macvm_set_rip(cpu, rip + ins_len);
- break;
- case VMX_REASON_VMCALL:
- // TODO: maybe just take this out?
- // if (g_hypervisor_iface) {
- // load_regs(cpu);
- // g_hypervisor_iface->hypercall_handler(cpu);
- // RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
- // store_regs(cpu);
- // }
+ case 8: {
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ if (exit_qual & 0x10) {
+ RRX(cpu, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
+ } else {
+ int tpr = RRX(cpu, reg);
+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
+ ret = EXCP_INTERRUPT;
+ }
break;
+ }
default:
- fprintf(stderr, "%llx: unhandled exit %llx\n", rip, exit_reason);
+ fprintf(stderr, "Unrecognized CR %d\n", cr);
+ abort();
+ }
+ RIP(cpu) += ins_len;
+ store_regs(cpu);
+ break;
+ }
+ case EXIT_REASON_APIC_ACCESS: { /* TODO */
+ struct x86_decode decode;
+
+ load_regs(cpu);
+ cpu->hvf_x86->fetch_rip = rip;
+
+ decode_instruction(cpu, &decode);
+ exec_instruction(cpu, &decode);
+ store_regs(cpu);
+ break;
+ }
+ case EXIT_REASON_TPR: {
+ ret = 1;
+ break;
+ }
+ case EXIT_REASON_TASK_SWITCH: {
+ uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
+ x68_segment_selector sel = {.sel = exit_qual & 0xffff};
+ vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
+ vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo
+ & VMCS_INTR_T_MASK);
+ break;
+ }
+ case EXIT_REASON_TRIPLE_FAULT: {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ ret = EXCP_INTERRUPT;
+ break;
+ }
+ case EXIT_REASON_RDPMC:
+ wreg(cpu->hvf_fd, HV_X86_RAX, 0);
+ wreg(cpu->hvf_fd, HV_X86_RDX, 0);
+ macvm_set_rip(cpu, rip + ins_len);
+ break;
+ case VMX_REASON_VMCALL:
+ /* TODO: inject #GP fault */
+ break;
+ default:
+ fprintf(stderr, "%llx: unhandled exit %llx\n", rip, exit_reason);
}
} while (ret == 0);
@@ -946,17 +972,16 @@ static int hvf_accel_init(MachineState *ms)
assert_hvf_ok(ret);
s = (HVFState *)g_malloc0(sizeof(HVFState));
-
+
s->num_slots = 32;
for (x = 0; x < s->num_slots; ++x) {
s->slots[x].size = 0;
s->slots[x].slot_id = x;
}
-
+
hvf_state = s;
cpu_interrupt_handler = hvf_handle_interrupt;
memory_listener_register(&hvf_memory_listener, &address_space_memory);
- memory_listener_register(&hvf_io_listener, &address_space_io);
return 0;
}
diff --git a/target/i386/hvf-i386.h b/target/i386/hvf-i386.h
index f3f958058a..797718ce34 100644
--- a/target/i386/hvf-i386.h
+++ b/target/i386/hvf-i386.h
@@ -41,7 +41,7 @@ struct hvf_state {
/* Functions exported to host specific mode */
/* Host specific functions */
-int hvf_inject_interrupt(CPUArchState * env, int vector);
+int hvf_inject_interrupt(CPUArchState *env, int vector);
int hvf_vcpu_run(struct hvf_vcpu_state *vcpu);
#endif
diff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf-utils/vmcs.h
index 6f7ccb361a..c410dcfaaa 100644
--- a/target/i386/hvf-utils/vmcs.h
+++ b/target/i386/hvf-utils/vmcs.h
@@ -27,326 +27,326 @@
*/
#ifndef _VMCS_H_
-#define _VMCS_H_
+#define _VMCS_H_
#include <Hypervisor/hv.h>
#include <Hypervisor/hv_vmx.h>
-#define VMCS_INITIAL 0xffffffffffffffff
+#define VMCS_INITIAL 0xffffffffffffffff
-#define VMCS_IDENT(encoding) ((encoding) | 0x80000000)
+#define VMCS_IDENT(encoding) ((encoding) | 0x80000000)
/*
* VMCS field encodings from Appendix H, Intel Architecture Manual Vol3B.
*/
-#define VMCS_INVALID_ENCODING 0xffffffff
+#define VMCS_INVALID_ENCODING 0xffffffff
/* 16-bit control fields */
-#define VMCS_VPID 0x00000000
-#define VMCS_PIR_VECTOR 0x00000002
+#define VMCS_VPID 0x00000000
+#define VMCS_PIR_VECTOR 0x00000002
/* 16-bit guest-state fields */
-#define VMCS_GUEST_ES_SELECTOR 0x00000800
-#define VMCS_GUEST_CS_SELECTOR 0x00000802
-#define VMCS_GUEST_SS_SELECTOR 0x00000804
-#define VMCS_GUEST_DS_SELECTOR 0x00000806
-#define VMCS_GUEST_FS_SELECTOR 0x00000808
-#define VMCS_GUEST_GS_SELECTOR 0x0000080A
-#define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
-#define VMCS_GUEST_TR_SELECTOR 0x0000080E
-#define VMCS_GUEST_INTR_STATUS 0x00000810
+#define VMCS_GUEST_ES_SELECTOR 0x00000800
+#define VMCS_GUEST_CS_SELECTOR 0x00000802
+#define VMCS_GUEST_SS_SELECTOR 0x00000804
+#define VMCS_GUEST_DS_SELECTOR 0x00000806
+#define VMCS_GUEST_FS_SELECTOR 0x00000808
+#define VMCS_GUEST_GS_SELECTOR 0x0000080A
+#define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
+#define VMCS_GUEST_TR_SELECTOR 0x0000080E
+#define VMCS_GUEST_INTR_STATUS 0x00000810
/* 16-bit host-state fields */
-#define VMCS_HOST_ES_SELECTOR 0x00000C00
-#define VMCS_HOST_CS_SELECTOR 0x00000C02
-#define VMCS_HOST_SS_SELECTOR 0x00000C04
-#define VMCS_HOST_DS_SELECTOR 0x00000C06
-#define VMCS_HOST_FS_SELECTOR 0x00000C08
-#define VMCS_HOST_GS_SELECTOR 0x00000C0A
-#define VMCS_HOST_TR_SELECTOR 0x00000C0C
+#define VMCS_HOST_ES_SELECTOR 0x00000C00
+#define VMCS_HOST_CS_SELECTOR 0x00000C02
+#define VMCS_HOST_SS_SELECTOR 0x00000C04
+#define VMCS_HOST_DS_SELECTOR 0x00000C06
+#define VMCS_HOST_FS_SELECTOR 0x00000C08
+#define VMCS_HOST_GS_SELECTOR 0x00000C0A
+#define VMCS_HOST_TR_SELECTOR 0x00000C0C
/* 64-bit control fields */
-#define VMCS_IO_BITMAP_A 0x00002000
-#define VMCS_IO_BITMAP_B 0x00002002
-#define VMCS_MSR_BITMAP 0x00002004
-#define VMCS_EXIT_MSR_STORE 0x00002006
-#define VMCS_EXIT_MSR_LOAD 0x00002008
-#define VMCS_ENTRY_MSR_LOAD 0x0000200A
-#define VMCS_EXECUTIVE_VMCS 0x0000200C
-#define VMCS_TSC_OFFSET 0x00002010
-#define VMCS_VIRTUAL_APIC 0x00002012
-#define VMCS_APIC_ACCESS 0x00002014
-#define VMCS_PIR_DESC 0x00002016
-#define VMCS_EPTP 0x0000201A
-#define VMCS_EOI_EXIT0 0x0000201C
-#define VMCS_EOI_EXIT1 0x0000201E
-#define VMCS_EOI_EXIT2 0x00002020
-#define VMCS_EOI_EXIT3 0x00002022
-#define VMCS_EOI_EXIT(vector) (VMCS_EOI_EXIT0 + ((vector) / 64) * 2)
+#define VMCS_IO_BITMAP_A 0x00002000
+#define VMCS_IO_BITMAP_B 0x00002002
+#define VMCS_MSR_BITMAP 0x00002004
+#define VMCS_EXIT_MSR_STORE 0x00002006
+#define VMCS_EXIT_MSR_LOAD 0x00002008
+#define VMCS_ENTRY_MSR_LOAD 0x0000200A
+#define VMCS_EXECUTIVE_VMCS 0x0000200C
+#define VMCS_TSC_OFFSET 0x00002010
+#define VMCS_VIRTUAL_APIC 0x00002012
+#define VMCS_APIC_ACCESS 0x00002014
+#define VMCS_PIR_DESC 0x00002016
+#define VMCS_EPTP 0x0000201A
+#define VMCS_EOI_EXIT0 0x0000201C
+#define VMCS_EOI_EXIT1 0x0000201E
+#define VMCS_EOI_EXIT2 0x00002020
+#define VMCS_EOI_EXIT3 0x00002022
+#define VMCS_EOI_EXIT(vector) (VMCS_EOI_EXIT0 + ((vector) / 64) * 2)
/* 64-bit read-only fields */
-#define VMCS_GUEST_PHYSICAL_ADDRESS 0x00002400
+#define VMCS_GUEST_PHYSICAL_ADDRESS 0x00002400
/* 64-bit guest-state fields */
-#define VMCS_LINK_POINTER 0x00002800
-#define VMCS_GUEST_IA32_DEBUGCTL 0x00002802
-#define VMCS_GUEST_IA32_PAT 0x00002804
-#define VMCS_GUEST_IA32_EFER 0x00002806
-#define VMCS_GUEST_IA32_PERF_GLOBAL_CTRL 0x00002808
-#define VMCS_GUEST_PDPTE0 0x0000280A
-#define VMCS_GUEST_PDPTE1 0x0000280C
-#define VMCS_GUEST_PDPTE2 0x0000280E
-#define VMCS_GUEST_PDPTE3 0x00002810
+#define VMCS_LINK_POINTER 0x00002800
+#define VMCS_GUEST_IA32_DEBUGCTL 0x00002802
+#define VMCS_GUEST_IA32_PAT 0x00002804
+#define VMCS_GUEST_IA32_EFER 0x00002806
+#define VMCS_GUEST_IA32_PERF_GLOBAL_CTRL 0x00002808
+#define VMCS_GUEST_PDPTE0 0x0000280A
+#define VMCS_GUEST_PDPTE1 0x0000280C
+#define VMCS_GUEST_PDPTE2 0x0000280E
+#define VMCS_GUEST_PDPTE3 0x00002810
/* 64-bit host-state fields */
-#define VMCS_HOST_IA32_PAT 0x00002C00
-#define VMCS_HOST_IA32_EFER 0x00002C02
-#define VMCS_HOST_IA32_PERF_GLOBAL_CTRL 0x00002C04
+#define VMCS_HOST_IA32_PAT 0x00002C00
+#define VMCS_HOST_IA32_EFER 0x00002C02
+#define VMCS_HOST_IA32_PERF_GLOBAL_CTRL 0x00002C04
/* 32-bit control fields */
-#define VMCS_PIN_BASED_CTLS 0x00004000
-#define VMCS_PRI_PROC_BASED_CTLS 0x00004002
-#define VMCS_EXCEPTION_BITMAP 0x00004004
-#define VMCS_PF_ERROR_MASK 0x00004006
-#define VMCS_PF_ERROR_MATCH 0x00004008
-#define VMCS_CR3_TARGET_COUNT 0x0000400A
-#define VMCS_EXIT_CTLS 0x0000400C
-#define VMCS_EXIT_MSR_STORE_COUNT 0x0000400E
-#define VMCS_EXIT_MSR_LOAD_COUNT 0x00004010
-#define VMCS_ENTRY_CTLS 0x00004012
-#define VMCS_ENTRY_MSR_LOAD_COUNT 0x00004014
-#define VMCS_ENTRY_INTR_INFO 0x00004016
-#define VMCS_ENTRY_EXCEPTION_ERROR 0x00004018
-#define VMCS_ENTRY_INST_LENGTH 0x0000401A
-#define VMCS_TPR_THRESHOLD 0x0000401C
-#define VMCS_SEC_PROC_BASED_CTLS 0x0000401E
-#define VMCS_PLE_GAP 0x00004020
-#define VMCS_PLE_WINDOW 0x00004022
+#define VMCS_PIN_BASED_CTLS 0x00004000
+#define VMCS_PRI_PROC_BASED_CTLS 0x00004002
+#define VMCS_EXCEPTION_BITMAP 0x00004004
+#define VMCS_PF_ERROR_MASK 0x00004006
+#define VMCS_PF_ERROR_MATCH 0x00004008
+#define VMCS_CR3_TARGET_COUNT 0x0000400A
+#define VMCS_EXIT_CTLS 0x0000400C
+#define VMCS_EXIT_MSR_STORE_COUNT 0x0000400E
+#define VMCS_EXIT_MSR_LOAD_COUNT 0x00004010
+#define VMCS_ENTRY_CTLS 0x00004012
+#define VMCS_ENTRY_MSR_LOAD_COUNT 0x00004014
+#define VMCS_ENTRY_INTR_INFO 0x00004016
+#define VMCS_ENTRY_EXCEPTION_ERROR 0x00004018
+#define VMCS_ENTRY_INST_LENGTH 0x0000401A
+#define VMCS_TPR_THRESHOLD 0x0000401C
+#define VMCS_SEC_PROC_BASED_CTLS 0x0000401E
+#define VMCS_PLE_GAP 0x00004020
+#define VMCS_PLE_WINDOW 0x00004022
/* 32-bit read-only data fields */
-#define VMCS_INSTRUCTION_ERROR 0x00004400
-#define VMCS_EXIT_REASON 0x00004402
-#define VMCS_EXIT_INTR_INFO 0x00004404
-#define VMCS_EXIT_INTR_ERRCODE 0x00004406
-#define VMCS_IDT_VECTORING_INFO 0x00004408
-#define VMCS_IDT_VECTORING_ERROR 0x0000440A
-#define VMCS_EXIT_INSTRUCTION_LENGTH 0x0000440C
-#define VMCS_EXIT_INSTRUCTION_INFO 0x0000440E
+#define VMCS_INSTRUCTION_ERROR 0x00004400
+#define VMCS_EXIT_REASON 0x00004402
+#define VMCS_EXIT_INTR_INFO 0x00004404
+#define VMCS_EXIT_INTR_ERRCODE 0x00004406
+#define VMCS_IDT_VECTORING_INFO 0x00004408
+#define VMCS_IDT_VECTORING_ERROR 0x0000440A
+#define VMCS_EXIT_INSTRUCTION_LENGTH 0x0000440C
+#define VMCS_EXIT_INSTRUCTION_INFO 0x0000440E
/* 32-bit guest-state fields */
-#define VMCS_GUEST_ES_LIMIT 0x00004800
-#define VMCS_GUEST_CS_LIMIT 0x00004802
-#define VMCS_GUEST_SS_LIMIT 0x00004804
-#define VMCS_GUEST_DS_LIMIT 0x00004806
-#define VMCS_GUEST_FS_LIMIT 0x00004808
-#define VMCS_GUEST_GS_LIMIT 0x0000480A
-#define VMCS_GUEST_LDTR_LIMIT 0x0000480C
-#define VMCS_GUEST_TR_LIMIT 0x0000480E
-#define VMCS_GUEST_GDTR_LIMIT 0x00004810
-#define VMCS_GUEST_IDTR_LIMIT 0x00004812
-#define VMCS_GUEST_ES_ACCESS_RIGHTS 0x00004814
-#define VMCS_GUEST_CS_ACCESS_RIGHTS 0x00004816
-#define VMCS_GUEST_SS_ACCESS_RIGHTS 0x00004818
-#define VMCS_GUEST_DS_ACCESS_RIGHTS 0x0000481A
-#define VMCS_GUEST_FS_ACCESS_RIGHTS 0x0000481C
-#define VMCS_GUEST_GS_ACCESS_RIGHTS 0x0000481E
-#define VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x00004820
-#define VMCS_GUEST_TR_ACCESS_RIGHTS 0x00004822
-#define VMCS_GUEST_INTERRUPTIBILITY 0x00004824
-#define VMCS_GUEST_ACTIVITY 0x00004826
-#define VMCS_GUEST_SMBASE 0x00004828
-#define VMCS_GUEST_IA32_SYSENTER_CS 0x0000482A
-#define VMCS_PREEMPTION_TIMER_VALUE 0x0000482E
+#define VMCS_GUEST_ES_LIMIT 0x00004800
+#define VMCS_GUEST_CS_LIMIT 0x00004802
+#define VMCS_GUEST_SS_LIMIT 0x00004804
+#define VMCS_GUEST_DS_LIMIT 0x00004806
+#define VMCS_GUEST_FS_LIMIT 0x00004808
+#define VMCS_GUEST_GS_LIMIT 0x0000480A
+#define VMCS_GUEST_LDTR_LIMIT 0x0000480C
+#define VMCS_GUEST_TR_LIMIT 0x0000480E
+#define VMCS_GUEST_GDTR_LIMIT 0x00004810
+#define VMCS_GUEST_IDTR_LIMIT 0x00004812
+#define VMCS_GUEST_ES_ACCESS_RIGHTS 0x00004814
+#define VMCS_GUEST_CS_ACCESS_RIGHTS 0x00004816
+#define VMCS_GUEST_SS_ACCESS_RIGHTS 0x00004818
+#define VMCS_GUEST_DS_ACCESS_RIGHTS 0x0000481A
+#define VMCS_GUEST_FS_ACCESS_RIGHTS 0x0000481C
+#define VMCS_GUEST_GS_ACCESS_RIGHTS 0x0000481E
+#define VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x00004820
+#define VMCS_GUEST_TR_ACCESS_RIGHTS 0x00004822
+#define VMCS_GUEST_INTERRUPTIBILITY 0x00004824
+#define VMCS_GUEST_ACTIVITY 0x00004826
+#define VMCS_GUEST_SMBASE 0x00004828
+#define VMCS_GUEST_IA32_SYSENTER_CS 0x0000482A
+#define VMCS_PREEMPTION_TIMER_VALUE 0x0000482E
/* 32-bit host state fields */
-#define VMCS_HOST_IA32_SYSENTER_CS 0x00004C00
+#define VMCS_HOST_IA32_SYSENTER_CS 0x00004C00
/* Natural Width control fields */
-#define VMCS_CR0_MASK 0x00006000
-#define VMCS_CR4_MASK 0x00006002
-#define VMCS_CR0_SHADOW 0x00006004
-#define VMCS_CR4_SHADOW 0x00006006
-#define VMCS_CR3_TARGET0 0x00006008
-#define VMCS_CR3_TARGET1 0x0000600A
-#define VMCS_CR3_TARGET2 0x0000600C
-#define VMCS_CR3_TARGET3 0x0000600E
+#define VMCS_CR0_MASK 0x00006000
+#define VMCS_CR4_MASK 0x00006002
+#define VMCS_CR0_SHADOW 0x00006004
+#define VMCS_CR4_SHADOW 0x00006006
+#define VMCS_CR3_TARGET0 0x00006008
+#define VMCS_CR3_TARGET1 0x0000600A
+#define VMCS_CR3_TARGET2 0x0000600C
+#define VMCS_CR3_TARGET3 0x0000600E
/* Natural Width read-only fields */
-#define VMCS_EXIT_QUALIFICATION 0x00006400
-#define VMCS_IO_RCX 0x00006402
-#define VMCS_IO_RSI 0x00006404
-#define VMCS_IO_RDI 0x00006406
-#define VMCS_IO_RIP 0x00006408
-#define VMCS_GUEST_LINEAR_ADDRESS 0x0000640A
+#define VMCS_EXIT_QUALIFICATION 0x00006400
+#define VMCS_IO_RCX 0x00006402
+#define VMCS_IO_RSI 0x00006404
+#define VMCS_IO_RDI 0x00006406
+#define VMCS_IO_RIP 0x00006408
+#define VMCS_GUEST_LINEAR_ADDRESS 0x0000640A
/* Natural Width guest-state fields */
-#define VMCS_GUEST_CR0 0x00006800
-#define VMCS_GUEST_CR3 0x00006802
-#define VMCS_GUEST_CR4 0x00006804
-#define VMCS_GUEST_ES_BASE 0x00006806
-#define VMCS_GUEST_CS_BASE 0x00006808
-#define VMCS_GUEST_SS_BASE 0x0000680A
-#define VMCS_GUEST_DS_BASE 0x0000680C
-#define VMCS_GUEST_FS_BASE 0x0000680E
-#define VMCS_GUEST_GS_BASE 0x00006810
-#define VMCS_GUEST_LDTR_BASE 0x00006812
-#define VMCS_GUEST_TR_BASE 0x00006814
-#define VMCS_GUEST_GDTR_BASE 0x00006816
-#define VMCS_GUEST_IDTR_BASE 0x00006818
-#define VMCS_GUEST_DR7 0x0000681A
-#define VMCS_GUEST_RSP 0x0000681C
-#define VMCS_GUEST_RIP 0x0000681E
-#define VMCS_GUEST_RFLAGS 0x00006820
-#define VMCS_GUEST_PENDING_DBG_EXCEPTIONS 0x00006822
-#define VMCS_GUEST_IA32_SYSENTER_ESP 0x00006824
-#define VMCS_GUEST_IA32_SYSENTER_EIP 0x00006826
+#define VMCS_GUEST_CR0 0x00006800
+#define VMCS_GUEST_CR3 0x00006802
+#define VMCS_GUEST_CR4 0x00006804
+#define VMCS_GUEST_ES_BASE 0x00006806
+#define VMCS_GUEST_CS_BASE 0x00006808
+#define VMCS_GUEST_SS_BASE 0x0000680A
+#define VMCS_GUEST_DS_BASE 0x0000680C
+#define VMCS_GUEST_FS_BASE 0x0000680E
+#define VMCS_GUEST_GS_BASE 0x00006810
+#define VMCS_GUEST_LDTR_BASE 0x00006812
+#define VMCS_GUEST_TR_BASE 0x00006814
+#define VMCS_GUEST_GDTR_BASE 0x00006816
+#define VMCS_GUEST_IDTR_BASE 0x00006818
+#define VMCS_GUEST_DR7 0x0000681A
+#define VMCS_GUEST_RSP 0x0000681C
+#define VMCS_GUEST_RIP 0x0000681E
+#define VMCS_GUEST_RFLAGS 0x00006820
+#define VMCS_GUEST_PENDING_DBG_EXCEPTIONS 0x00006822
+#define VMCS_GUEST_IA32_SYSENTER_ESP 0x00006824
+#define VMCS_GUEST_IA32_SYSENTER_EIP 0x00006826
/* Natural Width host-state fields */
-#define VMCS_HOST_CR0 0x00006C00
-#define VMCS_HOST_CR3 0x00006C02
-#define VMCS_HOST_CR4 0x00006C04
-#define VMCS_HOST_FS_BASE 0x00006C06
-#define VMCS_HOST_GS_BASE 0x00006C08
-#define VMCS_HOST_TR_BASE 0x00006C0A
-#define VMCS_HOST_GDTR_BASE 0x00006C0C
-#define VMCS_HOST_IDTR_BASE 0x00006C0E
-#define VMCS_HOST_IA32_SYSENTER_ESP 0x00006C10
-#define VMCS_HOST_IA32_SYSENTER_EIP 0x00006C12
-#define VMCS_HOST_RSP 0x00006C14
-#define VMCS_HOST_RIP 0x00006c16
+#define VMCS_HOST_CR0 0x00006C00
+#define VMCS_HOST_CR3 0x00006C02
+#define VMCS_HOST_CR4 0x00006C04
+#define VMCS_HOST_FS_BASE 0x00006C06
+#define VMCS_HOST_GS_BASE 0x00006C08
+#define VMCS_HOST_TR_BASE 0x00006C0A
+#define VMCS_HOST_GDTR_BASE 0x00006C0C
+#define VMCS_HOST_IDTR_BASE 0x00006C0E
+#define VMCS_HOST_IA32_SYSENTER_ESP 0x00006C10
+#define VMCS_HOST_IA32_SYSENTER_EIP 0x00006C12
+#define VMCS_HOST_RSP 0x00006C14
+#define VMCS_HOST_RIP 0x00006c16
/*
* VM instruction error numbers
*/
-#define VMRESUME_WITH_NON_LAUNCHED_VMCS 5
+#define VMRESUME_WITH_NON_LAUNCHED_VMCS 5
/*
* VMCS exit reasons
*/
-#define EXIT_REASON_EXCEPTION 0
-#define EXIT_REASON_EXT_INTR 1
-#define EXIT_REASON_TRIPLE_FAULT 2
-#define EXIT_REASON_INIT 3
-#define EXIT_REASON_SIPI 4
-#define EXIT_REASON_IO_SMI 5
-#define EXIT_REASON_SMI 6
-#define EXIT_REASON_INTR_WINDOW 7
-#define EXIT_REASON_NMI_WINDOW 8
-#define EXIT_REASON_TASK_SWITCH 9
-#define EXIT_REASON_CPUID 10
-#define EXIT_REASON_GETSEC 11
-#define EXIT_REASON_HLT 12
-#define EXIT_REASON_INVD 13
-#define EXIT_REASON_INVLPG 14
-#define EXIT_REASON_RDPMC 15
-#define EXIT_REASON_RDTSC 16
-#define EXIT_REASON_RSM 17
-#define EXIT_REASON_VMCALL 18
-#define EXIT_REASON_VMCLEAR 19
-#define EXIT_REASON_VMLAUNCH 20
-#define EXIT_REASON_VMPTRLD 21
-#define EXIT_REASON_VMPTRST 22
-#define EXIT_REASON_VMREAD 23
-#define EXIT_REASON_VMRESUME 24
-#define EXIT_REASON_VMWRITE 25
-#define EXIT_REASON_VMXOFF 26
-#define EXIT_REASON_VMXON 27
-#define EXIT_REASON_CR_ACCESS 28
-#define EXIT_REASON_DR_ACCESS 29
-#define EXIT_REASON_INOUT 30
-#define EXIT_REASON_RDMSR 31
-#define EXIT_REASON_WRMSR 32
-#define EXIT_REASON_INVAL_VMCS 33
-#define EXIT_REASON_INVAL_MSR 34
-#define EXIT_REASON_MWAIT 36
-#define EXIT_REASON_MTF 37
-#define EXIT_REASON_MONITOR 39
-#define EXIT_REASON_PAUSE 40
-#define EXIT_REASON_MCE_DURING_ENTRY 41
-#define EXIT_REASON_TPR 43
-#define EXIT_REASON_APIC_ACCESS 44
-#define EXIT_REASON_VIRTUALIZED_EOI 45
-#define EXIT_REASON_GDTR_IDTR 46
-#define EXIT_REASON_LDTR_TR 47
-#define EXIT_REASON_EPT_FAULT 48
-#define EXIT_REASON_EPT_MISCONFIG 49
-#define EXIT_REASON_INVEPT 50
-#define EXIT_REASON_RDTSCP 51
-#define EXIT_REASON_VMX_PREEMPT 52
-#define EXIT_REASON_INVVPID 53
-#define EXIT_REASON_WBINVD 54
-#define EXIT_REASON_XSETBV 55
-#define EXIT_REASON_APIC_WRITE 56
+#define EXIT_REASON_EXCEPTION 0
+#define EXIT_REASON_EXT_INTR 1
+#define EXIT_REASON_TRIPLE_FAULT 2
+#define EXIT_REASON_INIT 3
+#define EXIT_REASON_SIPI 4
+#define EXIT_REASON_IO_SMI 5
+#define EXIT_REASON_SMI 6
+#define EXIT_REASON_INTR_WINDOW 7
+#define EXIT_REASON_NMI_WINDOW 8
+#define EXIT_REASON_TASK_SWITCH 9
+#define EXIT_REASON_CPUID 10
+#define EXIT_REASON_GETSEC 11
+#define EXIT_REASON_HLT 12
+#define EXIT_REASON_INVD 13
+#define EXIT_REASON_INVLPG 14
+#define EXIT_REASON_RDPMC 15
+#define EXIT_REASON_RDTSC 16
+#define EXIT_REASON_RSM 17
+#define EXIT_REASON_VMCALL 18
+#define EXIT_REASON_VMCLEAR 19
+#define EXIT_REASON_VMLAUNCH 20
+#define EXIT_REASON_VMPTRLD 21
+#define EXIT_REASON_VMPTRST 22
+#define EXIT_REASON_VMREAD 23
+#define EXIT_REASON_VMRESUME 24
+#define EXIT_REASON_VMWRITE 25
+#define EXIT_REASON_VMXOFF 26
+#define EXIT_REASON_VMXON 27
+#define EXIT_REASON_CR_ACCESS 28
+#define EXIT_REASON_DR_ACCESS 29
+#define EXIT_REASON_INOUT 30
+#define EXIT_REASON_RDMSR 31
+#define EXIT_REASON_WRMSR 32
+#define EXIT_REASON_INVAL_VMCS 33
+#define EXIT_REASON_INVAL_MSR 34
+#define EXIT_REASON_MWAIT 36
+#define EXIT_REASON_MTF 37
+#define EXIT_REASON_MONITOR 39
+#define EXIT_REASON_PAUSE 40
+#define EXIT_REASON_MCE_DURING_ENTR 41
+#define EXIT_REASON_TPR 43
+#define EXIT_REASON_APIC_ACCESS 44
+#define EXIT_REASON_VIRTUALIZED_EOI 45
+#define EXIT_REASON_GDTR_IDTR 46
+#define EXIT_REASON_LDTR_TR 47
+#define EXIT_REASON_EPT_FAULT 48
+#define EXIT_REASON_EPT_MISCONFIG 49
+#define EXIT_REASON_INVEPT 50
+#define EXIT_REASON_RDTSCP 51
+#define EXIT_REASON_VMX_PREEMPT 52
+#define EXIT_REASON_INVVPID 53
+#define EXIT_REASON_WBINVD 54
+#define EXIT_REASON_XSETBV 55
+#define EXIT_REASON_APIC_WRITE 56
/*
* NMI unblocking due to IRET.
*
* Applies to VM-exits due to hardware exception or EPT fault.
*/
-#define EXIT_QUAL_NMIUDTI (1 << 12)
+#define EXIT_QUAL_NMIUDTI (1 << 12)
/*
* VMCS interrupt information fields
*/
-#define VMCS_INTR_VALID (1U << 31)
-#define VMCS_INTR_T_MASK 0x700 /* Interruption-info type */
-#define VMCS_INTR_T_HWINTR (0 << 8)
-#define VMCS_INTR_T_NMI (2 << 8)
-#define VMCS_INTR_T_HWEXCEPTION (3 << 8)
-#define VMCS_INTR_T_SWINTR (4 << 8)
-#define VMCS_INTR_T_PRIV_SWEXCEPTION (5 << 8)
-#define VMCS_INTR_T_SWEXCEPTION (6 << 8)
-#define VMCS_INTR_DEL_ERRCODE (1 << 11)
+#define VMCS_INTR_VALID (1U << 31)
+#define VMCS_INTR_T_MASK 0x700 /* Interruption-info type */
+#define VMCS_INTR_T_HWINTR (0 << 8)
+#define VMCS_INTR_T_NMI (2 << 8)
+#define VMCS_INTR_T_HWEXCEPTION (3 << 8)
+#define VMCS_INTR_T_SWINTR (4 << 8)
+#define VMCS_INTR_T_PRIV_SWEXCEPTION (5 << 8)
+#define VMCS_INTR_T_SWEXCEPTION (6 << 8)
+#define VMCS_INTR_DEL_ERRCODE (1 << 11)
/*
* VMCS IDT-Vectoring information fields
*/
-#define VMCS_IDT_VEC_VALID (1U << 31)
-#define VMCS_IDT_VEC_TYPE 0x700
-#define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11)
-#define VMCS_IDT_VEC_HWINTR (0 << 8)
-#define VMCS_IDT_VEC_NMI (2 << 8)
-#define VMCS_IDT_VEC_HWEXCEPTION (3 << 8)
-#define VMCS_IDT_VEC_SWINTR (4 << 8)
+#define VMCS_IDT_VEC_VALID (1U << 31)
+#define VMCS_IDT_VEC_TYPE 0x700
+#define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11)
+#define VMCS_IDT_VEC_HWINTR (0 << 8)
+#define VMCS_IDT_VEC_NMI (2 << 8)
+#define VMCS_IDT_VEC_HWEXCEPTION (3 << 8)
+#define VMCS_IDT_VEC_SWINTR (4 << 8)
/*
* VMCS Guest interruptibility field
*/
-#define VMCS_INTERRUPTIBILITY_STI_BLOCKING (1 << 0)
-#define VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING (1 << 1)
-#define VMCS_INTERRUPTIBILITY_SMI_BLOCKING (1 << 2)
-#define VMCS_INTERRUPTIBILITY_NMI_BLOCKING (1 << 3)
+#define VMCS_INTERRUPTIBILITY_STI_BLOCKING (1 << 0)
+#define VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING (1 << 1)
+#define VMCS_INTERRUPTIBILITY_SMI_BLOCKING (1 << 2)
+#define VMCS_INTERRUPTIBILITY_NMI_BLOCKING (1 << 3)
/*
* Exit qualification for EXIT_REASON_INVAL_VMCS
*/
-#define EXIT_QUAL_NMI_WHILE_STI_BLOCKING 3
+#define EXIT_QUAL_NMI_WHILE_STI_BLOCKING 3
/*
* Exit qualification for EPT violation
*/
-#define EPT_VIOLATION_DATA_READ (1UL << 0)
-#define EPT_VIOLATION_DATA_WRITE (1UL << 1)
-#define EPT_VIOLATION_INST_FETCH (1UL << 2)
-#define EPT_VIOLATION_GPA_READABLE (1UL << 3)
-#define EPT_VIOLATION_GPA_WRITEABLE (1UL << 4)
-#define EPT_VIOLATION_GPA_EXECUTABLE (1UL << 5)
-#define EPT_VIOLATION_GLA_VALID (1UL << 7)
-#define EPT_VIOLATION_XLAT_VALID (1UL << 8)
+#define EPT_VIOLATION_DATA_READ (1UL << 0)
+#define EPT_VIOLATION_DATA_WRITE (1UL << 1)
+#define EPT_VIOLATION_INST_FETCH (1UL << 2)
+#define EPT_VIOLATION_GPA_READABLE (1UL << 3)
+#define EPT_VIOLATION_GPA_WRITEABLE (1UL << 4)
+#define EPT_VIOLATION_GPA_EXECUTABLE (1UL << 5)
+#define EPT_VIOLATION_GLA_VALID (1UL << 7)
+#define EPT_VIOLATION_XLAT_VALID (1UL << 8)
/*
* Exit qualification for APIC-access VM exit
*/
-#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
-#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
+#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
+#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
/*
* Exit qualification for APIC-write VM exit
*/
-#define APIC_WRITE_OFFSET(qual) ((qual) & 0xFFF)
+#define APIC_WRITE_OFFSET(qual) ((qual) & 0xFFF)
-#define VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING (1 << 2)
-#define VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET (1 << 3)
-#define VMCS_PRI_PROC_BASED_CTLS_HLT (1 << 7)
+#define VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING (1 << 2)
+#define VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET (1 << 3)
+#define VMCS_PRI_PROC_BASED_CTLS_HLT (1 << 7)
#define VMCS_PRI_PROC_BASED_CTLS_MWAIT (1 << 10)
#define VMCS_PRI_PROC_BASED_CTLS_TSC (1 << 12)
#define VMCS_PRI_PROC_BASED_CTLS_CR8_LOAD (1 << 19)
@@ -359,10 +359,10 @@
#define VMCS_PRI_PROC_BASED2_CTLS_X2APIC (1 << 4)
enum task_switch_reason {
- TSR_CALL,
- TSR_IRET,
+ TSR_CALL,
+ TSR_IRET,
TSR_JMP,
- TSR_IDT_GATE, /* task gate in IDT */
+ TSR_IDT_GATE, /* task gate in IDT */
};
#endif
diff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf-utils/vmx.h
index 8a080e6777..d086c8d253 100644
--- a/target/i386/hvf-utils/vmx.h
+++ b/target/i386/hvf-utils/vmx.h
@@ -31,45 +31,45 @@
#include "exec/address-spaces.h"
-static uint64_t inline rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg)
+static inline uint64_t rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg)
{
- uint64_t v;
+ uint64_t v;
- if (hv_vcpu_read_register(vcpu, reg, &v)) {
- abort();
- }
+ if (hv_vcpu_read_register(vcpu, reg, &v)) {
+ abort();
+ }
- return v;
+ return v;
}
/* write GPR */
-static void inline wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v)
+static inline void wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v)
{
- if (hv_vcpu_write_register(vcpu, reg, v)) {
- abort();
- }
+ if (hv_vcpu_write_register(vcpu, reg, v)) {
+ abort();
+ }
}
/* read VMCS field */
-static uint64_t inline rvmcs(hv_vcpuid_t vcpu, uint32_t field)
+static inline uint64_t rvmcs(hv_vcpuid_t vcpu, uint32_t field)
{
- uint64_t v;
+ uint64_t v;
- hv_vmx_vcpu_read_vmcs(vcpu, field, &v);
+ hv_vmx_vcpu_read_vmcs(vcpu, field, &v);
- return v;
+ return v;
}
/* write VMCS field */
-static void inline wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v)
+static inline void wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v)
{
- hv_vmx_vcpu_write_vmcs(vcpu, field, v);
+ hv_vmx_vcpu_write_vmcs(vcpu, field, v);
}
/* desired control word constrained by hardware/hypervisor capabilities */
-static uint64_t inline cap2ctrl(uint64_t cap, uint64_t ctrl)
+static inline uint64_t cap2ctrl(uint64_t cap, uint64_t ctrl)
{
- return (ctrl | (cap & 0xffffffff)) & (cap >> 32);
+ return (ctrl | (cap & 0xffffffff)) & (cap >> 32);
}
#define VM_ENTRY_GUEST_LMA (1LL << 9)
@@ -91,11 +91,14 @@ static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
efer |= EFER_LMA;
wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
- wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | VM_ENTRY_GUEST_LMA);
+ wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) |
+ VM_ENTRY_GUEST_LMA);
uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS);
- if ((efer & EFER_LME) && (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
- wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS);
+ if ((efer & EFER_LME) &&
+ (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
+ wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS,
+ (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS);
}
}
@@ -110,39 +113,45 @@ static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
}
-static void inline macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
+static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
{
int i;
uint64_t pdpte[4] = {0, 0, 0, 0};
uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER);
uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0);
- if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & EFER_LME))
- address_space_rw(&address_space_memory, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
+ if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) &&
+ !(efer & EFER_LME)) {
+ address_space_rw(&address_space_memory,
+ rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
MEMTXATTRS_UNSPECIFIED,
(uint8_t *)pdpte, 32, 0);
+ }
- for (i = 0; i < 4; i++)
+ for (i = 0; i < 4; i++) {
wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
+ }
wvmcs(vcpu, VMCS_CR0_MASK, CR0_CD | CR0_NE | CR0_PG);
wvmcs(vcpu, VMCS_CR0_SHADOW, cr0);
cr0 &= ~CR0_CD;
- wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE| CR0_ET);
+ wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE | CR0_ET);
if (efer & EFER_LME) {
- if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG))
- enter_long_mode(vcpu, cr0, efer);
- if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG))
+ if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG)) {
+ enter_long_mode(vcpu, cr0, efer);
+ }
+ if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG)) {
exit_long_mode(vcpu, cr0, efer);
+ }
}
hv_vcpu_invalidate_tlb(vcpu);
hv_vcpu_flush(vcpu);
}
-static void inline macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
+static inline void macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
{
uint64_t guest_cr4 = cr4 | CR4_VMXE;
@@ -153,7 +162,7 @@ static void inline macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
hv_vcpu_flush(vcpu);
}
-static void inline macvm_set_rip(CPUState *cpu, uint64_t rip)
+static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)
{
uint64_t val;
@@ -162,39 +171,44 @@ static void inline macvm_set_rip(CPUState *cpu, uint64_t rip)
/* after moving forward in rip, we need to clean INTERRUPTABILITY */
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
- if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING))
+ if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
+ VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY,
- val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
+ val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
+ VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
+ }
}
-static void inline vmx_clear_nmi_blocking(CPUState *cpu)
+static inline void vmx_clear_nmi_blocking(CPUState *cpu)
{
uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
}
-static void inline vmx_set_nmi_blocking(CPUState *cpu)
+static inline void vmx_set_nmi_blocking(CPUState *cpu)
{
uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
}
-static void inline vmx_set_nmi_window_exiting(CPUState *cpu)
+static inline void vmx_set_nmi_window_exiting(CPUState *cpu)
{
uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val |
+ VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
}
-static void inline vmx_clear_nmi_window_exiting(CPUState *cpu)
+static inline void vmx_clear_nmi_window_exiting(CPUState *cpu)
{
uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val &
+ ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
}
#endif
diff --git a/target/i386/hvf-utils/x86.c b/target/i386/hvf-utils/x86.c
index e3db2c9c8b..07eb5a8586 100644
--- a/target/i386/hvf-utils/x86.c
+++ b/target/i386/hvf-utils/x86.c
@@ -26,35 +26,38 @@
#include "x86_mmu.h"
#include "x86_descr.h"
-static uint32_t x86_segment_access_rights(struct x86_segment_descriptor *var)
+/* static uint32_t x86_segment_access_rights(struct x86_segment_descriptor *var)
{
- uint32_t ar;
-
- if (!var->p) {
- ar = 1 << 16;
- return ar;
- }
-
- ar = var->type & 15;
- ar |= (var->s & 1) << 4;
- ar |= (var->dpl & 3) << 5;
- ar |= (var->p & 1) << 7;
- ar |= (var->avl & 1) << 12;
- ar |= (var->l & 1) << 13;
- ar |= (var->db & 1) << 14;
- ar |= (var->g & 1) << 15;
- return ar;
-}
-
-bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
+ uint32_t ar;
+
+ if (!var->p) {
+ ar = 1 << 16;
+ return ar;
+ }
+
+ ar = var->type & 15;
+ ar |= (var->s & 1) << 4;
+ ar |= (var->dpl & 3) << 5;
+ ar |= (var->p & 1) << 7;
+ ar |= (var->avl & 1) << 12;
+ ar |= (var->l & 1) << 13;
+ ar |= (var->db & 1) << 14;
+ ar |= (var->g & 1) << 15;
+ return ar;
+}*/
+
+bool x86_read_segment_descriptor(struct CPUState *cpu,
+ struct x86_segment_descriptor *desc,
+ x68_segment_selector sel)
{
addr_t base;
uint32_t limit;
ZERO_INIT(*desc);
- // valid gdt descriptors start from index 1
- if (!sel.index && GDT_SEL == sel.ti)
+ /* valid gdt descriptors start from index 1 */
+ if (!sel.index && GDT_SEL == sel.ti) {
return false;
+ }
if (GDT_SEL == sel.ti) {
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);
@@ -64,18 +67,21 @@ bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descri
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);
}
- if (sel.index * 8 >= limit)
+ if (sel.index * 8 >= limit) {
return false;
+ }
vmx_read_mem(cpu, desc, base + sel.index * 8, sizeof(*desc));
return true;
}
-bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
+bool x86_write_segment_descriptor(struct CPUState *cpu,
+ struct x86_segment_descriptor *desc,
+ x68_segment_selector sel)
{
addr_t base;
uint32_t limit;
-
+
if (GDT_SEL == sel.ti) {
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
@@ -83,23 +89,24 @@ bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descr
base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);
limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);
}
-
+
if (sel.index * 8 >= limit) {
- printf("%s: gdt limit\n", __FUNCTION__);
+ printf("%s: gdt limit\n", __func__);
return false;
}
vmx_write_mem(cpu, base + sel.index * 8, desc, sizeof(*desc));
return true;
}
-bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate)
+bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
+ int gate)
{
addr_t base = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE);
uint32_t limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT);
ZERO_INIT(*idt_desc);
if (gate * 8 >= limit) {
- printf("%s: idt limit\n", __FUNCTION__);
+ printf("%s: idt limit\n", __func__);
return false;
}
@@ -120,7 +127,7 @@ bool x86_is_real(struct CPUState *cpu)
bool x86_is_v8086(struct CPUState *cpu)
{
- return (x86_is_protected(cpu) && (RFLAGS(cpu) & RFLAGS_VM));
+ return x86_is_protected(cpu) && (RFLAGS(cpu) & RFLAGS_VM);
}
bool x86_is_long_mode(struct CPUState *cpu)
@@ -153,17 +160,18 @@ addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg)
return vmx_read_segment_base(cpu, seg) + addr;
}
-addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg)
+addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size,
+ x86_reg_segment seg)
{
switch (size) {
- case 2:
- addr = (uint16_t)addr;
- break;
- case 4:
- addr = (uint32_t)addr;
- break;
- default:
- break;
+ case 2:
+ addr = (uint16_t)addr;
+ break;
+ case 4:
+ addr = (uint32_t)addr;
+ break;
+ default:
+ break;
}
return linear_addr(cpu, addr, seg);
}
diff --git a/target/i386/hvf-utils/x86.h b/target/i386/hvf-utils/x86.h
index 5dffdd6568..435b49ae04 100644
--- a/target/i386/hvf-utils/x86.h
+++ b/target/i386/hvf-utils/x86.h
@@ -25,26 +25,26 @@
#include "qemu-common.h"
#include "x86_flags.h"
-// exceptions
+/* exceptions */
typedef enum x86_exception {
- EXCEPTION_DE, // divide error
- EXCEPTION_DB, // debug fault
- EXCEPTION_NMI, // non-maskable interrupt
- EXCEPTION_BP, // breakpoint trap
- EXCEPTION_OF, // overflow trap
- EXCEPTION_BR, // boundary range exceeded fault
- EXCEPTION_UD, // undefined opcode
- EXCEPTION_NM, // device not available
- EXCEPTION_DF, // double fault
- EXCEPTION_RSVD, // not defined
- EXCEPTION_TS, // invalid TSS fault
- EXCEPTION_NP, // not present fault
- EXCEPTION_GP, // general protection fault
- EXCEPTION_PF, // page fault
- EXCEPTION_RSVD2, // not defined
+ EXCEPTION_DE, /* divide error */
+ EXCEPTION_DB, /* debug fault */
+ EXCEPTION_NMI, /* non-maskable interrupt */
+ EXCEPTION_BP, /* breakpoint trap */
+ EXCEPTION_OF, /* overflow trap */
+ EXCEPTION_BR, /* boundary range exceeded fault */
+ EXCEPTION_UD, /* undefined opcode */
+ EXCEPTION_NM, /* device not available */
+ EXCEPTION_DF, /* double fault */
+ EXCEPTION_RSVD, /* not defined */
+ EXCEPTION_TS, /* invalid TSS fault */
+ EXCEPTION_NP, /* not present fault */
+ EXCEPTION_GP, /* general protection fault */
+ EXCEPTION_PF, /* page fault */
+ EXCEPTION_RSVD2, /* not defined */
} x86_exception;
-// general purpose regs
+/* general purpose regs */
typedef enum x86_reg_name {
REG_RAX = 0,
REG_RCX = 1,
@@ -64,7 +64,7 @@ typedef enum x86_reg_name {
REG_R15 = 15,
} x86_reg_name;
-// segment regs
+/* segment regs */
typedef enum x86_reg_segment {
REG_SEG_ES = 0,
REG_SEG_CS = 1,
@@ -76,24 +76,23 @@ typedef enum x86_reg_segment {
REG_SEG_TR = 7,
} x86_reg_segment;
-typedef struct x86_register
-{
+typedef struct x86_register {
union {
struct {
- uint64_t rrx; // full 64 bit
+ uint64_t rrx; /* full 64 bit */
};
struct {
- uint32_t erx; // low 32 bit part
+ uint32_t erx; /* low 32 bit part */
uint32_t hi32_unused1;
};
struct {
- uint16_t rx; // low 16 bit part
+ uint16_t rx; /* low 16 bit part */
uint16_t hi16_unused1;
uint32_t hi32_unused2;
};
struct {
- uint8_t lx; // low 8 bit part
- uint8_t hx; // high 8 bit
+ uint8_t lx; /* low 8 bit part */
+ uint8_t hx; /* high 8 bit */
uint16_t hi16_unused2;
uint32_t hi32_unused3;
};
@@ -120,7 +119,7 @@ typedef enum x86_rflags {
RFLAGS_ID = (1L << 21),
} x86_rflags;
-// rflags register
+/* rflags register */
typedef struct x86_reg_flags {
union {
struct {
@@ -205,7 +204,7 @@ typedef enum x86_reg_cr4 {
CR4_SMEP = (1L << 20),
} x86_reg_cr4;
-// 16 bit Task State Segment
+/* 16 bit Task State Segment */
typedef struct x86_tss_segment16 {
uint16_t link;
uint16_t sp0;
@@ -231,9 +230,8 @@ typedef struct x86_tss_segment16 {
uint16_t ldtr;
} __attribute__((packed)) x86_tss_segment16;
-// 32 bit Task State Segment
-typedef struct x86_tss_segment32
-{
+/* 32 bit Task State Segment */
+typedef struct x86_tss_segment32 {
uint32_t prev_tss;
uint32_t esp0;
uint32_t ss0;
@@ -263,9 +261,8 @@ typedef struct x86_tss_segment32
uint16_t iomap_base;
} __attribute__ ((__packed__)) x86_tss_segment32;
-// 64 bit Task State Segment
-typedef struct x86_tss_segment64
-{
+/* 64 bit Task State Segment */
+typedef struct x86_tss_segment64 {
uint32_t unused;
uint64_t rsp0;
uint64_t rsp1;
@@ -283,7 +280,7 @@ typedef struct x86_tss_segment64
uint16_t iomap_base;
} __attribute__ ((__packed__)) x86_tss_segment64;
-// segment descriptors
+/* segment descriptors */
typedef struct x86_segment_descriptor {
uint64_t limit0:16;
uint64_t base0:16;
@@ -305,7 +302,8 @@ static inline uint32_t x86_segment_base(x86_segment_descriptor *desc)
return (uint32_t)((desc->base2 << 24) | (desc->base1 << 16) | desc->base0);
}
-static inline void x86_set_segment_base(x86_segment_descriptor *desc, uint32_t base)
+static inline void x86_set_segment_base(x86_segment_descriptor *desc,
+ uint32_t base)
{
desc->base2 = base >> 24;
desc->base1 = (base >> 16) & 0xff;
@@ -315,12 +313,14 @@ static inline void x86_set_segment_base(x86_segment_descriptor *desc, uint32_t b
static inline uint32_t x86_segment_limit(x86_segment_descriptor *desc)
{
uint32_t limit = (uint32_t)((desc->limit1 << 16) | desc->limit0);
- if (desc->g)
+ if (desc->g) {
return (limit << 12) | 0xfff;
+ }
return limit;
}
-static inline void x86_set_segment_limit(x86_segment_descriptor *desc, uint32_t limit)
+static inline void x86_set_segment_limit(x86_segment_descriptor *desc,
+ uint32_t limit)
{
desc->limit0 = limit & 0xffff;
desc->limit1 = limit >> 16;
@@ -356,11 +356,11 @@ typedef struct x68_segment_selector {
};
} __attribute__ ((__packed__)) x68_segment_selector;
-// Definition of hvf_x86_state is here
+/* Definition of hvf_x86_state is here */
struct hvf_x86_state {
int hlt;
uint64_t init_tsc;
-
+
int interruptable;
uint64_t exp_rip;
uint64_t fetch_rip;
@@ -370,7 +370,7 @@ struct hvf_x86_state {
struct lazy_flags lflags;
struct x86_efer efer;
uint8_t mmio_buf[4096];
- uint8_t* apic_page;
+ uint8_t *apic_page;
};
/*
@@ -380,7 +380,7 @@ struct hvf_xsave_buf {
uint32_t data[1024];
};
-// useful register access macros
+/* useful register access macros */
#define RIP(cpu) (cpu->hvf_x86->rip)
#define EIP(cpu) ((uint32_t)cpu->hvf_x86->rip)
#define RFLAGS(cpu) (cpu->hvf_x86->rflags.rflags)
@@ -436,13 +436,18 @@ struct hvf_xsave_buf {
#define DH(cpu) RH(cpu, REG_RDX)
#define BH(cpu) RH(cpu, REG_RBX)
-// deal with GDT/LDT descriptors in memory
-bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
-bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
+/* deal with GDT/LDT descriptors in memory */
+bool x86_read_segment_descriptor(struct CPUState *cpu,
+ struct x86_segment_descriptor *desc,
+ x68_segment_selector sel);
+bool x86_write_segment_descriptor(struct CPUState *cpu,
+ struct x86_segment_descriptor *desc,
+ x68_segment_selector sel);
-bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate);
+bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc,
+ int gate);
-// helpers
+/* helpers */
bool x86_is_protected(struct CPUState *cpu);
bool x86_is_real(struct CPUState *cpu);
bool x86_is_v8086(struct CPUState *cpu);
@@ -452,19 +457,20 @@ bool x86_is_paging_mode(struct CPUState *cpu);
bool x86_is_pae_enabled(struct CPUState *cpu);
addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg);
-addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg);
+addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size,
+ x86_reg_segment seg);
addr_t linear_rip(struct CPUState *cpu, addr_t rip);
static inline uint64_t rdtscp(void)
{
uint64_t tsc;
- __asm__ __volatile__("rdtscp; " // serializing read of tsc
- "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up
- "or %%rdx,%%rax" // and or onto rax
- : "=a"(tsc) // output to tsc variable
+ __asm__ __volatile__("rdtscp; " /* serializing read of tsc */
+ "shl $32,%%rdx; " /* shift higher 32 bits stored in rdx up */
+ "or %%rdx,%%rax" /* and or onto rax */
+ : "=a"(tsc) /* output to tsc variable */
:
- : "%rcx", "%rdx"); // rcx and rdx are clobbered
-
+ : "%rcx", "%rdx"); /* rcx and rdx are clobbered */
+
return tsc;
}
diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf-utils/x86_cpuid.c
index e496cf001c..5d63bca8fd 100644
--- a/target/i386/hvf-utils/x86_cpuid.c
+++ b/target/i386/hvf-utils/x86_cpuid.c
@@ -41,10 +41,10 @@ struct x86_cpuid builtin_cpus[] = {
.model = 3,
.stepping = 3,
.features = PPRO_FEATURES,
- .ext_features = /*CPUID_EXT_SSE3 |*/ CPUID_EXT_POPCNT, CPUID_MTRR | CPUID_CLFLUSH,
- CPUID_PSE36,
+ .ext_features = /*CPUID_EXT_SSE3 |*/ CPUID_EXT_POPCNT, CPUID_MTRR |
+ CPUID_CLFLUSH, CPUID_PSE36,
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .ext3_features = 0,//CPUID_EXT3_LAHF_LM,
+ .ext3_features = 0, /* CPUID_EXT3_LAHF_LM, */
.xlevel = 0x80000004,
.model_id = "vmx32",
},
@@ -92,14 +92,15 @@ struct x86_cpuid builtin_cpus[] = {
},
};
-static struct x86_cpuid *_cpuid = NULL;
+static struct x86_cpuid *_cpuid;
-void init_cpuid(struct CPUState* cpu)
+void init_cpuid(struct CPUState *cpu)
{
- _cpuid = &builtin_cpus[2]; // core2duo
+ _cpuid = &builtin_cpus[2]; /* core2duo */
}
-void get_cpuid_func(struct CPUState* cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
+void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax,
+ uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
{
uint32_t h_rax, h_rbx, h_rcx, h_rdx;
host_cpuid(func, cnt, &h_rax, &h_rbx, &h_rcx, &h_rdx);
@@ -107,164 +108,172 @@ void get_cpuid_func(struct CPUState* cpu, int func, int cnt, uint32_t *eax, uint
*eax = *ebx = *ecx = *edx = 0;
- switch(func) {
- case 0:
- *eax = _cpuid->level;
- *ebx = _cpuid->vendor1;
- *edx = _cpuid->vendor2;
- *ecx = _cpuid->vendor3;
- break;
- case 1:
- *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
- *ebx = (apic_id << 24) | (h_rbx & 0x00ffffff);
- *ecx = h_rcx;
- *edx = h_rdx;
+ switch (func) {
+ case 0:
+ *eax = _cpuid->level;
+ *ebx = _cpuid->vendor1;
+ *edx = _cpuid->vendor2;
+ *ecx = _cpuid->vendor3;
+ break;
+ case 1:
+ *eax = h_rax;/*_cpuid->stepping | (_cpuid->model << 3) |
+ (_cpuid->family << 6); */
+ *ebx = (apic_id << 24) | (h_rbx & 0x00ffffff);
+ *ecx = h_rcx;
+ *edx = h_rdx;
- if (cpu->nr_cores * cpu->nr_threads > 1) {
- *ebx |= (cpu->nr_cores * cpu->nr_threads) << 16;
- *edx |= 1 << 28; /* Enable Hyper-Threading */
- }
+ if (cpu->nr_cores * cpu->nr_threads > 1) {
+ *ebx |= (cpu->nr_cores * cpu->nr_threads) << 16;
+ *edx |= 1 << 28; /* Enable Hyper-Threading */
+ }
- *ecx = *ecx & ~(CPUID_EXT_OSXSAVE | CPUID_EXT_MONITOR | CPUID_EXT_X2APIC |
- CPUID_EXT_VMX | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_TM2 | CPUID_EXT_PCID |
- CPUID_EXT_EST | CPUID_EXT_SSE42 | CPUID_EXT_SSE41);
- *ecx |= CPUID_EXT_HYPERVISOR;
- break;
- case 2:
- /* cache info: needed for Pentium Pro compatibility */
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 4:
- /* cache info: needed for Core compatibility */
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 5:
- /* mwait info: needed for Core compatibility */
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 6:
- /* Thermal and Power Leaf */
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 7:
- *eax = h_rax;
- *ebx = h_rbx & ~(CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF | CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
- CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INVPCID);
- *ecx = h_rcx & ~(CPUID_7_0_ECX_AVX512BMI);
- *edx = h_rdx;
- break;
- case 9:
- /* Direct Cache Access Information Leaf */
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 0xA:
- /* Architectural Performance Monitoring Leaf */
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 0xB:
- /* CPU Topology Leaf */
- *eax = 0;
- *ebx = 0; /* Means that we don't support this leaf */
- *ecx = 0;
- *edx = 0;
- break;
- case 0xD:
- *eax = h_rax;
- if (!cnt)
- *eax &= (XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK);
- if (1 == cnt)
- *eax &= (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC);
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 0x80000000:
- *eax = _cpuid->xlevel;
- *ebx = _cpuid->vendor1;
- *edx = _cpuid->vendor2;
- *ecx = _cpuid->vendor3;
- break;
- case 0x80000001:
- *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
- *ebx = 0;
- *ecx = _cpuid->ext3_features & h_rcx;
- *edx = _cpuid->ext2_features & h_rdx;
- break;
- case 0x80000002:
- case 0x80000003:
- case 0x80000004:
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 0x80000005:
- /* cache info (L1 cache) */
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 0x80000006:
- /* cache info (L2 cache) */
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = h_rcx;
- *edx = h_rdx;
- break;
- case 0x80000007:
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0; /* Note - We disable invariant TSC (bit 8) in purpose */
- break;
- case 0x80000008:
- /* virtual & phys address size in low 2 bytes. */
- *eax = h_rax;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 0x8000000A:
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- case 0x80000019:
- *eax = h_rax;
- *ebx = h_rbx;
- *ecx = 0;
- *edx = 0;
- case 0xC0000000:
- *eax = _cpuid->xlevel2;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
- default:
- *eax = 0;
- *ebx = 0;
- *ecx = 0;
- *edx = 0;
- break;
+ *ecx = *ecx & ~(CPUID_EXT_OSXSAVE | CPUID_EXT_MONITOR |
+ CPUID_EXT_X2APIC | CPUID_EXT_VMX |
+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_TM2 |
+ CPUID_EXT_PCID | CPUID_EXT_EST | CPUID_EXT_SSE42 |
+ CPUID_EXT_SSE41);
+ *ecx |= CPUID_EXT_HYPERVISOR;
+ break;
+ case 2:
+ /* cache info: needed for Pentium Pro compatibility */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 4:
+ /* cache info: needed for Core compatibility */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 5:
+ /* mwait info: needed for Core compatibility */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 6:
+ /* Thermal and Power Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 7:
+ *eax = h_rax;
+ *ebx = h_rbx & ~(CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |
+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |
+ CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INVPCID);
+ *ecx = h_rcx & ~(CPUID_7_0_ECX_AVX512BMI);
+ *edx = h_rdx;
+ break;
+ case 9:
+ /* Direct Cache Access Information Leaf */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0xA:
+ /* Architectural Performance Monitoring Leaf */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0xB:
+ /* CPU Topology Leaf */
+ *eax = 0;
+ *ebx = 0; /* Means that we don't support this leaf */
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0xD:
+ *eax = h_rax;
+ if (!cnt) {
+ *eax &= (XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK);
+ }
+ if (1 == cnt) {
+ *eax &= (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC);
+ }
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000000:
+ *eax = _cpuid->xlevel;
+ *ebx = _cpuid->vendor1;
+ *edx = _cpuid->vendor2;
+ *ecx = _cpuid->vendor3;
+ break;
+ case 0x80000001:
+ *eax = h_rax;/*_cpuid->stepping | (_cpuid->model << 3) |
+ (_cpuid->family << 6);*/
+ *ebx = 0;
+ *ecx = _cpuid->ext3_features & h_rcx;
+ *edx = _cpuid->ext2_features & h_rdx;
+ break;
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000005:
+ /* cache info (L1 cache) */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000006:
+ /* cache info (L2 cache) */
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = h_rcx;
+ *edx = h_rdx;
+ break;
+ case 0x80000007:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0; /* Note - We disable invariant TSC (bit 8) in purpose */
+ break;
+ case 0x80000008:
+ /* virtual & phys address size in low 2 bytes. */
+ *eax = h_rax;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0x8000000A:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ case 0x80000019:
+ *eax = h_rax;
+ *ebx = h_rbx;
+ *ecx = 0;
+ *edx = 0;
+ case 0xC0000000:
+ *eax = _cpuid->xlevel2;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
+ default:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ break;
}
}
diff --git a/target/i386/hvf-utils/x86_cpuid.h b/target/i386/hvf-utils/x86_cpuid.h
index 02f2f115b0..ab10b84b61 100644
--- a/target/i386/hvf-utils/x86_cpuid.h
+++ b/target/i386/hvf-utils/x86_cpuid.h
@@ -35,7 +35,7 @@ struct x86_cpuid {
uint32_t features, ext_features, ext2_features, ext3_features;
uint32_t kvm_features, svm_features;
uint32_t xlevel;
- char model_id[48];
+ char model_id[50];
int vendor_override;
uint32_t flags;
uint32_t xlevel2;
@@ -44,8 +44,9 @@ struct x86_cpuid {
struct CPUState;
-void init_cpuid(struct CPUState* cpu);
-void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
+void init_cpuid(struct CPUState *cpu);
+void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax,
+ uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
#endif /* __CPUID_H__ */
diff --git a/target/i386/hvf-utils/x86_decode.c b/target/i386/hvf-utils/x86_decode.c
index b4d8e22449..4faf82f721 100644
--- a/target/i386/hvf-utils/x86_decode.c
+++ b/target/i386/hvf-utils/x86_decode.c
@@ -29,9 +29,11 @@
static void decode_invalid(CPUState *cpu, struct x86_decode *decode)
{
- printf("%llx: failed to decode instruction ", cpu->hvf_x86->fetch_rip - decode->len);
- for (int i = 0; i < decode->opcode_len; i++)
+ printf("%llx: failed to decode instruction ", cpu->hvf_x86->fetch_rip -
+ decode->len);
+ for (int i = 0; i < decode->opcode_len; i++) {
printf("%x ", decode->opcode[i]);
+ }
printf("\n");
VM_PANIC("decoder failed\n");
}
@@ -39,43 +41,44 @@ static void decode_invalid(CPUState *cpu, struct x86_decode *decode)
uint64_t sign(uint64_t val, int size)
{
switch (size) {
- case 1:
- val = (int8_t)val;
- break;
- case 2:
- val = (int16_t)val;
- break;
- case 4:
- val = (int32_t)val;
- break;
- case 8:
- val = (int64_t)val;
- break;
- default:
- VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
- break;
+ case 1:
+ val = (int8_t)val;
+ break;
+ case 2:
+ val = (int16_t)val;
+ break;
+ case 4:
+ val = (int32_t)val;
+ break;
+ case 8:
+ val = (int64_t)val;
+ break;
+ default:
+ VM_PANIC_EX("%s invalid size %d\n", __func__, size);
+ break;
}
return val;
}
-static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode, int size)
+static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode,
+ int size)
{
addr_t val = 0;
-
+
switch (size) {
- case 1:
- case 2:
- case 4:
- case 8:
- break;
- default:
- VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
- break;
+ case 1:
+ case 2:
+ case 4:
+ case 8:
+ break;
+ default:
+ VM_PANIC_EX("%s invalid size %d\n", __func__, size);
+ break;
}
addr_t va = linear_rip(cpu, RIP(cpu)) + decode->len;
vmx_read_mem(cpu, &val, va, size);
decode->len += size;
-
+
return val;
}
@@ -99,68 +102,76 @@ static inline uint64_t decode_qword(CPUState *cpu, struct x86_decode *decode)
return decode_bytes(cpu, decode, 8);
}
-static void decode_modrm_rm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_modrm_rm(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_RM;
}
-static void decode_modrm_reg(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_modrm_reg(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = decode->modrm.reg;
op->ptr = get_reg_ref(cpu, op->reg, decode->rex.r, decode->operand_size);
}
-static void decode_rax(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_rax(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = REG_RAX;
op->ptr = get_reg_ref(cpu, op->reg, 0, decode->operand_size);
}
-static inline void decode_immediate(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *var, int size)
+static inline void decode_immediate(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *var, int size)
{
var->type = X86_VAR_IMMEDIATE;
var->size = size;
switch (size) {
- case 1:
- var->val = decode_byte(cpu, decode);
- break;
- case 2:
- var->val = decode_word(cpu, decode);
- break;
- case 4:
- var->val = decode_dword(cpu, decode);
- break;
- case 8:
- var->val = decode_qword(cpu, decode);
- break;
- default:
- VM_PANIC_EX("bad size %d\n", size);
+ case 1:
+ var->val = decode_byte(cpu, decode);
+ break;
+ case 2:
+ var->val = decode_word(cpu, decode);
+ break;
+ case 4:
+ var->val = decode_dword(cpu, decode);
+ break;
+ case 8:
+ var->val = decode_qword(cpu, decode);
+ break;
+ default:
+ VM_PANIC_EX("bad size %d\n", size);
}
}
-static void decode_imm8(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm8(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
decode_immediate(cpu, decode, op, 1);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm8_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm8_signed(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
decode_immediate(cpu, decode, op, 1);
op->val = sign(op->val, 1);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm16(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
decode_immediate(cpu, decode, op, 2);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
if (8 == decode->operand_size) {
decode_immediate(cpu, decode, op, 4);
@@ -171,20 +182,23 @@ static void decode_imm(CPUState *cpu, struct x86_decode *decode, struct x86_deco
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm_signed(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
decode_immediate(cpu, decode, op, decode->operand_size);
op->val = sign(op->val, decode->operand_size);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm_1(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm_1(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_IMMEDIATE;
op->val = 1;
}
-static void decode_imm_0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_imm_0(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_IMMEDIATE;
op->val = 0;
@@ -194,54 +208,54 @@ static void decode_imm_0(CPUState *cpu, struct x86_decode *decode, struct x86_de
static void decode_pushseg(CPUState *cpu, struct x86_decode *decode)
{
uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
-
+
decode->op[0].type = X86_VAR_REG;
switch (op) {
- case 0xe:
- decode->op[0].reg = REG_SEG_CS;
- break;
- case 0x16:
- decode->op[0].reg = REG_SEG_SS;
- break;
- case 0x1e:
- decode->op[0].reg = REG_SEG_DS;
- break;
- case 0x06:
- decode->op[0].reg = REG_SEG_ES;
- break;
- case 0xa0:
- decode->op[0].reg = REG_SEG_FS;
- break;
- case 0xa8:
- decode->op[0].reg = REG_SEG_GS;
- break;
+ case 0xe:
+ decode->op[0].reg = REG_SEG_CS;
+ break;
+ case 0x16:
+ decode->op[0].reg = REG_SEG_SS;
+ break;
+ case 0x1e:
+ decode->op[0].reg = REG_SEG_DS;
+ break;
+ case 0x06:
+ decode->op[0].reg = REG_SEG_ES;
+ break;
+ case 0xa0:
+ decode->op[0].reg = REG_SEG_FS;
+ break;
+ case 0xa8:
+ decode->op[0].reg = REG_SEG_GS;
+ break;
}
}
static void decode_popseg(CPUState *cpu, struct x86_decode *decode)
{
uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
-
+
decode->op[0].type = X86_VAR_REG;
switch (op) {
- case 0xf:
- decode->op[0].reg = REG_SEG_CS;
- break;
- case 0x17:
- decode->op[0].reg = REG_SEG_SS;
- break;
- case 0x1f:
- decode->op[0].reg = REG_SEG_DS;
- break;
- case 0x07:
- decode->op[0].reg = REG_SEG_ES;
- break;
- case 0xa1:
- decode->op[0].reg = REG_SEG_FS;
- break;
- case 0xa9:
- decode->op[0].reg = REG_SEG_GS;
- break;
+ case 0xf:
+ decode->op[0].reg = REG_SEG_CS;
+ break;
+ case 0x17:
+ decode->op[0].reg = REG_SEG_SS;
+ break;
+ case 0x1f:
+ decode->op[0].reg = REG_SEG_DS;
+ break;
+ case 0x07:
+ decode->op[0].reg = REG_SEG_ES;
+ break;
+ case 0xa1:
+ decode->op[0].reg = REG_SEG_FS;
+ break;
+ case 0xa9:
+ decode->op[0].reg = REG_SEG_GS;
+ break;
}
}
@@ -249,36 +263,41 @@ static void decode_incgroup(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x40;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
}
static void decode_decgroup(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x48;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
}
static void decode_incgroup2(CPUState *cpu, struct x86_decode *decode)
{
- if (!decode->modrm.reg)
+ if (!decode->modrm.reg) {
decode->cmd = X86_DECODE_CMD_INC;
- else if (1 == decode->modrm.reg)
+ } else if (1 == decode->modrm.reg) {
decode->cmd = X86_DECODE_CMD_DEC;
+ }
}
static void decode_pushgroup(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x50;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
}
static void decode_popgroup(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x58;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
}
static void decode_jxx(CPUState *cpu, struct x86_decode *decode)
@@ -340,18 +359,18 @@ static void decode_f7group(CPUState *cpu, struct x86_decode *decode)
decode_modrm_rm(cpu, decode, &decode->op[0]);
switch (decode->modrm.reg) {
- case 0:
- case 1:
- decode_imm(cpu, decode, &decode->op[1]);
- break;
- case 2:
- break;
- case 3:
- decode->op[1].type = X86_VAR_IMMEDIATE;
- decode->op[1].val = 0;
- break;
- default:
- break;
+ case 0:
+ case 1:
+ decode_imm(cpu, decode, &decode->op[1]);
+ break;
+ case 2:
+ break;
+ case 3:
+ decode->op[1].type = X86_VAR_IMMEDIATE;
+ decode->op[1].val = 0;
+ break;
+ default:
+ break;
}
}
@@ -359,18 +378,21 @@ static void decode_xchgroup(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x90;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
}
static void decode_movgroup(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0xb8;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
}
-static void fetch_moffs(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void fetch_moffs(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_OFFSET;
op->ptr = decode_bytes(cpu, decode, decode->addressing_size);
@@ -380,11 +402,13 @@ static void decode_movgroup8(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0xb0;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
}
-static void decode_rcx(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_rcx(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = REG_RCX;
@@ -396,10 +420,14 @@ struct decode_tbl {
enum x86_decode_cmd cmd;
uint8_t operand_size;
bool is_modrm;
- void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
- void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
- void (*decode_op3)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op3);
- void (*decode_op4)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op4);
+ void (*decode_op1)(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op1);
+ void (*decode_op2)(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op2);
+ void (*decode_op3)(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op3);
+ void (*decode_op4)(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op4);
void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
addr_t flags_mask;
};
@@ -412,13 +440,16 @@ struct decode_x87_tbl {
uint8_t operand_size;
bool rev;
bool pop;
- void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
- void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
+ void (*decode_op1)(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op1);
+ void (*decode_op2)(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op2);
void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
addr_t flags_mask;
};
-struct decode_tbl invl_inst = {0x0, 0, 0, false, NULL, NULL, NULL, NULL, decode_invalid};
+struct decode_tbl invl_inst = {0x0, 0, 0, false, NULL, NULL, NULL, NULL,
+ decode_invalid};
struct decode_tbl _decode_tbl1[255];
struct decode_tbl _decode_tbl2[255];
@@ -427,28 +458,35 @@ struct decode_x87_tbl _decode_tbl3[255];
static void decode_x87_ins(CPUState *cpu, struct x86_decode *decode)
{
struct decode_x87_tbl *decoder;
-
+
decode->is_fpu = true;
int mode = decode->modrm.mod == 3 ? 1 : 0;
- int index = ((decode->opcode[0] & 0xf) << 4) | (mode << 3) | decode->modrm.reg;
-
+ int index = ((decode->opcode[0] & 0xf) << 4) | (mode << 3) |
+ decode->modrm.reg;
+
decoder = &_decode_tbl3[index];
-
+
decode->cmd = decoder->cmd;
- if (decoder->operand_size)
+ if (decoder->operand_size) {
decode->operand_size = decoder->operand_size;
+ }
decode->flags_mask = decoder->flags_mask;
decode->fpop_stack = decoder->pop;
decode->frev = decoder->rev;
-
- if (decoder->decode_op1)
+
+ if (decoder->decode_op1) {
decoder->decode_op1(cpu, decode, &decode->op[0]);
- if (decoder->decode_op2)
+ }
+ if (decoder->decode_op2) {
decoder->decode_op2(cpu, decode, &decode->op[1]);
- if (decoder->decode_postfix)
+ }
+ if (decoder->decode_postfix) {
decoder->decode_postfix(cpu, decode);
-
- VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n", decode->opcode[0], decode->modrm.modrm, decoder->modrm_reg, decoder->modrm_mod);
+ }
+
+ VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n",
+ decode->opcode[0], decode->modrm.modrm, decoder->modrm_reg,
+ decoder->modrm_mod);
}
static void decode_ffgroup(CPUState *cpu, struct x86_decode *decode)
@@ -465,8 +503,9 @@ static void decode_ffgroup(CPUState *cpu, struct x86_decode *decode)
X86_DECODE_CMD_INVL
};
decode->cmd = group[decode->modrm.reg];
- if (decode->modrm.reg > 2)
+ if (decode->modrm.reg > 2) {
decode->flags_mask = 0;
+ }
}
static void decode_sldtgroup(CPUState *cpu, struct x86_decode *decode)
@@ -482,7 +521,8 @@ static void decode_sldtgroup(CPUState *cpu, struct x86_decode *decode)
X86_DECODE_CMD_INVL
};
decode->cmd = group[decode->modrm.reg];
- printf("%llx: decode_sldtgroup: %d\n", cpu->hvf_x86->fetch_rip, decode->modrm.reg);
+ printf("%llx: decode_sldtgroup: %d\n", cpu->hvf_x86->fetch_rip,
+ decode->modrm.reg);
}
static void decode_lidtgroup(CPUState *cpu, struct x86_decode *decode)
@@ -524,28 +564,34 @@ static void decode_x87_general(CPUState *cpu, struct x86_decode *decode)
decode->is_fpu = true;
}
-static void decode_x87_modrm_floatp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_x87_modrm_floatp(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X87_VAR_FLOATP;
}
-static void decode_x87_modrm_intp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_x87_modrm_intp(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X87_VAR_INTP;
}
-static void decode_x87_modrm_bytep(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_x87_modrm_bytep(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X87_VAR_BYTEP;
}
-static void decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X87_VAR_REG;
op->reg = 0;
}
-static void decode_decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+static void decode_decode_x87_modrm_st0(CPUState *cpu,
+ struct x86_decode *decode,
+ struct x86_decode_op *op)
{
op->type = X87_VAR_REG;
op->reg = decode->modrm.modrm & 7;
@@ -556,35 +602,35 @@ static void decode_aegroup(CPUState *cpu, struct x86_decode *decode)
{
decode->is_fpu = true;
switch (decode->modrm.reg) {
- case 0:
- decode->cmd = X86_DECODE_CMD_FXSAVE;
- decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
- break;
- case 1:
- decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
- decode->cmd = X86_DECODE_CMD_FXRSTOR;
- break;
- case 5:
- if (decode->modrm.modrm == 0xe8) {
- decode->cmd = X86_DECODE_CMD_LFENCE;
- } else {
- VM_PANIC("xrstor");
- }
- break;
- case 6:
- VM_PANIC_ON(decode->modrm.modrm != 0xf0);
- decode->cmd = X86_DECODE_CMD_MFENCE;
- break;
- case 7:
- if (decode->modrm.modrm == 0xf8) {
- decode->cmd = X86_DECODE_CMD_SFENCE;
- } else {
- decode->cmd = X86_DECODE_CMD_CLFLUSH;
- }
- break;
- default:
- VM_PANIC_ON_EX(1, "0xae: reg %d\n", decode->modrm.reg);
- break;
+ case 0:
+ decode->cmd = X86_DECODE_CMD_FXSAVE;
+ decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
+ break;
+ case 1:
+ decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
+ decode->cmd = X86_DECODE_CMD_FXRSTOR;
+ break;
+ case 5:
+ if (decode->modrm.modrm == 0xe8) {
+ decode->cmd = X86_DECODE_CMD_LFENCE;
+ } else {
+ VM_PANIC("xrstor");
+ }
+ break;
+ case 6:
+ VM_PANIC_ON(decode->modrm.modrm != 0xf0);
+ decode->cmd = X86_DECODE_CMD_MFENCE;
+ break;
+ case 7:
+ if (decode->modrm.modrm == 0xf8) {
+ decode->cmd = X86_DECODE_CMD_SFENCE;
+ } else {
+ decode->cmd = X86_DECODE_CMD_CLFLUSH;
+ }
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "0xae: reg %d\n", decode->modrm.reg);
+ break;
}
}
@@ -592,568 +638,1003 @@ static void decode_bswap(CPUState *cpu, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[1] - 0xc8;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->operand_size);
}
static void decode_d9_4(CPUState *cpu, struct x86_decode *decode)
{
- switch(decode->modrm.modrm) {
- case 0xe0:
- // FCHS
- decode->cmd = X86_DECODE_CMD_FCHS;
- break;
- case 0xe1:
- decode->cmd = X86_DECODE_CMD_FABS;
- break;
- case 0xe4:
- VM_PANIC_ON_EX(1, "FTST");
- break;
- case 0xe5:
- // FXAM
- decode->cmd = X86_DECODE_CMD_FXAM;
- break;
- default:
- VM_PANIC_ON_EX(1, "FLDENV");
- break;
+ switch (decode->modrm.modrm) {
+ case 0xe0:
+ /* FCHS */
+ decode->cmd = X86_DECODE_CMD_FCHS;
+ break;
+ case 0xe1:
+ decode->cmd = X86_DECODE_CMD_FABS;
+ break;
+ case 0xe4:
+ VM_PANIC_ON_EX(1, "FTST");
+ break;
+ case 0xe5:
+ /* FXAM */
+ decode->cmd = X86_DECODE_CMD_FXAM;
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "FLDENV");
+ break;
}
}
static void decode_db_4(CPUState *cpu, struct x86_decode *decode)
{
switch (decode->modrm.modrm) {
- case 0xe0:
- VM_PANIC_ON_EX(1, "unhandled FNENI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
- break;
- case 0xe1:
- VM_PANIC_ON_EX(1, "unhandled FNDISI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
- break;
- case 0xe2:
- VM_PANIC_ON_EX(1, "unhandled FCLEX: %x %x\n", decode->opcode[0], decode->modrm.modrm);
- break;
- case 0xe3:
- decode->cmd = X86_DECODE_CMD_FNINIT;
- break;
- case 0xe4:
- decode->cmd = X86_DECODE_CMD_FNSETPM;
- break;
- default:
- VM_PANIC_ON_EX(1, "unhandled fpu opcode: %x %x\n", decode->opcode[0], decode->modrm.modrm);
- break;
+ case 0xe0:
+ VM_PANIC_ON_EX(1, "unhandled FNENI: %x %x\n", decode->opcode[0],
+ decode->modrm.modrm);
+ break;
+ case 0xe1:
+ VM_PANIC_ON_EX(1, "unhandled FNDISI: %x %x\n", decode->opcode[0],
+ decode->modrm.modrm);
+ break;
+ case 0xe2:
+ VM_PANIC_ON_EX(1, "unhandled FCLEX: %x %x\n", decode->opcode[0],
+ decode->modrm.modrm);
+ break;
+ case 0xe3:
+ decode->cmd = X86_DECODE_CMD_FNINIT;
+ break;
+ case 0xe4:
+ decode->cmd = X86_DECODE_CMD_FNSETPM;
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "unhandled fpu opcode: %x %x\n", decode->opcode[0],
+ decode->modrm.modrm);
+ break;
}
}
#define RFLAGS_MASK_NONE 0
-#define RFLAGS_MASK_OSZAPC (RFLAGS_OF | RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
-#define RFLAGS_MASK_LAHF (RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
+#define RFLAGS_MASK_OSZAPC (RFLAGS_OF | RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | \
+ RFLAGS_PF | RFLAGS_CF)
+#define RFLAGS_MASK_LAHF (RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | \
+ RFLAGS_CF)
#define RFLAGS_MASK_CF (RFLAGS_CF)
#define RFLAGS_MASK_IF (RFLAGS_IF)
#define RFLAGS_MASK_TF (RFLAGS_TF)
#define RFLAGS_MASK_DF (RFLAGS_DF)
#define RFLAGS_MASK_ZF (RFLAGS_ZF)
-struct decode_tbl _1op_inst[] =
-{
- {0x0, X86_DECODE_CMD_ADD, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x1, X86_DECODE_CMD_ADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x2, X86_DECODE_CMD_ADD, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x3, X86_DECODE_CMD_ADD, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x4, X86_DECODE_CMD_ADD, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x5, X86_DECODE_CMD_ADD, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x6, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
- {0x7, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
- {0x8, X86_DECODE_CMD_OR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x9, X86_DECODE_CMD_OR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xa, X86_DECODE_CMD_OR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xb, X86_DECODE_CMD_OR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xc, X86_DECODE_CMD_OR, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xd, X86_DECODE_CMD_OR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xe, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
- {0xf, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
-
- {0x10, X86_DECODE_CMD_ADC, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x11, X86_DECODE_CMD_ADC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x12, X86_DECODE_CMD_ADC, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x13, X86_DECODE_CMD_ADC, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x14, X86_DECODE_CMD_ADC, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x15, X86_DECODE_CMD_ADC, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0x16, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
- {0x17, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
-
- {0x18, X86_DECODE_CMD_SBB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x19, X86_DECODE_CMD_SBB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x1a, X86_DECODE_CMD_SBB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x1b, X86_DECODE_CMD_SBB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x1c, X86_DECODE_CMD_SBB, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x1d, X86_DECODE_CMD_SBB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0x1e, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
- {0x1f, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
-
- {0x20, X86_DECODE_CMD_AND, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x21, X86_DECODE_CMD_AND, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x22, X86_DECODE_CMD_AND, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x23, X86_DECODE_CMD_AND, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x24, X86_DECODE_CMD_AND, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x25, X86_DECODE_CMD_AND, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x28, X86_DECODE_CMD_SUB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x29, X86_DECODE_CMD_SUB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x2a, X86_DECODE_CMD_SUB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x2b, X86_DECODE_CMD_SUB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x2c, X86_DECODE_CMD_SUB, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x2d, X86_DECODE_CMD_SUB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x2f, X86_DECODE_CMD_DAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x30, X86_DECODE_CMD_XOR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x31, X86_DECODE_CMD_XOR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x32, X86_DECODE_CMD_XOR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x33, X86_DECODE_CMD_XOR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x34, X86_DECODE_CMD_XOR, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x35, X86_DECODE_CMD_XOR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0x38, X86_DECODE_CMD_CMP, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x39, X86_DECODE_CMD_CMP, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x3a, X86_DECODE_CMD_CMP, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x3b, X86_DECODE_CMD_CMP, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x3c, X86_DECODE_CMD_CMP, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x3d, X86_DECODE_CMD_CMP, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0x3f, X86_DECODE_CMD_AAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0x40, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x41, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x42, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x43, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x44, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x45, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x46, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
- {0x47, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
-
- {0x48, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x49, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x4a, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x4b, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x4c, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x4d, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x4e, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
- {0x4f, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
-
- {0x50, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x51, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x52, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x53, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x54, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x55, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x56, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
- {0x57, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
-
- {0x58, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x59, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x5a, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x5b, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x5c, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x5d, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x5e, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
- {0x5f, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
-
- {0x60, X86_DECODE_CMD_PUSHA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x61, X86_DECODE_CMD_POPA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0x68, X86_DECODE_CMD_PUSH, 0, false, decode_imm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x6a, X86_DECODE_CMD_PUSH, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x69, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x6b, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm8_signed, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0x6c, X86_DECODE_CMD_INS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x6d, X86_DECODE_CMD_INS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x6e, X86_DECODE_CMD_OUTS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x6f, X86_DECODE_CMD_OUTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0x70, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x71, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x72, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x73, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x74, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x75, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x76, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x77, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x78, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x79, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x7a, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x7b, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x7c, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x7d, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x7e, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x7f, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
-
- {0x80, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
- {0x81, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
- {0x82, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
- {0x83, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8_signed, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
- {0x84, X86_DECODE_CMD_TST, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x85, X86_DECODE_CMD_TST, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0x86, X86_DECODE_CMD_XCHG, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x87, X86_DECODE_CMD_XCHG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x88, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x89, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x8a, X86_DECODE_CMD_MOV, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x8b, X86_DECODE_CMD_MOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x8c, X86_DECODE_CMD_MOV_FROM_SEG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x8d, X86_DECODE_CMD_LEA, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x8e, X86_DECODE_CMD_MOV_TO_SEG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x8f, X86_DECODE_CMD_POP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0x90, X86_DECODE_CMD_NOP, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x91, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
- {0x92, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
- {0x93, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
- {0x94, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
- {0x95, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
- {0x96, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
- {0x97, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
-
- {0x98, X86_DECODE_CMD_CBW, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x99, X86_DECODE_CMD_CWD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0x9a, X86_DECODE_CMD_CALL_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
-
- {0x9c, X86_DECODE_CMD_PUSHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- //{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_POPF},
- {0x9e, X86_DECODE_CMD_SAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9f, X86_DECODE_CMD_LAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_LAHF},
-
- {0xa0, X86_DECODE_CMD_MOV, 1, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa1, X86_DECODE_CMD_MOV, 0, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa2, X86_DECODE_CMD_MOV, 1, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa3, X86_DECODE_CMD_MOV, 0, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xa4, X86_DECODE_CMD_MOVS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa5, X86_DECODE_CMD_MOVS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa6, X86_DECODE_CMD_CMPS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xa7, X86_DECODE_CMD_CMPS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xaa, X86_DECODE_CMD_STOS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xab, X86_DECODE_CMD_STOS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xac, X86_DECODE_CMD_LODS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xad, X86_DECODE_CMD_LODS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xae, X86_DECODE_CMD_SCAS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xaf, X86_DECODE_CMD_SCAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xa8, X86_DECODE_CMD_TST, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xa9, X86_DECODE_CMD_TST, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xb0, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb1, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb2, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb3, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb4, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb5, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb6, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
- {0xb7, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
-
- {0xb8, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xb9, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xba, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xbb, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xbc, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xbd, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xbe, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
- {0xbf, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
-
- {0xc0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
- {0xc1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
-
- {0xc2, X86_DECODE_RET_NEAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xc3, X86_DECODE_RET_NEAR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xc4, X86_DECODE_CMD_LES, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xc5, X86_DECODE_CMD_LDS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xc6, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xc7, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xc8, X86_DECODE_CMD_ENTER, 0, false, decode_imm16, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xc9, X86_DECODE_CMD_LEAVE, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xca, X86_DECODE_RET_FAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xcb, X86_DECODE_RET_FAR, 0, false, decode_imm_0, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xcd, X86_DECODE_CMD_INT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- //{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IRET},
-
- {0xd0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
- {0xd1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
- {0xd2, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
- {0xd3, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
-
- {0xd4, X86_DECODE_CMD_AAM, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xd5, X86_DECODE_CMD_AAD, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xd7, X86_DECODE_CMD_XLAT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xd8, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xd9, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xda, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xdb, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xdc, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xdd, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xde, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
- {0xdf, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
-
- {0xe0, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe1, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe2, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xe3, X86_DECODE_CMD_JCXZ, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
-
- {0xe4, X86_DECODE_CMD_IN, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe5, X86_DECODE_CMD_IN, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe6, X86_DECODE_CMD_OUT, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe7, X86_DECODE_CMD_OUT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe8, X86_DECODE_CMD_CALL_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xe9, X86_DECODE_CMD_JMP_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xea, X86_DECODE_CMD_JMP_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
- {0xeb, X86_DECODE_CMD_JMP_NEAR, 1, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xec, X86_DECODE_CMD_IN, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xed, X86_DECODE_CMD_IN, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xee, X86_DECODE_CMD_OUT, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xef, X86_DECODE_CMD_OUT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xf4, X86_DECODE_CMD_HLT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xf5, X86_DECODE_CMD_CMC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
-
- {0xf6, X86_DECODE_CMD_INVL, 1, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
- {0xf7, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
-
- {0xf8, X86_DECODE_CMD_CLC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
- {0xf9, X86_DECODE_CMD_STC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
-
- {0xfa, X86_DECODE_CMD_CLI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
- {0xfb, X86_DECODE_CMD_STI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
- {0xfc, X86_DECODE_CMD_CLD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
- {0xfd, X86_DECODE_CMD_STD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
- {0xfe, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, NULL, NULL, NULL, decode_incgroup2, RFLAGS_MASK_OSZAPC},
- {0xff, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_ffgroup, RFLAGS_MASK_OSZAPC},
+struct decode_tbl _1op_inst[] = {
+ {0x0, X86_DECODE_CMD_ADD, 1, true, decode_modrm_rm, decode_modrm_reg, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1, X86_DECODE_CMD_ADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2, X86_DECODE_CMD_ADD, 1, true, decode_modrm_reg, decode_modrm_rm, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3, X86_DECODE_CMD_ADD, 0, true, decode_modrm_reg, decode_modrm_rm, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x4, X86_DECODE_CMD_ADD, 1, false, decode_rax, decode_imm8, NULL, NULL,
+ NULL, RFLAGS_MASK_OSZAPC},
+ {0x5, X86_DECODE_CMD_ADD, 0, false, decode_rax, decode_imm, NULL, NULL,
+ NULL, RFLAGS_MASK_OSZAPC},
+ {0x6, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL,
+ decode_pushseg, RFLAGS_MASK_NONE},
+ {0x7, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL,
+ decode_popseg, RFLAGS_MASK_NONE},
+ {0x8, X86_DECODE_CMD_OR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x9, X86_DECODE_CMD_OR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa, X86_DECODE_CMD_OR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL,
+ NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xb, X86_DECODE_CMD_OR, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xc, X86_DECODE_CMD_OR, 1, false, decode_rax, decode_imm8,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xd, X86_DECODE_CMD_OR, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xe, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0xf, X86_DECODE_CMD_POP_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+
+ {0x10, X86_DECODE_CMD_ADC, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x11, X86_DECODE_CMD_ADC, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x12, X86_DECODE_CMD_ADC, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x13, X86_DECODE_CMD_ADC, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x14, X86_DECODE_CMD_ADC, 1, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x15, X86_DECODE_CMD_ADC, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x16, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0x17, X86_DECODE_CMD_POP_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+
+ {0x18, X86_DECODE_CMD_SBB, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x19, X86_DECODE_CMD_SBB, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1a, X86_DECODE_CMD_SBB, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1b, X86_DECODE_CMD_SBB, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1c, X86_DECODE_CMD_SBB, 1, false, decode_rax, decode_imm8,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x1d, X86_DECODE_CMD_SBB, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x1e, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0x1f, X86_DECODE_CMD_POP_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+
+ {0x20, X86_DECODE_CMD_AND, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x21, X86_DECODE_CMD_AND, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x22, X86_DECODE_CMD_AND, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x23, X86_DECODE_CMD_AND, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x24, X86_DECODE_CMD_AND, 1, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x25, X86_DECODE_CMD_AND, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x28, X86_DECODE_CMD_SUB, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x29, X86_DECODE_CMD_SUB, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2a, X86_DECODE_CMD_SUB, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2b, X86_DECODE_CMD_SUB, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2c, X86_DECODE_CMD_SUB, 1, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2d, X86_DECODE_CMD_SUB, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x2f, X86_DECODE_CMD_DAS, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x30, X86_DECODE_CMD_XOR, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x31, X86_DECODE_CMD_XOR, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x32, X86_DECODE_CMD_XOR, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x33, X86_DECODE_CMD_XOR, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x34, X86_DECODE_CMD_XOR, 1, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x35, X86_DECODE_CMD_XOR, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x38, X86_DECODE_CMD_CMP, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x39, X86_DECODE_CMD_CMP, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3a, X86_DECODE_CMD_CMP, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3b, X86_DECODE_CMD_CMP, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3c, X86_DECODE_CMD_CMP, 1, false, decode_rax, decode_imm8,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x3d, X86_DECODE_CMD_CMP, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x3f, X86_DECODE_CMD_AAS, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x40, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x41, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x42, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x43, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x44, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x45, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x46, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+ {0x47, X86_DECODE_CMD_INC, 0, false,
+ NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
+
+ {0x48, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x49, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4a, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4b, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4c, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4d, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4e, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+ {0x4f, X86_DECODE_CMD_DEC, 0, false,
+ NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
+
+ {0x50, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x51, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x52, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x53, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x54, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x55, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x56, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+ {0x57, X86_DECODE_CMD_PUSH, 0, false,
+ NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
+
+ {0x58, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x59, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5a, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5b, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5c, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5d, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5e, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+ {0x5f, X86_DECODE_CMD_POP, 0, false,
+ NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
+
+ {0x60, X86_DECODE_CMD_PUSHA, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x61, X86_DECODE_CMD_POPA, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x68, X86_DECODE_CMD_PUSH, 0, false, decode_imm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6a, X86_DECODE_CMD_PUSH, 0, false, decode_imm8_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x69, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg,
+ decode_modrm_rm, decode_imm, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x6b, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm,
+ decode_imm8_signed, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0x6c, X86_DECODE_CMD_INS, 1, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6d, X86_DECODE_CMD_INS, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6e, X86_DECODE_CMD_OUTS, 1, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x6f, X86_DECODE_CMD_OUTS, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x70, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x71, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x72, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x73, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x74, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x75, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x76, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x77, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x78, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x79, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7a, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7b, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7c, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7d, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7e, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x7f, X86_DECODE_CMD_JXX, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+
+ {0x80, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8,
+ NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x81, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm,
+ NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x82, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8,
+ NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x83, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8_signed,
+ NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
+ {0x84, X86_DECODE_CMD_TST, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x85, X86_DECODE_CMD_TST, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0x86, X86_DECODE_CMD_XCHG, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x87, X86_DECODE_CMD_XCHG, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x88, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x89, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8a, X86_DECODE_CMD_MOV, 1, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8b, X86_DECODE_CMD_MOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8c, X86_DECODE_CMD_MOV_FROM_SEG, 0, true, decode_modrm_rm,
+ decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8d, X86_DECODE_CMD_LEA, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8e, X86_DECODE_CMD_MOV_TO_SEG, 0, true, decode_modrm_reg,
+ decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x8f, X86_DECODE_CMD_POP, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x90, X86_DECODE_CMD_NOP, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x91, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x92, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x93, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x94, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x95, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x96, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+ {0x97, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax,
+ NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
+
+ {0x98, X86_DECODE_CMD_CBW, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x99, X86_DECODE_CMD_CWD, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0x9a, X86_DECODE_CMD_CALL_FAR, 0, false, NULL,
+ NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
+
+ {0x9c, X86_DECODE_CMD_PUSHF, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ /*{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_POPF},*/
+ {0x9e, X86_DECODE_CMD_SAHF, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9f, X86_DECODE_CMD_LAHF, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_LAHF},
+
+ {0xa0, X86_DECODE_CMD_MOV, 1, false, decode_rax, fetch_moffs,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa1, X86_DECODE_CMD_MOV, 0, false, decode_rax, fetch_moffs,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa2, X86_DECODE_CMD_MOV, 1, false, fetch_moffs, decode_rax,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa3, X86_DECODE_CMD_MOV, 0, false, fetch_moffs, decode_rax,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xa4, X86_DECODE_CMD_MOVS, 1, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa5, X86_DECODE_CMD_MOVS, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa6, X86_DECODE_CMD_CMPS, 1, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa7, X86_DECODE_CMD_CMPS, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xaa, X86_DECODE_CMD_STOS, 1, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xab, X86_DECODE_CMD_STOS, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xac, X86_DECODE_CMD_LODS, 1, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xad, X86_DECODE_CMD_LODS, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xae, X86_DECODE_CMD_SCAS, 1, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xaf, X86_DECODE_CMD_SCAS, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xa8, X86_DECODE_CMD_TST, 1, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa9, X86_DECODE_CMD_TST, 0, false, decode_rax, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xb0, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb1, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb2, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb3, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb4, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb5, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb6, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+ {0xb7, X86_DECODE_CMD_MOV, 1, false, NULL,
+ NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
+
+ {0xb8, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xb9, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xba, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbb, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbc, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbd, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbe, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+ {0xbf, X86_DECODE_CMD_MOV, 0, false, NULL,
+ NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
+
+ {0xc0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8,
+ NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xc1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8,
+ NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+
+ {0xc2, X86_DECODE_RET_NEAR, 0, false, decode_imm16,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc3, X86_DECODE_RET_NEAR, 0, false, NULL,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xc4, X86_DECODE_CMD_LES, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc5, X86_DECODE_CMD_LDS, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xc6, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_imm8,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc7, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_imm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xc8, X86_DECODE_CMD_ENTER, 0, false, decode_imm16, decode_imm8,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xc9, X86_DECODE_CMD_LEAVE, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xca, X86_DECODE_RET_FAR, 0, false, decode_imm16, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xcb, X86_DECODE_RET_FAR, 0, false, decode_imm_0, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xcd, X86_DECODE_CMD_INT, 0, false, decode_imm8, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ /*{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL,
+ NULL, NULL, NULL, RFLAGS_MASK_IRET},*/
+
+ {0xd0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm_1,
+ NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xd1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm_1,
+ NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xd2, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_rcx,
+ NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+ {0xd3, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_rcx,
+ NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
+
+ {0xd4, X86_DECODE_CMD_AAM, 0, false, decode_imm8,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xd5, X86_DECODE_CMD_AAD, 0, false, decode_imm8,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xd7, X86_DECODE_CMD_XLAT, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xd8, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xd9, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xda, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdb, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdc, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdd, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xde, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+ {0xdf, X86_DECODE_CMD_INVL, 0, true, NULL,
+ NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
+
+ {0xe0, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe1, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe2, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xe3, X86_DECODE_CMD_JCXZ, 1, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+
+ {0xe4, X86_DECODE_CMD_IN, 1, false, decode_imm8,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe5, X86_DECODE_CMD_IN, 0, false, decode_imm8,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe6, X86_DECODE_CMD_OUT, 1, false, decode_imm8,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe7, X86_DECODE_CMD_OUT, 0, false, decode_imm8,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe8, X86_DECODE_CMD_CALL_NEAR, 0, false, decode_imm_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xe9, X86_DECODE_CMD_JMP_NEAR, 0, false, decode_imm_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xea, X86_DECODE_CMD_JMP_FAR, 0, false,
+ NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
+ {0xeb, X86_DECODE_CMD_JMP_NEAR, 1, false, decode_imm8_signed,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xec, X86_DECODE_CMD_IN, 1, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xed, X86_DECODE_CMD_IN, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xee, X86_DECODE_CMD_OUT, 1, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xef, X86_DECODE_CMD_OUT, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xf4, X86_DECODE_CMD_HLT, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xf5, X86_DECODE_CMD_CMC, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
+
+ {0xf6, X86_DECODE_CMD_INVL, 1, true,
+ NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
+ {0xf7, X86_DECODE_CMD_INVL, 0, true,
+ NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
+
+ {0xf8, X86_DECODE_CMD_CLC, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
+ {0xf9, X86_DECODE_CMD_STC, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
+
+ {0xfa, X86_DECODE_CMD_CLI, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
+ {0xfb, X86_DECODE_CMD_STI, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
+ {0xfc, X86_DECODE_CMD_CLD, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
+ {0xfd, X86_DECODE_CMD_STD, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
+ {0xfe, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, decode_incgroup2, RFLAGS_MASK_OSZAPC},
+ {0xff, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, decode_ffgroup, RFLAGS_MASK_OSZAPC},
};
-struct decode_tbl _2op_inst[] =
-{
- {0x0, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_sldtgroup, RFLAGS_MASK_NONE},
- {0x1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_lidtgroup, RFLAGS_MASK_NONE},
- {0x6, X86_DECODE_CMD_CLTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_TF},
- {0x9, X86_DECODE_CMD_WBINVD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x18, X86_DECODE_CMD_PREFETCH, 0, true, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
- {0x1f, X86_DECODE_CMD_NOP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x20, X86_DECODE_CMD_MOV_FROM_CR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x21, X86_DECODE_CMD_MOV_FROM_DR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x22, X86_DECODE_CMD_MOV_TO_CR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x23, X86_DECODE_CMD_MOV_TO_DR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x30, X86_DECODE_CMD_WRMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x31, X86_DECODE_CMD_RDTSC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x32, X86_DECODE_CMD_RDMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x40, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x41, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x42, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x43, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x44, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x45, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x46, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x47, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x48, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x49, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x4a, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x4b, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x4c, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x4d, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x4e, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x4f, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x77, X86_DECODE_CMD_EMMS, 0, false, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
- {0x82, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x83, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x84, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x85, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x86, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x87, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x88, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x89, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x8a, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x8b, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x8c, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x8d, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x8e, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x8f, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
- {0x90, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x91, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x92, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x93, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x94, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x95, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x96, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x97, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x98, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x99, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9a, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9b, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9c, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9d, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9e, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0x9f, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xb0, X86_DECODE_CMD_CMPXCHG, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xb1, X86_DECODE_CMD_CMPXCHG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xb6, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xb7, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xb8, X86_DECODE_CMD_POPCNT, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xbe, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xbf, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa0, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
- {0xa1, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
- {0xa2, X86_DECODE_CMD_CPUID, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xa3, X86_DECODE_CMD_BT, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
- {0xa4, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xa5, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xa8, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
- {0xa9, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
- {0xab, X86_DECODE_CMD_BTS, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
- {0xac, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xad, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xae, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_aegroup, RFLAGS_MASK_NONE},
-
- {0xaf, X86_DECODE_CMD_IMUL_2, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xb2, X86_DECODE_CMD_LSS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xb3, X86_DECODE_CMD_BTR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xba, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_btgroup, RFLAGS_MASK_OSZAPC},
- {0xbb, X86_DECODE_CMD_BTC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xbc, X86_DECODE_CMD_BSF, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
- {0xbd, X86_DECODE_CMD_BSR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xc1, X86_DECODE_CMD_XADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
-
- {0xc7, X86_DECODE_CMD_CMPXCHG8B, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_ZF},
-
- {0xc8, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xc9, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xca, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xcb, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xcc, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xcd, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xce, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
- {0xcf, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+struct decode_tbl _2op_inst[] = {
+ {0x0, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, decode_sldtgroup, RFLAGS_MASK_NONE},
+ {0x1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, decode_lidtgroup, RFLAGS_MASK_NONE},
+ {0x6, X86_DECODE_CMD_CLTS, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_TF},
+ {0x9, X86_DECODE_CMD_WBINVD, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x18, X86_DECODE_CMD_PREFETCH, 0, true,
+ NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
+ {0x1f, X86_DECODE_CMD_NOP, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x20, X86_DECODE_CMD_MOV_FROM_CR, 0, true, decode_modrm_rm,
+ decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x21, X86_DECODE_CMD_MOV_FROM_DR, 0, true, decode_modrm_rm,
+ decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x22, X86_DECODE_CMD_MOV_TO_CR, 0, true, decode_modrm_reg,
+ decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x23, X86_DECODE_CMD_MOV_TO_DR, 0, true, decode_modrm_reg,
+ decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x30, X86_DECODE_CMD_WRMSR, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x31, X86_DECODE_CMD_RDTSC, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x32, X86_DECODE_CMD_RDMSR, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x40, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x41, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x42, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x43, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x44, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x45, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x46, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x47, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x48, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x49, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4a, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4b, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4c, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4d, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4e, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x4f, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x77, X86_DECODE_CMD_EMMS, 0, false,
+ NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
+ {0x82, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x83, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x84, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x85, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x86, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x87, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x88, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x89, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8a, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8b, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8c, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8d, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8e, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x8f, X86_DECODE_CMD_JXX, 0, false,
+ NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
+ {0x90, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x91, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x92, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x93, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x94, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x95, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x96, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x97, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x98, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x99, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9a, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9b, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9c, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9d, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9e, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0x9f, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xb0, X86_DECODE_CMD_CMPXCHG, 1, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb1, X86_DECODE_CMD_CMPXCHG, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xb6, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb7, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb8, X86_DECODE_CMD_POPCNT, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xbe, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xbf, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa0, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0xa1, X86_DECODE_CMD_POP_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+ {0xa2, X86_DECODE_CMD_CPUID, 0, false,
+ NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xa3, X86_DECODE_CMD_BT, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_CF},
+ {0xa4, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg,
+ decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa5, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg,
+ decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xa8, X86_DECODE_CMD_PUSH_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
+ {0xa9, X86_DECODE_CMD_POP_SEG, 0, false, false,
+ NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
+ {0xab, X86_DECODE_CMD_BTS, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_CF},
+ {0xac, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg,
+ decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xad, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg,
+ decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xae, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, decode_aegroup, RFLAGS_MASK_NONE},
+
+ {0xaf, X86_DECODE_CMD_IMUL_2, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xb2, X86_DECODE_CMD_LSS, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xb3, X86_DECODE_CMD_BTR, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xba, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8,
+ NULL, NULL, decode_btgroup, RFLAGS_MASK_OSZAPC},
+ {0xbb, X86_DECODE_CMD_BTC, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xbc, X86_DECODE_CMD_BSF, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+ {0xbd, X86_DECODE_CMD_BSR, 0, true, decode_modrm_reg, decode_modrm_rm,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xc1, X86_DECODE_CMD_XADD, 0, true, decode_modrm_rm, decode_modrm_reg,
+ NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
+
+ {0xc7, X86_DECODE_CMD_CMPXCHG8B, 0, true, decode_modrm_rm,
+ NULL, NULL, NULL, NULL, RFLAGS_MASK_ZF},
+
+ {0xc8, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xc9, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xca, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcb, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcc, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcd, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xce, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
+ {0xcf, X86_DECODE_CMD_BSWAP, 0, false,
+ NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
};
-struct decode_x87_tbl invl_inst_x87 = {0x0, 0, 0, 0, 0, false, false, NULL, NULL, decode_invalid, 0};
-
-struct decode_x87_tbl _x87_inst[] =
-{
- {0xd8, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd8, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xd8, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd8, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xd8, 4, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd8, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xd8, 5, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd8, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd8, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xd8, 7, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd8, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
-
- {0xd9, 0, 3, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xd9, 1, 0, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 2, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 3, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, decode_d9_4, RFLAGS_MASK_NONE},
- {0xd9, 4, 0, X86_DECODE_CMD_INVL, 4, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 5, 3, X86_DECODE_CMD_FLDxx, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 5, 0, X86_DECODE_CMD_FLDCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
- //
- {0xd9, 7, 3, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
- {0xd9, 7, 0, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xda, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xda, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xda, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xda, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xda, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xda, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xda, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xda, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xda, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xda, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xda, 6, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xda, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xda, 7, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xda, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
-
- {0xdb, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdb, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdb, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdb, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdb, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdb, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdb, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdb, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, decode_db_4, RFLAGS_MASK_NONE},
- {0xdb, 4, 0, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdb, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdb, 5, 0, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdb, 7, 0, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xdc, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdc, 0, 0, X86_DECODE_CMD_FADD, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xdc, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdc, 1, 0, X86_DECODE_CMD_FMUL, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xdc, 4, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdc, 4, 0, X86_DECODE_CMD_FSUB, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xdc, 5, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdc, 5, 0, X86_DECODE_CMD_FSUB, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xdc, 6, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdc, 6, 0, X86_DECODE_CMD_FDIV, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
- {0xdc, 7, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdc, 7, 0, X86_DECODE_CMD_FDIV, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
-
- {0xdd, 0, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdd, 2, 3, X86_DECODE_CMD_FST, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 2, 0, X86_DECODE_CMD_FST, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 3, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 4, 3, X86_DECODE_CMD_FUCOM, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdd, 4, 0, X86_DECODE_CMD_FRSTOR, 8, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdd, 7, 0, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdd, 7, 3, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
-
- {0xde, 0, 3, X86_DECODE_CMD_FADD, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xde, 0, 0, X86_DECODE_CMD_FADD, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xde, 1, 3, X86_DECODE_CMD_FMUL, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xde, 1, 0, X86_DECODE_CMD_FMUL, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xde, 4, 3, X86_DECODE_CMD_FSUB, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xde, 4, 0, X86_DECODE_CMD_FSUB, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xde, 5, 3, X86_DECODE_CMD_FSUB, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xde, 5, 0, X86_DECODE_CMD_FSUB, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xde, 6, 3, X86_DECODE_CMD_FDIV, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xde, 6, 0, X86_DECODE_CMD_FDIV, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
- {0xde, 7, 3, X86_DECODE_CMD_FDIV, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xde, 7, 0, X86_DECODE_CMD_FDIV, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
-
- {0xdf, 0, 0, X86_DECODE_CMD_FLD, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdf, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdf, 2, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdf, 2, 0, X86_DECODE_CMD_FST, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdf, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdf, 3, 0, X86_DECODE_CMD_FST, 2, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdf, 4, 3, X86_DECODE_CMD_FNSTSW, 2, false, true, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdf, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
- {0xdf, 5, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
- {0xdf, 7, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+struct decode_x87_tbl invl_inst_x87 = {0x0, 0, 0, 0, 0, false, false, NULL,
+ NULL, decode_invalid, 0};
+
+struct decode_x87_tbl _x87_inst[] = {
+ {0xd8, 0, 3, X86_DECODE_CMD_FADD, 10, false, false,
+ decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0,
+ decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 4, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 5, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0,
+ decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 7, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd8, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0,
+ decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+
+ {0xd9, 0, 3, X86_DECODE_CMD_FLD, 10, false, false,
+ decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 0, 0, X86_DECODE_CMD_FLD, 4, false, false,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 1, 0, X86_DECODE_CMD_INVL, 10, false, false,
+ decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 2, 3, X86_DECODE_CMD_INVL, 10, false, false,
+ decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 2, 0, X86_DECODE_CMD_FST, 4, false, false,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 3, 3, X86_DECODE_CMD_INVL, 10, false, false,
+ decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 3, 0, X86_DECODE_CMD_FST, 4, false, true,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 4, 3, X86_DECODE_CMD_INVL, 10, false, false,
+ decode_x87_modrm_st0, NULL, decode_d9_4, RFLAGS_MASK_NONE},
+ {0xd9, 4, 0, X86_DECODE_CMD_INVL, 4, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 5, 3, X86_DECODE_CMD_FLDxx, 10, false, false, NULL, NULL, NULL,
+ RFLAGS_MASK_NONE},
+ {0xd9, 5, 0, X86_DECODE_CMD_FLDCW, 2, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xd9, 7, 3, X86_DECODE_CMD_FNSTCW, 2, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xd9, 7, 0, X86_DECODE_CMD_FNSTCW, 2, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xda, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
+ decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
+ RFLAGS_MASK_NONE},
+ {0xda, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0,
+ decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xda, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0,
+ decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 6, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
+ RFLAGS_MASK_NONE},
+ {0xda, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xda, 7, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
+ RFLAGS_MASK_NONE},
+ {0xda, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0,
+ decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+
+ {0xdb, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0,
+ decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 0, 0, X86_DECODE_CMD_FLD, 4, false, false,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 2, 0, X86_DECODE_CMD_FST, 4, false, false,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 3, 0, X86_DECODE_CMD_FST, 4, false, true,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL,
+ decode_db_4, RFLAGS_MASK_NONE},
+ {0xdb, 4, 0, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL,
+ RFLAGS_MASK_NONE},
+ {0xdb, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 5, 0, X86_DECODE_CMD_FLD, 10, false, false,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdb, 7, 0, X86_DECODE_CMD_FST, 10, false, true,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xdc, 0, 3, X86_DECODE_CMD_FADD, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 0, 0, X86_DECODE_CMD_FADD, 8, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 1, 0, X86_DECODE_CMD_FMUL, 8, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 4, 3, X86_DECODE_CMD_FSUB, 10, true, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 4, 0, X86_DECODE_CMD_FSUB, 8, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 5, 3, X86_DECODE_CMD_FSUB, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 5, 0, X86_DECODE_CMD_FSUB, 8, true, false,
+ decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 6, 3, X86_DECODE_CMD_FDIV, 10, true, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 6, 0, X86_DECODE_CMD_FDIV, 8, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 7, 3, X86_DECODE_CMD_FDIV, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdc, 7, 0, X86_DECODE_CMD_FDIV, 8, true, false,
+ decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
+
+ {0xdd, 0, 0, X86_DECODE_CMD_FLD, 8, false, false,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 2, 3, X86_DECODE_CMD_FST, 10, false, false,
+ decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 2, 0, X86_DECODE_CMD_FST, 8, false, false,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 3, 3, X86_DECODE_CMD_FST, 10, false, true,
+ decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 3, 0, X86_DECODE_CMD_FST, 8, false, true,
+ decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 4, 3, X86_DECODE_CMD_FUCOM, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 4, 0, X86_DECODE_CMD_FRSTOR, 8, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 7, 0, X86_DECODE_CMD_FNSTSW, 0, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdd, 7, 3, X86_DECODE_CMD_FNSTSW, 0, false, false,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+
+ {0xde, 0, 3, X86_DECODE_CMD_FADD, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 0, 0, X86_DECODE_CMD_FADD, 2, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 1, 3, X86_DECODE_CMD_FMUL, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 1, 0, X86_DECODE_CMD_FMUL, 2, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 4, 3, X86_DECODE_CMD_FSUB, 10, true, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 4, 0, X86_DECODE_CMD_FSUB, 2, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 5, 3, X86_DECODE_CMD_FSUB, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 5, 0, X86_DECODE_CMD_FSUB, 2, true, false,
+ decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 6, 3, X86_DECODE_CMD_FDIV, 10, true, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 6, 0, X86_DECODE_CMD_FDIV, 2, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+ {0xde, 7, 3, X86_DECODE_CMD_FDIV, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xde, 7, 0, X86_DECODE_CMD_FDIV, 2, true, false,
+ decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
+
+ {0xdf, 0, 0, X86_DECODE_CMD_FLD, 2, false, false,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 2, 3, X86_DECODE_CMD_FST, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 2, 0, X86_DECODE_CMD_FST, 2, false, false,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 3, 3, X86_DECODE_CMD_FST, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 3, 0, X86_DECODE_CMD_FST, 2, false, true,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 4, 3, X86_DECODE_CMD_FNSTSW, 2, false, true,
+ decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, true,
+ decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 5, 0, X86_DECODE_CMD_FLD, 8, false, false,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
+ {0xdf, 7, 0, X86_DECODE_CMD_FST, 8, false, true,
+ decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
};
-void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
addr_t ptr = 0;
x86_reg_segment seg = REG_SEG_DS;
@@ -1163,43 +1644,45 @@ void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode, struct x86_d
goto calc_addr;
}
- if (decode->displacement_size)
+ if (decode->displacement_size) {
ptr = sign(decode->displacement, decode->displacement_size);
+ }
switch (decode->modrm.rm) {
- case 0:
- ptr += BX(cpu) + SI(cpu);
- break;
- case 1:
- ptr += BX(cpu) + DI(cpu);
- break;
- case 2:
- ptr += BP(cpu) + SI(cpu);
- seg = REG_SEG_SS;
- break;
- case 3:
- ptr += BP(cpu) + DI(cpu);
- seg = REG_SEG_SS;
- break;
- case 4:
- ptr += SI(cpu);
- break;
- case 5:
- ptr += DI(cpu);
- break;
- case 6:
- ptr += BP(cpu);
- seg = REG_SEG_SS;
- break;
- case 7:
- ptr += BX(cpu);
- break;
+ case 0:
+ ptr += BX(cpu) + SI(cpu);
+ break;
+ case 1:
+ ptr += BX(cpu) + DI(cpu);
+ break;
+ case 2:
+ ptr += BP(cpu) + SI(cpu);
+ seg = REG_SEG_SS;
+ break;
+ case 3:
+ ptr += BP(cpu) + DI(cpu);
+ seg = REG_SEG_SS;
+ break;
+ case 4:
+ ptr += SI(cpu);
+ break;
+ case 5:
+ ptr += DI(cpu);
+ break;
+ case 6:
+ ptr += BP(cpu);
+ seg = REG_SEG_SS;
+ break;
+ case 7:
+ ptr += BX(cpu);
+ break;
}
calc_addr:
- if (X86_DECODE_CMD_LEA == decode->cmd)
+ if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = (uint16_t)ptr;
- else
+ } else {
op->ptr = decode_linear_addr(cpu, decode, (uint16_t)ptr, seg);
+ }
}
addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
@@ -1207,24 +1690,25 @@ addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
addr_t ptr = 0;
int which = 0;
- if (is_extended)
+ if (is_extended) {
reg |= REG_R8;
+ }
switch (size) {
- case 1:
- if (is_extended || reg < 4) {
- which = 1;
- ptr = (addr_t)&RL(cpu, reg);
- } else {
- which = 2;
- ptr = (addr_t)&RH(cpu, reg - 4);
- }
- break;
- default:
- which = 3;
- ptr = (addr_t)&RRX(cpu, reg);
- break;
+ case 1:
+ if (is_extended || reg < 4) {
+ which = 1;
+ ptr = (addr_t)&RL(cpu, reg);
+ } else {
+ which = 2;
+ ptr = (addr_t)&RH(cpu, reg - 4);
+ }
+ break;
+ default:
+ which = 3;
+ ptr = (addr_t)&RRX(cpu, reg);
+ break;
}
return ptr;
}
@@ -1232,11 +1716,12 @@ addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size)
{
addr_t val = 0;
- memcpy(&val, (void*)get_reg_ref(cpu, reg, is_extended, size), size);
+ memcpy(&val, (void *)get_reg_ref(cpu, reg, is_extended, size), size);
return val;
}
-static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode, x86_reg_segment *sel)
+static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode,
+ x86_reg_segment *sel)
{
addr_t base = 0;
addr_t scaled_index = 0;
@@ -1247,52 +1732,61 @@ static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode, x86_reg_segm
*sel = REG_SEG_DS;
if (decode->modrm.mod || base_reg != REG_RBP) {
- if (decode->rex.b)
+ if (decode->rex.b) {
base_reg |= REG_R8;
- if (REG_RSP == base_reg || REG_RBP == base_reg)
+ }
+ if (REG_RSP == base_reg || REG_RBP == base_reg) {
*sel = REG_SEG_SS;
+ }
base = get_reg_val(cpu, decode->sib.base, decode->rex.b, addr_size);
}
- if (decode->rex.x)
+ if (decode->rex.x) {
index_reg |= REG_R8;
+ }
- if (index_reg != REG_RSP)
- scaled_index = get_reg_val(cpu, index_reg, decode->rex.x, addr_size) << decode->sib.scale;
+ if (index_reg != REG_RSP) {
+ scaled_index = get_reg_val(cpu, index_reg, decode->rex.x, addr_size) <<
+ decode->sib.scale;
+ }
return base + scaled_index;
}
-void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
x86_reg_segment seg = REG_SEG_DS;
addr_t ptr = 0;
int addr_size = decode->addressing_size;
- if (decode->displacement_size)
+ if (decode->displacement_size) {
ptr = sign(decode->displacement, decode->displacement_size);
+ }
if (4 == decode->modrm.rm) {
ptr += get_sib_val(cpu, decode, &seg);
- }
- else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
- if (x86_is_long_mode(cpu))
+ } else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
+ if (x86_is_long_mode(cpu)) {
ptr += RIP(cpu) + decode->len;
- else
+ } else {
ptr = decode->displacement;
- }
- else {
- if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm)
+ }
+ } else {
+ if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm) {
seg = REG_SEG_SS;
+ }
ptr += get_reg_val(cpu, decode->modrm.rm, decode->rex.b, addr_size);
}
- if (X86_DECODE_CMD_LEA == decode->cmd)
+ if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = (uint32_t)ptr;
- else
+ } else {
op->ptr = decode_linear_addr(cpu, decode, (uint32_t)ptr, seg);
+ }
}
-void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
x86_reg_segment seg = REG_SEG_DS;
int32_t offset = 0;
@@ -1300,46 +1794,51 @@ void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode, struct x86_d
int rm = decode->modrm.rm;
addr_t ptr;
int src = decode->modrm.rm;
-
- if (decode->displacement_size)
+
+ if (decode->displacement_size) {
offset = sign(decode->displacement, decode->displacement_size);
+ }
- if (4 == rm)
+ if (4 == rm) {
ptr = get_sib_val(cpu, decode, &seg) + offset;
- else if (0 == mod && 5 == rm)
+ } else if (0 == mod && 5 == rm) {
ptr = RIP(cpu) + decode->len + (int32_t) offset;
- else
+ } else {
ptr = get_reg_val(cpu, src, decode->rex.b, 8) + (int64_t) offset;
-
- if (X86_DECODE_CMD_LEA == decode->cmd)
+ }
+
+ if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = ptr;
- else
+ } else {
op->ptr = decode_linear_addr(cpu, decode, ptr, seg);
+ }
}
-void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
+void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op)
{
if (3 == decode->modrm.mod) {
op->reg = decode->modrm.reg;
op->type = X86_VAR_REG;
- op->ptr = get_reg_ref(cpu, decode->modrm.rm, decode->rex.b, decode->operand_size);
+ op->ptr = get_reg_ref(cpu, decode->modrm.rm, decode->rex.b,
+ decode->operand_size);
return;
}
switch (decode->addressing_size) {
- case 2:
- calc_modrm_operand16(cpu, decode, op);
- break;
- case 4:
- calc_modrm_operand32(cpu, decode, op);
- break;
- case 8:
- calc_modrm_operand64(cpu, decode, op);
- break;
- default:
- VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
- break;
+ case 2:
+ calc_modrm_operand16(cpu, decode, op);
+ break;
+ case 4:
+ calc_modrm_operand32(cpu, decode, op);
+ break;
+ case 8:
+ calc_modrm_operand64(cpu, decode, op);
+ break;
+ default:
+ VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
+ break;
}
}
@@ -1348,36 +1847,36 @@ static void decode_prefix(CPUState *cpu, struct x86_decode *decode)
while (1) {
uint8_t byte = decode_byte(cpu, decode);
switch (byte) {
- case PREFIX_LOCK:
- decode->lock = byte;
- break;
- case PREFIX_REPN:
- case PREFIX_REP:
- decode->rep = byte;
- break;
- case PREFIX_CS_SEG_OVEERIDE:
- case PREFIX_SS_SEG_OVEERIDE:
- case PREFIX_DS_SEG_OVEERIDE:
- case PREFIX_ES_SEG_OVEERIDE:
- case PREFIX_FS_SEG_OVEERIDE:
- case PREFIX_GS_SEG_OVEERIDE:
- decode->segment_override = byte;
- break;
- case PREFIX_OP_SIZE_OVERRIDE:
- decode->op_size_override = byte;
- break;
- case PREFIX_ADDR_SIZE_OVERRIDE:
- decode->addr_size_override = byte;
+ case PREFIX_LOCK:
+ decode->lock = byte;
+ break;
+ case PREFIX_REPN:
+ case PREFIX_REP:
+ decode->rep = byte;
+ break;
+ case PREFIX_CS_SEG_OVEERIDE:
+ case PREFIX_SS_SEG_OVEERIDE:
+ case PREFIX_DS_SEG_OVEERIDE:
+ case PREFIX_ES_SEG_OVEERIDE:
+ case PREFIX_FS_SEG_OVEERIDE:
+ case PREFIX_GS_SEG_OVEERIDE:
+ decode->segment_override = byte;
+ break;
+ case PREFIX_OP_SIZE_OVERRIDE:
+ decode->op_size_override = byte;
+ break;
+ case PREFIX_ADDR_SIZE_OVERRIDE:
+ decode->addr_size_override = byte;
+ break;
+ case PREFIX_REX ... (PREFIX_REX + 0xf):
+ if (x86_is_long_mode(cpu)) {
+ decode->rex.rex = byte;
break;
- case PREFIX_REX ... (PREFIX_REX + 0xf):
- if (x86_is_long_mode(cpu)) {
- decode->rex.rex = byte;
- break;
- }
- // fall through when not in long mode
- default:
- decode->len--;
- return;
+ }
+ /* fall through when not in long mode */
+ default:
+ decode->len--;
+ return;
}
}
}
@@ -1386,33 +1885,36 @@ void set_addressing_size(CPUState *cpu, struct x86_decode *decode)
{
decode->addressing_size = -1;
if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
- if (decode->addr_size_override)
+ if (decode->addr_size_override) {
decode->addressing_size = 4;
- else
+ } else {
decode->addressing_size = 2;
- }
- else if (!x86_is_long_mode(cpu)) {
- // protected
+ }
+ } else if (!x86_is_long_mode(cpu)) {
+ /* protected */
struct vmx_segment cs;
vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
- // check db
+ /* check db */
if ((cs.ar >> 14) & 1) {
- if (decode->addr_size_override)
+ if (decode->addr_size_override) {
decode->addressing_size = 2;
- else
+ } else {
decode->addressing_size = 4;
+ }
} else {
- if (decode->addr_size_override)
+ if (decode->addr_size_override) {
decode->addressing_size = 4;
- else
+ } else {
decode->addressing_size = 2;
+ }
}
} else {
- // long
- if (decode->addr_size_override)
+ /* long */
+ if (decode->addr_size_override) {
decode->addressing_size = 4;
- else
+ } else {
decode->addressing_size = 8;
+ }
}
}
@@ -1420,99 +1922,98 @@ void set_operand_size(CPUState *cpu, struct x86_decode *decode)
{
decode->operand_size = -1;
if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
- if (decode->op_size_override)
+ if (decode->op_size_override) {
decode->operand_size = 4;
- else
+ } else {
decode->operand_size = 2;
- }
- else if (!x86_is_long_mode(cpu)) {
- // protected
+ }
+ } else if (!x86_is_long_mode(cpu)) {
+ /* protected */
struct vmx_segment cs;
vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
- // check db
+ /* check db */
if ((cs.ar >> 14) & 1) {
- if (decode->op_size_override)
+ if (decode->op_size_override) {
decode->operand_size = 2;
- else
+ } else{
decode->operand_size = 4;
+ }
} else {
- if (decode->op_size_override)
+ if (decode->op_size_override) {
decode->operand_size = 4;
- else
+ } else {
decode->operand_size = 2;
+ }
}
} else {
- // long
- if (decode->op_size_override)
+ /* long */
+ if (decode->op_size_override) {
decode->operand_size = 2;
- else
+ } else {
decode->operand_size = 4;
+ }
- if (decode->rex.w)
+ if (decode->rex.w) {
decode->operand_size = 8;
+ }
}
}
static void decode_sib(CPUState *cpu, struct x86_decode *decode)
{
- if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) && (decode->addressing_size != 2)) {
+ if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) &&
+ (decode->addressing_size != 2)) {
decode->sib.sib = decode_byte(cpu, decode);
decode->sib_present = true;
}
}
-/* 16 bit modrm
- * mod R/M
- * 00 [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] [disp16] [BX]
- * 01 [BX+SI+disp8] [BX+DI+disp8] [BP+SI+disp8] [BP+DI+disp8] [SI+disp8] [DI+disp8] [BP+disp8] [BX+disp8]
- * 10 [BX+SI+disp16] [BX+DI+disp16] [BP+SI+disp16] [BP+DI+disp16] [SI+disp16] [DI+disp16] [BP+disp16] [BX+disp16]
- * 11 - - - - - - - -
- */
-int disp16_tbl[4][8] =
- {{0, 0, 0, 0, 0, 0, 2, 0},
+/* 16 bit modrm */
+int disp16_tbl[4][8] = {
+ {0, 0, 0, 0, 0, 0, 2, 0},
{1, 1, 1, 1, 1, 1, 1, 1},
{2, 2, 2, 2, 2, 2, 2, 2},
- {0, 0, 0, 0, 0, 0, 0, 0}};
+ {0, 0, 0, 0, 0, 0, 0, 0}
+};
-/*
- 32/64-bit modrm
- Mod
- 00 [r/m] [r/m] [r/m] [r/m] [SIB] [RIP/EIP1,2+disp32] [r/m] [r/m]
- 01 [r/m+disp8] [r/m+disp8] [r/m+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8]
- 10 [r/m+disp32] [r/m+disp32] [r/m+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32]
- 11 - - - - - - - -
- */
-int disp32_tbl[4][8] =
- {{0, 0, 0, 0, -1, 4, 0, 0},
+/* 32/64-bit modrm */
+int disp32_tbl[4][8] = {
+ {0, 0, 0, 0, -1, 4, 0, 0},
{1, 1, 1, 1, 1, 1, 1, 1},
{4, 4, 4, 4, 4, 4, 4, 4},
- {0, 0, 0, 0, 0, 0, 0, 0}};
+ {0, 0, 0, 0, 0, 0, 0, 0}
+};
static inline void decode_displacement(CPUState *cpu, struct x86_decode *decode)
{
int addressing_size = decode->addressing_size;
int mod = decode->modrm.mod;
int rm = decode->modrm.rm;
-
+
decode->displacement_size = 0;
switch (addressing_size) {
- case 2:
- decode->displacement_size = disp16_tbl[mod][rm];
- if (decode->displacement_size)
- decode->displacement = (uint16_t)decode_bytes(cpu, decode, decode->displacement_size);
- break;
- case 4:
- case 8:
- if (-1 == disp32_tbl[mod][rm]) {
- if (5 == decode->sib.base)
- decode->displacement_size = 4;
+ case 2:
+ decode->displacement_size = disp16_tbl[mod][rm];
+ if (decode->displacement_size) {
+ decode->displacement = (uint16_t)decode_bytes(cpu, decode,
+ decode->displacement_size);
+ }
+ break;
+ case 4:
+ case 8:
+ if (-1 == disp32_tbl[mod][rm]) {
+ if (5 == decode->sib.base) {
+ decode->displacement_size = 4;
}
- else
- decode->displacement_size = disp32_tbl[mod][rm];
-
- if (decode->displacement_size)
- decode->displacement = (uint32_t)decode_bytes(cpu, decode, decode->displacement_size);
- break;
+ } else {
+ decode->displacement_size = disp32_tbl[mod][rm];
+ }
+
+ if (decode->displacement_size) {
+ decode->displacement = (uint32_t)decode_bytes(cpu, decode,
+ decode->displacement_size);
+ }
+ break;
}
}
@@ -1520,40 +2021,52 @@ static inline void decode_modrm(CPUState *cpu, struct x86_decode *decode)
{
decode->modrm.modrm = decode_byte(cpu, decode);
decode->is_modrm = true;
-
+
decode_sib(cpu, decode);
decode_displacement(cpu, decode);
}
-static inline void decode_opcode_general(CPUState *cpu, struct x86_decode *decode, uint8_t opcode, struct decode_tbl *inst_decoder)
+static inline void decode_opcode_general(CPUState *cpu,
+ struct x86_decode *decode,
+ uint8_t opcode,
+ struct decode_tbl *inst_decoder)
{
decode->cmd = inst_decoder->cmd;
- if (inst_decoder->operand_size)
+ if (inst_decoder->operand_size) {
decode->operand_size = inst_decoder->operand_size;
+ }
decode->flags_mask = inst_decoder->flags_mask;
-
- if (inst_decoder->is_modrm)
+
+ if (inst_decoder->is_modrm) {
decode_modrm(cpu, decode);
- if (inst_decoder->decode_op1)
+ }
+ if (inst_decoder->decode_op1) {
inst_decoder->decode_op1(cpu, decode, &decode->op[0]);
- if (inst_decoder->decode_op2)
+ }
+ if (inst_decoder->decode_op2) {
inst_decoder->decode_op2(cpu, decode, &decode->op[1]);
- if (inst_decoder->decode_op3)
+ }
+ if (inst_decoder->decode_op3) {
inst_decoder->decode_op3(cpu, decode, &decode->op[2]);
- if (inst_decoder->decode_op4)
+ }
+ if (inst_decoder->decode_op4) {
inst_decoder->decode_op4(cpu, decode, &decode->op[3]);
- if (inst_decoder->decode_postfix)
+ }
+ if (inst_decoder->decode_postfix) {
inst_decoder->decode_postfix(cpu, decode);
+ }
}
-static inline void decode_opcode_1(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
+static inline void decode_opcode_1(CPUState *cpu, struct x86_decode *decode,
+ uint8_t opcode)
{
struct decode_tbl *inst_decoder = &_decode_tbl1[opcode];
decode_opcode_general(cpu, decode, opcode, inst_decoder);
}
-static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
+static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode,
+ uint8_t opcode)
{
struct decode_tbl *inst_decoder = &_decode_tbl2[opcode];
decode_opcode_general(cpu, decode, opcode, inst_decoder);
@@ -1562,7 +2075,7 @@ static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode, uin
static void decode_opcodes(CPUState *cpu, struct x86_decode *decode)
{
uint8_t opcode;
-
+
opcode = decode_byte(cpu, decode);
decode->opcode[decode->opcode_len++] = opcode;
if (opcode != OPCODE_ESCAPE) {
@@ -1583,21 +2096,24 @@ uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode)
set_operand_size(cpu, decode);
decode_opcodes(cpu, decode);
-
+
return decode->len;
}
void init_decoder(CPUState *cpu)
{
int i;
-
- for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
+
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++) {
memcpy(_decode_tbl1, &invl_inst, sizeof(invl_inst));
- for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
+ }
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++) {
memcpy(_decode_tbl2, &invl_inst, sizeof(invl_inst));
- for (i = 0; i < ARRAY_SIZE(_decode_tbl3); i++)
+ }
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl3); i++) {
memcpy(_decode_tbl3, &invl_inst, sizeof(invl_inst_x87));
-
+ }
+
for (i = 0; i < ARRAY_SIZE(_1op_inst); i++) {
_decode_tbl1[_1op_inst[i].opcode] = _1op_inst[i];
}
@@ -1605,7 +2121,9 @@ void init_decoder(CPUState *cpu)
_decode_tbl2[_2op_inst[i].opcode] = _2op_inst[i];
}
for (i = 0; i < ARRAY_SIZE(_x87_inst); i++) {
- int index = ((_x87_inst[i].opcode & 0xf) << 4) | ((_x87_inst[i].modrm_mod & 1) << 3) | _x87_inst[i].modrm_reg;
+ int index = ((_x87_inst[i].opcode & 0xf) << 4) |
+ ((_x87_inst[i].modrm_mod & 1) << 3) |
+ _x87_inst[i].modrm_reg;
_decode_tbl3[index] = _x87_inst[i];
}
}
@@ -1613,47 +2131,55 @@ void init_decoder(CPUState *cpu)
const char *decode_cmd_to_string(enum x86_decode_cmd cmd)
{
- static const char *cmds[] = {"INVL", "PUSH", "PUSH_SEG", "POP", "POP_SEG", "MOV", "MOVSX", "MOVZX", "CALL_NEAR",
- "CALL_NEAR_ABS_INDIRECT", "CALL_FAR_ABS_INDIRECT", "CMD_CALL_FAR", "RET_NEAR", "RET_FAR", "ADD", "OR",
- "ADC", "SBB", "AND", "SUB", "XOR", "CMP", "INC", "DEC", "TST", "NOT", "NEG", "JMP_NEAR", "JMP_NEAR_ABS_INDIRECT",
- "JMP_FAR", "JMP_FAR_ABS_INDIRECT", "LEA", "JXX",
- "JCXZ", "SETXX", "MOV_TO_SEG", "MOV_FROM_SEG", "CLI", "STI", "CLD", "STD", "STC",
- "CLC", "OUT", "IN", "INS", "OUTS", "LIDT", "SIDT", "LGDT", "SGDT", "SMSW", "LMSW", "RDTSCP", "INVLPG", "MOV_TO_CR",
- "MOV_FROM_CR", "MOV_TO_DR", "MOV_FROM_DR", "PUSHF", "POPF", "CPUID", "ROL", "ROR", "RCL", "RCR", "SHL", "SAL",
- "SHR","SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL", "IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS",
- "LODS", "STOS", "BSWAP", "XCHG", "RDTSC", "RDMSR", "WRMSR", "ENTER", "LEAVE", "BT", "BTS", "BTC", "BTR", "BSF",
- "BSR", "IRET", "INT", "POPA", "PUSHA", "CWD", "CBW", "DAS", "AAD", "AAM", "AAS", "LOOP", "SLDT", "STR", "LLDT",
- "LTR", "VERR", "VERW", "SAHF", "LAHF", "WBINVD", "LDS", "LSS", "LES", "LGS", "LFS", "CMC", "XLAT", "NOP", "CMOV",
- "CLTS", "XADD", "HLT", "CMPXCHG8B", "CMPXCHG", "POPCNT",
- "FNINIT", "FLD", "FLDxx", "FNSTCW", "FNSTSW", "FNSETPM", "FSAVE", "FRSTOR", "FXSAVE", "FXRSTOR", "FDIV", "FMUL",
- "FSUB", "FADD", "EMMS", "MFENCE", "SFENCE", "LFENCE", "PREFETCH", "FST", "FABS", "FUCOM", "FUCOMI", "FLDCW",
+ static const char *cmds[] = {"INVL", "PUSH", "PUSH_SEG", "POP", "POP_SEG",
+ "MOV", "MOVSX", "MOVZX", "CALL_NEAR", "CALL_NEAR_ABS_INDIRECT",
+ "CALL_FAR_ABS_INDIRECT", "CMD_CALL_FAR", "RET_NEAR", "RET_FAR", "ADD",
+ "OR", "ADC", "SBB", "AND", "SUB", "XOR", "CMP", "INC", "DEC", "TST",
+ "NOT", "NEG", "JMP_NEAR", "JMP_NEAR_ABS_INDIRECT", "JMP_FAR",
+ "JMP_FAR_ABS_INDIRECT", "LEA", "JXX", "JCXZ", "SETXX", "MOV_TO_SEG",
+ "MOV_FROM_SEG", "CLI", "STI", "CLD", "STD", "STC", "CLC", "OUT", "IN",
+ "INS", "OUTS", "LIDT", "SIDT", "LGDT", "SGDT", "SMSW", "LMSW",
+ "RDTSCP", "INVLPG", "MOV_TO_CR", "MOV_FROM_CR", "MOV_TO_DR",
+ "MOV_FROM_DR", "PUSHF", "POPF", "CPUID", "ROL", "ROR", "RCL", "RCR",
+ "SHL", "SAL", "SHR", "SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL",
+ "IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS", "LODS", "STOS",
+ "BSWAP", "XCHG", "RDTSC", "RDMSR", "WRMSR", "ENTER", "LEAVE", "BT",
+ "BTS", "BTC", "BTR", "BSF", "BSR", "IRET", "INT", "POPA", "PUSHA",
+ "CWD", "CBW", "DAS", "AAD", "AAM", "AAS", "LOOP", "SLDT", "STR", "LLDT",
+ "LTR", "VERR", "VERW", "SAHF", "LAHF", "WBINVD", "LDS", "LSS", "LES",
+ "LGS", "LFS", "CMC", "XLAT", "NOP", "CMOV", "CLTS", "XADD", "HLT",
+ "CMPXCHG8B", "CMPXCHG", "POPCNT", "FNINIT", "FLD", "FLDxx", "FNSTCW",
+ "FNSTSW", "FNSETPM", "FSAVE", "FRSTOR", "FXSAVE", "FXRSTOR", "FDIV",
+ "FMUL", "FSUB", "FADD", "EMMS", "MFENCE", "SFENCE", "LFENCE",
+ "PREFETCH", "FST", "FABS", "FUCOM", "FUCOMI", "FLDCW",
"FXCH", "FCHS", "FCMOV", "FRNDINT", "FXAM", "LAST"};
return cmds[cmd];
}
-addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg)
+addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode,
+ addr_t addr, x86_reg_segment seg)
{
switch (decode->segment_override) {
- case PREFIX_CS_SEG_OVEERIDE:
- seg = REG_SEG_CS;
- break;
- case PREFIX_SS_SEG_OVEERIDE:
- seg = REG_SEG_SS;
- break;
- case PREFIX_DS_SEG_OVEERIDE:
- seg = REG_SEG_DS;
- break;
- case PREFIX_ES_SEG_OVEERIDE:
- seg = REG_SEG_ES;
- break;
- case PREFIX_FS_SEG_OVEERIDE:
- seg = REG_SEG_FS;
- break;
- case PREFIX_GS_SEG_OVEERIDE:
- seg = REG_SEG_GS;
- break;
- default:
- break;
+ case PREFIX_CS_SEG_OVEERIDE:
+ seg = REG_SEG_CS;
+ break;
+ case PREFIX_SS_SEG_OVEERIDE:
+ seg = REG_SEG_SS;
+ break;
+ case PREFIX_DS_SEG_OVEERIDE:
+ seg = REG_SEG_DS;
+ break;
+ case PREFIX_ES_SEG_OVEERIDE:
+ seg = REG_SEG_ES;
+ break;
+ case PREFIX_FS_SEG_OVEERIDE:
+ seg = REG_SEG_FS;
+ break;
+ case PREFIX_GS_SEG_OVEERIDE:
+ seg = REG_SEG_GS;
+ break;
+ default:
+ break;
}
return linear_addr_size(cpu, addr, decode->addressing_size, seg);
}
diff --git a/target/i386/hvf-utils/x86_decode.h b/target/i386/hvf-utils/x86_decode.h
index 3a22d7d1a5..b6763e1ba1 100644
--- a/target/i386/hvf-utils/x86_decode.h
+++ b/target/i386/hvf-utils/x86_decode.h
@@ -25,20 +25,20 @@
#include "x86.h"
typedef enum x86_prefix {
- // group 1
+ /* group 1 */
PREFIX_LOCK = 0xf0,
PREFIX_REPN = 0xf2,
PREFIX_REP = 0xf3,
- // group 2
+ /* group 2 */
PREFIX_CS_SEG_OVEERIDE = 0x2e,
PREFIX_SS_SEG_OVEERIDE = 0x36,
PREFIX_DS_SEG_OVEERIDE = 0x3e,
PREFIX_ES_SEG_OVEERIDE = 0x26,
PREFIX_FS_SEG_OVEERIDE = 0x64,
PREFIX_GS_SEG_OVEERIDE = 0x65,
- // group 3
+ /* group 3 */
PREFIX_OP_SIZE_OVERRIDE = 0x66,
- // group 4
+ /* group 4 */
PREFIX_ADDR_SIZE_OVERRIDE = 0x67,
PREFIX_REX = 0x40,
@@ -46,7 +46,7 @@ typedef enum x86_prefix {
enum x86_decode_cmd {
X86_DECODE_CMD_INVL = 0,
-
+
X86_DECODE_CMD_PUSH,
X86_DECODE_CMD_PUSH_SEG,
X86_DECODE_CMD_POP,
@@ -177,7 +177,7 @@ enum x86_decode_cmd {
X86_DECODE_CMD_CMPXCHG8B,
X86_DECODE_CMD_CMPXCHG,
X86_DECODE_CMD_POPCNT,
-
+
X86_DECODE_CMD_FNINIT,
X86_DECODE_CMD_FLD,
X86_DECODE_CMD_FLDxx,
@@ -255,7 +255,7 @@ typedef enum x86_var_type {
X86_VAR_REG,
X86_VAR_RM,
- // for floating point computations
+ /* for floating point computations */
X87_VAR_REG,
X87_VAR_FLOATP,
X87_VAR_INTP,
@@ -308,7 +308,17 @@ uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode);
addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size);
addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size);
-void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op);
-addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg);
+void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op);
+addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode,
+ addr_t addr, x86_reg_segment seg);
-void init_decoder(CPUState* cpu);
+void init_decoder(CPUState *cpu);
+void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op);
+void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op);
+void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode,
+ struct x86_decode_op *op);
+void set_addressing_size(CPUState *cpu, struct x86_decode *decode);
+void set_operand_size(CPUState *cpu, struct x86_decode *decode);
diff --git a/target/i386/hvf-utils/x86_descr.h b/target/i386/hvf-utils/x86_descr.h
index 78fb1bc420..f5e247782b 100644
--- a/target/i386/hvf-utils/x86_descr.h
+++ b/target/i386/hvf-utils/x86_descr.h
@@ -27,14 +27,29 @@ typedef struct vmx_segment {
uint64_t ar;
} vmx_segment;
-// deal with vmstate descriptors
-void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
-void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
+/* deal with vmstate descriptors */
+void vmx_read_segment_descriptor(struct CPUState *cpu,
+ struct vmx_segment *desc, x86_reg_segment seg);
+void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc,
+ x86_reg_segment seg);
-x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, x86_reg_segment seg);
-void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg);
+x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu,
+ x86_reg_segment seg);
+void vmx_write_segment_selector(struct CPUState *cpu,
+ x68_segment_selector selector,
+ x86_reg_segment seg);
uint64_t vmx_read_segment_base(struct CPUState *cpu, x86_reg_segment seg);
-void vmx_write_segment_base(struct CPUState *cpu, x86_reg_segment seg, uint64_t base);
+void vmx_write_segment_base(struct CPUState *cpu, x86_reg_segment seg,
+ uint64_t base);
-void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc);
+void x86_segment_descriptor_to_vmx(struct CPUState *cpu,
+ x68_segment_selector selector,
+ struct x86_segment_descriptor *desc,
+ struct vmx_segment *vmx_desc);
+
+uint32_t vmx_read_segment_limit(CPUState *cpu, x86_reg_segment seg);
+uint32_t vmx_read_segment_ar(CPUState *cpu, x86_reg_segment seg);
+void vmx_segment_to_x86_descriptor(struct CPUState *cpu,
+ struct vmx_segment *vmx_desc,
+ struct x86_segment_descriptor *desc);
diff --git a/target/i386/hvf-utils/x86_emu.c b/target/i386/hvf-utils/x86_emu.c
index 8b5efc76f0..dc33cd2576 100644
--- a/target/i386/hvf-utils/x86_emu.c
+++ b/target/i386/hvf-utils/x86_emu.c
@@ -45,8 +45,8 @@
#include "vmcs.h"
#include "vmx.h"
-static void print_debug(struct CPUState *cpu);
-void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count);
+void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
+ int direction, int size, uint32_t count);
#define EXEC_2OP_LOGIC_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
{ \
@@ -57,8 +57,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
uint8_t v1 = (uint8_t)decode->op[0].val; \
uint8_t v2 = (uint8_t)decode->op[1].val; \
uint8_t diff = v1 cmd v2; \
- if (save_res) \
+ if (save_res) { \
write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
+ } \
FLAGS_FUNC##_8(diff); \
break; \
} \
@@ -67,8 +68,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
uint16_t v1 = (uint16_t)decode->op[0].val; \
uint16_t v2 = (uint16_t)decode->op[1].val; \
uint16_t diff = v1 cmd v2; \
- if (save_res) \
+ if (save_res) { \
write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
+ } \
FLAGS_FUNC##_16(diff); \
break; \
} \
@@ -77,8 +79,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
uint32_t v1 = (uint32_t)decode->op[0].val; \
uint32_t v2 = (uint32_t)decode->op[1].val; \
uint32_t diff = v1 cmd v2; \
- if (save_res) \
+ if (save_res) { \
write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
+ } \
FLAGS_FUNC##_32(diff); \
break; \
} \
@@ -97,8 +100,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
uint8_t v1 = (uint8_t)decode->op[0].val; \
uint8_t v2 = (uint8_t)decode->op[1].val; \
uint8_t diff = v1 cmd v2; \
- if (save_res) \
+ if (save_res) { \
write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
+ } \
FLAGS_FUNC##_8(v1, v2, diff); \
break; \
} \
@@ -107,8 +111,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
uint16_t v1 = (uint16_t)decode->op[0].val; \
uint16_t v2 = (uint16_t)decode->op[1].val; \
uint16_t diff = v1 cmd v2; \
- if (save_res) \
+ if (save_res) { \
write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
+ } \
FLAGS_FUNC##_16(v1, v2, diff); \
break; \
} \
@@ -117,8 +122,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
uint32_t v1 = (uint32_t)decode->op[0].val; \
uint32_t v2 = (uint32_t)decode->op[1].val; \
uint32_t diff = v1 cmd v2; \
- if (save_res) \
+ if (save_res) { \
write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
+ } \
FLAGS_FUNC##_32(v1, v2, diff); \
break; \
} \
@@ -127,63 +133,63 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int directio
} \
}
-addr_t read_reg(struct CPUState* cpu, int reg, int size)
+addr_t read_reg(struct CPUState *cpu, int reg, int size)
{
switch (size) {
- case 1:
- return cpu->hvf_x86->regs[reg].lx;
- case 2:
- return cpu->hvf_x86->regs[reg].rx;
- case 4:
- return cpu->hvf_x86->regs[reg].erx;
- case 8:
- return cpu->hvf_x86->regs[reg].rrx;
- default:
- VM_PANIC_ON("read_reg size");
+ case 1:
+ return cpu->hvf_x86->regs[reg].lx;
+ case 2:
+ return cpu->hvf_x86->regs[reg].rx;
+ case 4:
+ return cpu->hvf_x86->regs[reg].erx;
+ case 8:
+ return cpu->hvf_x86->regs[reg].rrx;
+ default:
+ VM_PANIC_ON("read_reg size");
}
return 0;
}
-void write_reg(struct CPUState* cpu, int reg, addr_t val, int size)
+void write_reg(struct CPUState *cpu, int reg, addr_t val, int size)
{
switch (size) {
- case 1:
- cpu->hvf_x86->regs[reg].lx = val;
- break;
- case 2:
- cpu->hvf_x86->regs[reg].rx = val;
- break;
- case 4:
- cpu->hvf_x86->regs[reg].rrx = (uint32_t)val;
- break;
- case 8:
- cpu->hvf_x86->regs[reg].rrx = val;
- break;
- default:
- VM_PANIC_ON("write_reg size");
+ case 1:
+ cpu->hvf_x86->regs[reg].lx = val;
+ break;
+ case 2:
+ cpu->hvf_x86->regs[reg].rx = val;
+ break;
+ case 4:
+ cpu->hvf_x86->regs[reg].rrx = (uint32_t)val;
+ break;
+ case 8:
+ cpu->hvf_x86->regs[reg].rrx = val;
+ break;
+ default:
+ VM_PANIC_ON("write_reg size");
}
}
addr_t read_val_from_reg(addr_t reg_ptr, int size)
{
addr_t val;
-
+
switch (size) {
- case 1:
- val = *(uint8_t*)reg_ptr;
- break;
- case 2:
- val = *(uint16_t*)reg_ptr;
- break;
- case 4:
- val = *(uint32_t*)reg_ptr;
- break;
- case 8:
- val = *(uint64_t*)reg_ptr;
- break;
- default:
- VM_PANIC_ON_EX(1, "read_val: Unknown size %d\n", size);
- break;
+ case 1:
+ val = *(uint8_t *)reg_ptr;
+ break;
+ case 2:
+ val = *(uint16_t *)reg_ptr;
+ break;
+ case 4:
+ val = *(uint32_t *)reg_ptr;
+ break;
+ case 8:
+ val = *(uint64_t *)reg_ptr;
+ break;
+ default:
+ VM_PANIC_ON_EX(1, "read_val: Unknown size %d\n", size);
+ break;
}
return val;
}
@@ -191,30 +197,32 @@ addr_t read_val_from_reg(addr_t reg_ptr, int size)
void write_val_to_reg(addr_t reg_ptr, addr_t val, int size)
{
switch (size) {
- case 1:
- *(uint8_t*)reg_ptr = val;
- break;
- case 2:
- *(uint16_t*)reg_ptr = val;
- break;
- case 4:
- *(uint64_t*)reg_ptr = (uint32_t)val;
- break;
- case 8:
- *(uint64_t*)reg_ptr = val;
- break;
- default:
- VM_PANIC("write_val: Unknown size\n");
- break;
+ case 1:
+ *(uint8_t *)reg_ptr = val;
+ break;
+ case 2:
+ *(uint16_t *)reg_ptr = val;
+ break;
+ case 4:
+ *(uint64_t *)reg_ptr = (uint32_t)val;
+ break;
+ case 8:
+ *(uint64_t *)reg_ptr = val;
+ break;
+ default:
+ VM_PANIC("write_val: Unknown size\n");
+ break;
}
}
-static bool is_host_reg(struct CPUState* cpu, addr_t ptr) {
+static bool is_host_reg(struct CPUState *cpu, addr_t ptr)
+{
return (ptr > (addr_t)cpu && ptr < (addr_t)cpu + sizeof(struct CPUState)) ||
- (ptr > (addr_t)cpu->hvf_x86 && ptr < (addr_t)(cpu->hvf_x86 + sizeof(struct hvf_x86_state)));
+ (ptr > (addr_t)cpu->hvf_x86 && ptr <
+ (addr_t)(cpu->hvf_x86 + sizeof(struct hvf_x86_state)));
}
-void write_val_ext(struct CPUState* cpu, addr_t ptr, addr_t val, int size)
+void write_val_ext(struct CPUState *cpu, addr_t ptr, addr_t val, int size)
{
if (is_host_reg(cpu, ptr)) {
write_val_to_reg(ptr, val, size);
@@ -223,68 +231,77 @@ void write_val_ext(struct CPUState* cpu, addr_t ptr, addr_t val, int size)
vmx_write_mem(cpu, ptr, &val, size);
}
-uint8_t *read_mmio(struct CPUState* cpu, addr_t ptr, int bytes)
+uint8_t *read_mmio(struct CPUState *cpu, addr_t ptr, int bytes)
{
vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, ptr, bytes);
return cpu->hvf_x86->mmio_buf;
}
-addr_t read_val_ext(struct CPUState* cpu, addr_t ptr, int size)
+addr_t read_val_ext(struct CPUState *cpu, addr_t ptr, int size)
{
addr_t val;
uint8_t *mmio_ptr;
-
+
if (is_host_reg(cpu, ptr)) {
return read_val_from_reg(ptr, size);
}
-
+
mmio_ptr = read_mmio(cpu, ptr, size);
switch (size) {
- case 1:
- val = *(uint8_t*)mmio_ptr;
- break;
- case 2:
- val = *(uint16_t*)mmio_ptr;
- break;
- case 4:
- val = *(uint32_t*)mmio_ptr;
- break;
- case 8:
- val = *(uint64_t*)mmio_ptr;
- break;
- default:
- VM_PANIC("bad size\n");
- break;
+ case 1:
+ val = *(uint8_t *)mmio_ptr;
+ break;
+ case 2:
+ val = *(uint16_t *)mmio_ptr;
+ break;
+ case 4:
+ val = *(uint32_t *)mmio_ptr;
+ break;
+ case 8:
+ val = *(uint64_t *)mmio_ptr;
+ break;
+ default:
+ VM_PANIC("bad size\n");
+ break;
}
return val;
}
-static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode, int n, bool val_op0, bool val_op1, bool val_op2)
+static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode,
+ int n, bool val_op0, bool val_op1, bool val_op2)
{
int i;
bool calc_val[3] = {val_op0, val_op1, val_op2};
for (i = 0; i < n; i++) {
switch (decode->op[i].type) {
- case X86_VAR_IMMEDIATE:
- break;
- case X86_VAR_REG:
- VM_PANIC_ON(!decode->op[i].ptr);
- if (calc_val[i])
- decode->op[i].val = read_val_from_reg(decode->op[i].ptr, decode->operand_size);
- break;
- case X86_VAR_RM:
- calc_modrm_operand(cpu, decode, &decode->op[i]);
- if (calc_val[i])
- decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
- break;
- case X86_VAR_OFFSET:
- decode->op[i].ptr = decode_linear_addr(cpu, decode, decode->op[i].ptr, REG_SEG_DS);
- if (calc_val[i])
- decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
- break;
- default:
- break;
+ case X86_VAR_IMMEDIATE:
+ break;
+ case X86_VAR_REG:
+ VM_PANIC_ON(!decode->op[i].ptr);
+ if (calc_val[i]) {
+ decode->op[i].val = read_val_from_reg(decode->op[i].ptr,
+ decode->operand_size);
+ }
+ break;
+ case X86_VAR_RM:
+ calc_modrm_operand(cpu, decode, &decode->op[i]);
+ if (calc_val[i]) {
+ decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr,
+ decode->operand_size);
+ }
+ break;
+ case X86_VAR_OFFSET:
+ decode->op[i].ptr = decode_linear_addr(cpu, decode,
+ decode->op[i].ptr,
+ REG_SEG_DS);
+ if (calc_val[i]) {
+ decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr,
+ decode->operand_size);
+ }
+ break;
+ default:
+ break;
}
}
}
@@ -292,7 +309,8 @@ static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode, int
static void exec_mov(struct CPUState *cpu, struct x86_decode *decode)
{
fetch_operands(cpu, decode, 2, false, true, false);
- write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val,
+ decode->operand_size);
RIP(cpu) += decode->len;
}
@@ -341,7 +359,7 @@ static void exec_xor(struct CPUState *cpu, struct x86_decode *decode)
static void exec_neg(struct CPUState *cpu, struct x86_decode *decode)
{
- //EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ /*EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/
int32_t val;
fetch_operands(cpu, decode, 2, true, true, false);
@@ -350,17 +368,15 @@ static void exec_neg(struct CPUState *cpu, struct x86_decode *decode)
if (4 == decode->operand_size) {
SET_FLAGS_OSZAPC_SUB_32(0, 0 - val, val);
- }
- else if (2 == decode->operand_size) {
+ } else if (2 == decode->operand_size) {
SET_FLAGS_OSZAPC_SUB_16(0, 0 - val, val);
- }
- else if (1 == decode->operand_size) {
+ } else if (1 == decode->operand_size) {
SET_FLAGS_OSZAPC_SUB_8(0, 0 - val, val);
} else {
VM_PANIC("bad op size\n");
}
- //lflags_to_rflags(cpu);
+ /*lflags_to_rflags(cpu);*/
RIP(cpu) += decode->len;
}
@@ -399,7 +415,8 @@ static void exec_not(struct CPUState *cpu, struct x86_decode *decode)
{
fetch_operands(cpu, decode, 1, true, false, false);
- write_val_ext(cpu, decode->op[0].ptr, ~decode->op[0].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[0].ptr, ~decode->op[0].val,
+ decode->operand_size);
RIP(cpu) += decode->len;
}
@@ -410,10 +427,11 @@ void exec_movzx(struct CPUState *cpu, struct x86_decode *decode)
fetch_operands(cpu, decode, 1, false, false, false);
- if (0xb6 == decode->opcode[1])
+ if (0xb6 == decode->opcode[1]) {
src_op_size = 1;
- else
+ } else {
src_op_size = 2;
+ }
decode->operand_size = src_op_size;
calc_modrm_operand(cpu, decode, &decode->op[1]);
decode->op[1].val = read_val_ext(cpu, decode->op[1].ptr, src_op_size);
@@ -425,21 +443,22 @@ void exec_movzx(struct CPUState *cpu, struct x86_decode *decode)
static void exec_out(struct CPUState *cpu, struct x86_decode *decode)
{
switch (decode->opcode[0]) {
- case 0xe6:
- hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 1, 1, 1);
- break;
- case 0xe7:
- hvf_handle_io(cpu, decode->op[0].val, &RAX(cpu), 1, decode->operand_size, 1);
- break;
- case 0xee:
- hvf_handle_io(cpu, DX(cpu), &AL(cpu), 1, 1, 1);
- break;
- case 0xef:
- hvf_handle_io(cpu, DX(cpu), &RAX(cpu), 1, decode->operand_size, 1);
- break;
- default:
- VM_PANIC("Bad out opcode\n");
- break;
+ case 0xe6:
+ hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 1, 1, 1);
+ break;
+ case 0xe7:
+ hvf_handle_io(cpu, decode->op[0].val, &RAX(cpu), 1,
+ decode->operand_size, 1);
+ break;
+ case 0xee:
+ hvf_handle_io(cpu, DX(cpu), &AL(cpu), 1, 1, 1);
+ break;
+ case 0xef:
+ hvf_handle_io(cpu, DX(cpu), &RAX(cpu), 1, decode->operand_size, 1);
+ break;
+ default:
+ VM_PANIC("Bad out opcode\n");
+ break;
}
RIP(cpu) += decode->len;
}
@@ -448,63 +467,73 @@ static void exec_in(struct CPUState *cpu, struct x86_decode *decode)
{
addr_t val = 0;
switch (decode->opcode[0]) {
- case 0xe4:
- hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 0, 1, 1);
- break;
- case 0xe5:
- hvf_handle_io(cpu, decode->op[0].val, &val, 0, decode->operand_size, 1);
- if (decode->operand_size == 2)
- AX(cpu) = val;
- else
- RAX(cpu) = (uint32_t)val;
- break;
- case 0xec:
- hvf_handle_io(cpu, DX(cpu), &AL(cpu), 0, 1, 1);
- break;
- case 0xed:
- hvf_handle_io(cpu, DX(cpu), &val, 0, decode->operand_size, 1);
- if (decode->operand_size == 2)
- AX(cpu) = val;
- else
- RAX(cpu) = (uint32_t)val;
+ case 0xe4:
+ hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 0, 1, 1);
+ break;
+ case 0xe5:
+ hvf_handle_io(cpu, decode->op[0].val, &val, 0, decode->operand_size, 1);
+ if (decode->operand_size == 2) {
+ AX(cpu) = val;
+ } else {
+ RAX(cpu) = (uint32_t)val;
+ }
+ break;
+ case 0xec:
+ hvf_handle_io(cpu, DX(cpu), &AL(cpu), 0, 1, 1);
+ break;
+ case 0xed:
+ hvf_handle_io(cpu, DX(cpu), &val, 0, decode->operand_size, 1);
+ if (decode->operand_size == 2) {
+ AX(cpu) = val;
+ } else {
+ RAX(cpu) = (uint32_t)val;
+ }
- break;
- default:
- VM_PANIC("Bad in opcode\n");
- break;
+ break;
+ default:
+ VM_PANIC("Bad in opcode\n");
+ break;
}
RIP(cpu) += decode->len;
}
-static inline void string_increment_reg(struct CPUState * cpu, int reg, struct x86_decode *decode)
+static inline void string_increment_reg(struct CPUState *cpu, int reg,
+ struct x86_decode *decode)
{
addr_t val = read_reg(cpu, reg, decode->addressing_size);
- if (cpu->hvf_x86->rflags.df)
+ if (cpu->hvf_x86->rflags.df) {
val -= decode->operand_size;
- else
+ } else {
val += decode->operand_size;
+ }
write_reg(cpu, reg, val, decode->addressing_size);
}
-static inline void string_rep(struct CPUState * cpu, struct x86_decode *decode, void (*func)(struct CPUState *cpu, struct x86_decode *ins), int rep)
+static inline void string_rep(struct CPUState *cpu, struct x86_decode *decode,
+ void (*func)(struct CPUState *cpu,
+ struct x86_decode *ins), int rep)
{
addr_t rcx = read_reg(cpu, REG_RCX, decode->addressing_size);
while (rcx--) {
func(cpu, decode);
write_reg(cpu, REG_RCX, rcx, decode->addressing_size);
- if ((PREFIX_REP == rep) && !get_ZF(cpu))
+ if ((PREFIX_REP == rep) && !get_ZF(cpu)) {
break;
- if ((PREFIX_REPN == rep) && get_ZF(cpu))
+ }
+ if ((PREFIX_REPN == rep) && get_ZF(cpu)) {
break;
+ }
}
}
static void exec_ins_single(struct CPUState *cpu, struct x86_decode *decode)
{
- addr_t addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+ addr_t addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size,
+ REG_SEG_ES);
- hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 0, decode->operand_size, 1);
+ hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 0,
+ decode->operand_size, 1);
vmx_write_mem(cpu, addr, cpu->hvf_x86->mmio_buf, decode->operand_size);
string_increment_reg(cpu, REG_RDI, decode);
@@ -512,10 +541,11 @@ static void exec_ins_single(struct CPUState *cpu, struct x86_decode *decode)
static void exec_ins(struct CPUState *cpu, struct x86_decode *decode)
{
- if (decode->rep)
+ if (decode->rep) {
string_rep(cpu, decode, exec_ins_single, 0);
- else
+ } else {
exec_ins_single(cpu, decode);
+ }
RIP(cpu) += decode->len;
}
@@ -525,18 +555,20 @@ static void exec_outs_single(struct CPUState *cpu, struct x86_decode *decode)
addr_t addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, addr, decode->operand_size);
- hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 1, decode->operand_size, 1);
+ hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 1,
+ decode->operand_size, 1);
string_increment_reg(cpu, REG_RSI, decode);
}
static void exec_outs(struct CPUState *cpu, struct x86_decode *decode)
{
- if (decode->rep)
+ if (decode->rep) {
string_rep(cpu, decode, exec_outs_single, 0);
- else
+ } else {
exec_outs_single(cpu, decode);
-
+ }
+
RIP(cpu) += decode->len;
}
@@ -545,10 +577,11 @@ static void exec_movs_single(struct CPUState *cpu, struct x86_decode *decode)
addr_t src_addr;
addr_t dst_addr;
addr_t val;
-
+
src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
- dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
-
+ dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size,
+ REG_SEG_ES);
+
val = read_val_ext(cpu, src_addr, decode->operand_size);
write_val_ext(cpu, dst_addr, val, decode->operand_size);
@@ -560,9 +593,9 @@ static void exec_movs(struct CPUState *cpu, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(cpu, decode, exec_movs_single, 0);
- }
- else
+ } else {
exec_movs_single(cpu, decode);
+ }
RIP(cpu) += decode->len;
}
@@ -573,7 +606,8 @@ static void exec_cmps_single(struct CPUState *cpu, struct x86_decode *decode)
addr_t dst_addr;
src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
- dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+ dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size,
+ REG_SEG_ES);
decode->op[0].type = X86_VAR_IMMEDIATE;
decode->op[0].val = read_val_ext(cpu, src_addr, decode->operand_size);
@@ -590,9 +624,9 @@ static void exec_cmps(struct CPUState *cpu, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(cpu, decode, exec_cmps_single, decode->rep);
- }
- else
+ } else {
exec_cmps_single(cpu, decode);
+ }
RIP(cpu) += decode->len;
}
@@ -614,9 +648,9 @@ static void exec_stos(struct CPUState *cpu, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(cpu, decode, exec_stos_single, 0);
- }
- else
+ } else {
exec_stos_single(cpu, decode);
+ }
RIP(cpu) += decode->len;
}
@@ -624,7 +658,7 @@ static void exec_stos(struct CPUState *cpu, struct x86_decode *decode)
static void exec_scas_single(struct CPUState *cpu, struct x86_decode *decode)
{
addr_t addr;
-
+
addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
decode->op[1].type = X86_VAR_IMMEDIATE;
vmx_read_mem(cpu, &decode->op[1].val, addr, decode->operand_size);
@@ -639,9 +673,9 @@ static void exec_scas(struct CPUState *cpu, struct x86_decode *decode)
decode->op[0].reg = REG_RAX;
if (decode->rep) {
string_rep(cpu, decode, exec_scas_single, decode->rep);
- }
- else
+ } else {
exec_scas_single(cpu, decode);
+ }
RIP(cpu) += decode->len;
}
@@ -650,7 +684,7 @@ static void exec_lods_single(struct CPUState *cpu, struct x86_decode *decode)
{
addr_t addr;
addr_t val = 0;
-
+
addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
vmx_read_mem(cpu, &val, addr, decode->operand_size);
write_reg(cpu, REG_RAX, val, decode->operand_size);
@@ -662,14 +696,14 @@ static void exec_lods(struct CPUState *cpu, struct x86_decode *decode)
{
if (decode->rep) {
string_rep(cpu, decode, exec_lods_single, 0);
- }
- else
+ } else {
exec_lods_single(cpu, decode);
+ }
RIP(cpu) += decode->len;
}
-#define MSR_IA32_UCODE_REV 0x00000017
+#define MSR_IA32_UCODE_REV 0x00000017
void simulate_rdmsr(struct CPUState *cpu)
{
@@ -679,83 +713,83 @@ void simulate_rdmsr(struct CPUState *cpu)
uint64_t val = 0;
switch (msr) {
- case MSR_IA32_TSC:
- val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET);
- break;
- case MSR_IA32_APICBASE:
- val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
- break;
- case MSR_IA32_UCODE_REV:
- val = (0x100000000ULL << 32) | 0x100000000ULL;
- break;
- case MSR_EFER:
- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
- break;
- case MSR_FSBASE:
- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE);
- break;
- case MSR_GSBASE:
- val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE);
- break;
- case MSR_KERNELGSBASE:
- val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE);
- break;
- case MSR_STAR:
- abort();
- break;
- case MSR_LSTAR:
- abort();
- break;
- case MSR_CSTAR:
- abort();
- break;
- case MSR_IA32_MISC_ENABLE:
- val = env->msr_ia32_misc_enable;
- break;
- case MSR_MTRRphysBase(0):
- case MSR_MTRRphysBase(1):
- case MSR_MTRRphysBase(2):
- case MSR_MTRRphysBase(3):
- case MSR_MTRRphysBase(4):
- case MSR_MTRRphysBase(5):
- case MSR_MTRRphysBase(6):
- case MSR_MTRRphysBase(7):
- val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base;
- break;
- case MSR_MTRRphysMask(0):
- case MSR_MTRRphysMask(1):
- case MSR_MTRRphysMask(2):
- case MSR_MTRRphysMask(3):
- case MSR_MTRRphysMask(4):
- case MSR_MTRRphysMask(5):
- case MSR_MTRRphysMask(6):
- case MSR_MTRRphysMask(7):
- val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask;
- break;
- case MSR_MTRRfix64K_00000:
- val = env->mtrr_fixed[0];
- break;
- case MSR_MTRRfix16K_80000:
- case MSR_MTRRfix16K_A0000:
- val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1];
- break;
- case MSR_MTRRfix4K_C0000:
- case MSR_MTRRfix4K_C8000:
- case MSR_MTRRfix4K_D0000:
- case MSR_MTRRfix4K_D8000:
- case MSR_MTRRfix4K_E0000:
- case MSR_MTRRfix4K_E8000:
- case MSR_MTRRfix4K_F0000:
- case MSR_MTRRfix4K_F8000:
- val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3];
- break;
- case MSR_MTRRdefType:
- val = env->mtrr_deftype;
- break;
- default:
- // fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr);
- val = 0;
- break;
+ case MSR_IA32_TSC:
+ val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET);
+ break;
+ case MSR_IA32_APICBASE:
+ val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
+ break;
+ case MSR_IA32_UCODE_REV:
+ val = (0x100000000ULL << 32) | 0x100000000ULL;
+ break;
+ case MSR_EFER:
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
+ break;
+ case MSR_FSBASE:
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE);
+ break;
+ case MSR_GSBASE:
+ val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE);
+ break;
+ case MSR_KERNELGSBASE:
+ val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE);
+ break;
+ case MSR_STAR:
+ abort();
+ break;
+ case MSR_LSTAR:
+ abort();
+ break;
+ case MSR_CSTAR:
+ abort();
+ break;
+ case MSR_IA32_MISC_ENABLE:
+ val = env->msr_ia32_misc_enable;
+ break;
+ case MSR_MTRRphysBase(0):
+ case MSR_MTRRphysBase(1):
+ case MSR_MTRRphysBase(2):
+ case MSR_MTRRphysBase(3):
+ case MSR_MTRRphysBase(4):
+ case MSR_MTRRphysBase(5):
+ case MSR_MTRRphysBase(6):
+ case MSR_MTRRphysBase(7):
+ val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base;
+ break;
+ case MSR_MTRRphysMask(0):
+ case MSR_MTRRphysMask(1):
+ case MSR_MTRRphysMask(2):
+ case MSR_MTRRphysMask(3):
+ case MSR_MTRRphysMask(4):
+ case MSR_MTRRphysMask(5):
+ case MSR_MTRRphysMask(6):
+ case MSR_MTRRphysMask(7):
+ val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask;
+ break;
+ case MSR_MTRRfix64K_00000:
+ val = env->mtrr_fixed[0];
+ break;
+ case MSR_MTRRfix16K_80000:
+ case MSR_MTRRfix16K_A0000:
+ val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1];
+ break;
+ case MSR_MTRRfix4K_C0000:
+ case MSR_MTRRfix4K_C8000:
+ case MSR_MTRRfix4K_D0000:
+ case MSR_MTRRfix4K_D8000:
+ case MSR_MTRRfix4K_E0000:
+ case MSR_MTRRfix4K_E8000:
+ case MSR_MTRRfix4K_F0000:
+ case MSR_MTRRfix4K_F8000:
+ val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3];
+ break;
+ case MSR_MTRRdefType:
+ val = env->mtrr_deftype;
+ break;
+ default:
+ /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */
+ val = 0;
+ break;
}
RAX(cpu) = (uint32_t)val;
@@ -776,88 +810,89 @@ void simulate_wrmsr(struct CPUState *cpu)
uint64_t data = ((uint64_t)EDX(cpu) << 32) | EAX(cpu);
switch (msr) {
- case MSR_IA32_TSC:
- // if (!osx_is_sierra())
- // wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp());
- //hv_vm_sync_tsc(data);
- break;
- case MSR_IA32_APICBASE:
- cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
- break;
- case MSR_FSBASE:
- wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data);
- break;
- case MSR_GSBASE:
- wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data);
- break;
- case MSR_KERNELGSBASE:
- wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data);
- break;
- case MSR_STAR:
- abort();
- break;
- case MSR_LSTAR:
- abort();
- break;
- case MSR_CSTAR:
- abort();
- break;
- case MSR_EFER:
- cpu->hvf_x86->efer.efer = data;
- //printf("new efer %llx\n", EFER(cpu));
- wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);
- if (data & EFER_NXE)
- hv_vcpu_invalidate_tlb(cpu->hvf_fd);
- break;
- case MSR_MTRRphysBase(0):
- case MSR_MTRRphysBase(1):
- case MSR_MTRRphysBase(2):
- case MSR_MTRRphysBase(3):
- case MSR_MTRRphysBase(4):
- case MSR_MTRRphysBase(5):
- case MSR_MTRRphysBase(6):
- case MSR_MTRRphysBase(7):
- env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base = data;
- break;
- case MSR_MTRRphysMask(0):
- case MSR_MTRRphysMask(1):
- case MSR_MTRRphysMask(2):
- case MSR_MTRRphysMask(3):
- case MSR_MTRRphysMask(4):
- case MSR_MTRRphysMask(5):
- case MSR_MTRRphysMask(6):
- case MSR_MTRRphysMask(7):
- env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask = data;
- break;
- case MSR_MTRRfix64K_00000:
- env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix64K_00000] = data;
- break;
- case MSR_MTRRfix16K_80000:
- case MSR_MTRRfix16K_A0000:
- env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1] = data;
- break;
- case MSR_MTRRfix4K_C0000:
- case MSR_MTRRfix4K_C8000:
- case MSR_MTRRfix4K_D0000:
- case MSR_MTRRfix4K_D8000:
- case MSR_MTRRfix4K_E0000:
- case MSR_MTRRfix4K_E8000:
- case MSR_MTRRfix4K_F0000:
- case MSR_MTRRfix4K_F8000:
- env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3] = data;
- break;
- case MSR_MTRRdefType:
- env->mtrr_deftype = data;
- break;
- default:
- break;
+ case MSR_IA32_TSC:
+ /* if (!osx_is_sierra())
+ wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp());
+ hv_vm_sync_tsc(data);*/
+ break;
+ case MSR_IA32_APICBASE:
+ cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
+ break;
+ case MSR_FSBASE:
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data);
+ break;
+ case MSR_GSBASE:
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data);
+ break;
+ case MSR_KERNELGSBASE:
+ wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data);
+ break;
+ case MSR_STAR:
+ abort();
+ break;
+ case MSR_LSTAR:
+ abort();
+ break;
+ case MSR_CSTAR:
+ abort();
+ break;
+ case MSR_EFER:
+ cpu->hvf_x86->efer.efer = data;
+ /*printf("new efer %llx\n", EFER(cpu));*/
+ wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);
+ if (data & EFER_NXE) {
+ hv_vcpu_invalidate_tlb(cpu->hvf_fd);
+ }
+ break;
+ case MSR_MTRRphysBase(0):
+ case MSR_MTRRphysBase(1):
+ case MSR_MTRRphysBase(2):
+ case MSR_MTRRphysBase(3):
+ case MSR_MTRRphysBase(4):
+ case MSR_MTRRphysBase(5):
+ case MSR_MTRRphysBase(6):
+ case MSR_MTRRphysBase(7):
+ env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base = data;
+ break;
+ case MSR_MTRRphysMask(0):
+ case MSR_MTRRphysMask(1):
+ case MSR_MTRRphysMask(2):
+ case MSR_MTRRphysMask(3):
+ case MSR_MTRRphysMask(4):
+ case MSR_MTRRphysMask(5):
+ case MSR_MTRRphysMask(6):
+ case MSR_MTRRphysMask(7):
+ env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask = data;
+ break;
+ case MSR_MTRRfix64K_00000:
+ env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix64K_00000] = data;
+ break;
+ case MSR_MTRRfix16K_80000:
+ case MSR_MTRRfix16K_A0000:
+ env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1] = data;
+ break;
+ case MSR_MTRRfix4K_C0000:
+ case MSR_MTRRfix4K_C8000:
+ case MSR_MTRRfix4K_D0000:
+ case MSR_MTRRfix4K_D8000:
+ case MSR_MTRRfix4K_E0000:
+ case MSR_MTRRfix4K_E8000:
+ case MSR_MTRRfix4K_F0000:
+ case MSR_MTRRfix4K_F8000:
+ env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3] = data;
+ break;
+ case MSR_MTRRdefType:
+ env->mtrr_deftype = data;
+ break;
+ default:
+ break;
}
/* Related to support known hypervisor interface */
- // if (g_hypervisor_iface)
- // g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
+ /* if (g_hypervisor_iface)
+ g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
- //printf("write msr %llx\n", RCX(cpu));
+ printf("write msr %llx\n", RCX(cpu));*/
}
static void exec_wrmsr(struct CPUState *cpu, struct x86_decode *decode)
@@ -893,24 +928,26 @@ static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
VM_PANIC("bt 64bit\n");
}
}
- decode->op[0].val = read_val_ext(cpu, decode->op[0].ptr, decode->operand_size);
+ decode->op[0].val = read_val_ext(cpu, decode->op[0].ptr,
+ decode->operand_size);
cf = (decode->op[0].val >> index) & 0x01;
switch (flag) {
- case 0:
- set_CF(cpu, cf);
- return;
- case 1:
- decode->op[0].val ^= (1u << index);
- break;
- case 2:
- decode->op[0].val |= (1u << index);
- break;
- case 3:
- decode->op[0].val &= ~(1u << index);
- break;
+ case 0:
+ set_CF(cpu, cf);
+ return;
+ case 1:
+ decode->op[0].val ^= (1u << index);
+ break;
+ case 2:
+ decode->op[0].val |= (1u << index);
+ break;
+ case 3:
+ decode->op[0].val &= ~(1u << index);
+ break;
}
- write_val_ext(cpu, decode->op[0].ptr, decode->op[0].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[0].val,
+ decode->operand_size);
set_CF(cpu, cf);
}
@@ -946,58 +983,59 @@ void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
fetch_operands(cpu, decode, 2, true, true, false);
count = decode->op[1].val;
- count &= 0x1f; // count is masked to 5 bits
- if (!count)
+ count &= 0x1f; /* count is masked to 5 bits*/
+ if (!count) {
goto exit;
+ }
switch (decode->operand_size) {
- case 1:
- {
- uint8_t res = 0;
- if (count <= 8) {
- res = (decode->op[0].val << count);
- cf = (decode->op[0].val >> (8 - count)) & 0x1;
- of = cf ^ (res >> 7);
- }
-
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
- SET_FLAGS_OSZAPC_LOGIC_8(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
- break;
+ case 1:
+ {
+ uint8_t res = 0;
+ if (count <= 8) {
+ res = (decode->op[0].val << count);
+ cf = (decode->op[0].val >> (8 - count)) & 0x1;
+ of = cf ^ (res >> 7);
}
- case 2:
- {
- uint16_t res = 0;
-
- /* from bochs */
- if (count <= 16) {
- res = (decode->op[0].val << count);
- cf = (decode->op[0].val >> (16 - count)) & 0x1;
- of = cf ^ (res >> 15); // of = cf ^ result15
- }
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
- SET_FLAGS_OSZAPC_LOGIC_16(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
- break;
- }
- case 4:
- {
- uint32_t res = decode->op[0].val << count;
-
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
- SET_FLAGS_OSZAPC_LOGIC_32(res);
- cf = (decode->op[0].val >> (32 - count)) & 0x1;
- of = cf ^ (res >> 31); // of = cf ^ result31
- SET_FLAGS_OxxxxC(cpu, of, cf);
- break;
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ SET_FLAGS_OSZAPC_LOGIC_8(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 2:
+ {
+ uint16_t res = 0;
+
+ /* from bochs */
+ if (count <= 16) {
+ res = (decode->op[0].val << count);
+ cf = (decode->op[0].val >> (16 - count)) & 0x1;
+ of = cf ^ (res >> 15); /* of = cf ^ result15 */
}
- default:
- abort();
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ SET_FLAGS_OSZAPC_LOGIC_16(res);
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 4:
+ {
+ uint32_t res = decode->op[0].val << count;
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ SET_FLAGS_OSZAPC_LOGIC_32(res);
+ cf = (decode->op[0].val >> (32 - count)) & 0x1;
+ of = cf ^ (res >> 31); /* of = cf ^ result31 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ default:
+ abort();
}
exit:
- //lflags_to_rflags(cpu);
+ /* lflags_to_rflags(cpu); */
RIP(cpu) += decode->len;
}
@@ -1008,14 +1046,16 @@ void exec_movsx(struct CPUState *cpu, struct x86_decode *decode)
fetch_operands(cpu, decode, 2, false, false, false);
- if (0xbe == decode->opcode[1])
+ if (0xbe == decode->opcode[1]) {
src_op_size = 1;
- else
+ } else {
src_op_size = 2;
+ }
decode->operand_size = src_op_size;
calc_modrm_operand(cpu, decode, &decode->op[1]);
- decode->op[1].val = sign(read_val_ext(cpu, decode->op[1].ptr, src_op_size), src_op_size);
+ decode->op[1].val = sign(read_val_ext(cpu, decode->op[1].ptr, src_op_size),
+ src_op_size);
write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
@@ -1030,68 +1070,71 @@ void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
count = decode->op[1].val;
switch (decode->operand_size) {
- case 1:
- {
- uint32_t bit6, bit7;
- uint8_t res;
-
- if ((count & 0x07) == 0) {
- if (count & 0x18) {
- bit6 = ((uint8_t)decode->op[0].val >> 6) & 1;
- bit7 = ((uint8_t)decode->op[0].val >> 7) & 1;
- SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
- }
- } else {
- count &= 0x7; /* use only bottom 3 bits */
- res = ((uint8_t)decode->op[0].val >> count) | ((uint8_t)decode->op[0].val << (8 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
- bit6 = (res >> 6) & 1;
- bit7 = (res >> 7) & 1;
- /* set eflags: ROR count affects the following flags: C, O */
+ case 1:
+ {
+ uint32_t bit6, bit7;
+ uint8_t res;
+
+ if ((count & 0x07) == 0) {
+ if (count & 0x18) {
+ bit6 = ((uint8_t)decode->op[0].val >> 6) & 1;
+ bit7 = ((uint8_t)decode->op[0].val >> 7) & 1;
SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
- }
- break;
+ }
+ } else {
+ count &= 0x7; /* use only bottom 3 bits */
+ res = ((uint8_t)decode->op[0].val >> count) |
+ ((uint8_t)decode->op[0].val << (8 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ bit6 = (res >> 6) & 1;
+ bit7 = (res >> 7) & 1;
+ /* set eflags: ROR count affects the following flags: C, O */
+ SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
}
- case 2:
- {
- uint32_t bit14, bit15;
- uint16_t res;
-
- if ((count & 0x0f) == 0) {
- if (count & 0x10) {
- bit14 = ((uint16_t)decode->op[0].val >> 14) & 1;
- bit15 = ((uint16_t)decode->op[0].val >> 15) & 1;
- // of = result14 ^ result15
- SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
- }
- } else {
- count &= 0x0f; // use only 4 LSB's
- res = ((uint16_t)decode->op[0].val >> count) | ((uint16_t)decode->op[0].val << (16 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
-
- bit14 = (res >> 14) & 1;
- bit15 = (res >> 15) & 1;
- // of = result14 ^ result15
+ break;
+ }
+ case 2:
+ {
+ uint32_t bit14, bit15;
+ uint16_t res;
+
+ if ((count & 0x0f) == 0) {
+ if (count & 0x10) {
+ bit14 = ((uint16_t)decode->op[0].val >> 14) & 1;
+ bit15 = ((uint16_t)decode->op[0].val >> 15) & 1;
+ /* of = result14 ^ result15 */
SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
}
- break;
+ } else {
+ count &= 0x0f; /* use only 4 LSB's */
+ res = ((uint16_t)decode->op[0].val >> count) |
+ ((uint16_t)decode->op[0].val << (16 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+
+ bit14 = (res >> 14) & 1;
+ bit15 = (res >> 15) & 1;
+ /* of = result14 ^ result15 */
+ SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
}
- case 4:
- {
- uint32_t bit31, bit30;
- uint32_t res;
-
- count &= 0x1f;
- if (count) {
- res = ((uint32_t)decode->op[0].val >> count) | ((uint32_t)decode->op[0].val << (32 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
-
- bit31 = (res >> 31) & 1;
- bit30 = (res >> 30) & 1;
- // of = result30 ^ result31
- SET_FLAGS_OxxxxC(cpu, bit30 ^ bit31, bit31);
- }
- break;
+ break;
+ }
+ case 4:
+ {
+ uint32_t bit31, bit30;
+ uint32_t res;
+
+ count &= 0x1f;
+ if (count) {
+ res = ((uint32_t)decode->op[0].val >> count) |
+ ((uint32_t)decode->op[0].val << (32 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+
+ bit31 = (res >> 31) & 1;
+ bit30 = (res >> 30) & 1;
+ /* of = result30 ^ result31 */
+ SET_FLAGS_OxxxxC(cpu, bit30 ^ bit31, bit31);
+ }
+ break;
}
}
RIP(cpu) += decode->len;
@@ -1105,71 +1148,74 @@ void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
count = decode->op[1].val;
switch (decode->operand_size) {
- case 1:
- {
- uint32_t bit0, bit7;
- uint8_t res;
-
- if ((count & 0x07) == 0) {
- if (count & 0x18) {
- bit0 = ((uint8_t)decode->op[0].val & 1);
- bit7 = ((uint8_t)decode->op[0].val >> 7);
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
- }
- } else {
- count &= 0x7; // use only lowest 3 bits
- res = ((uint8_t)decode->op[0].val << count) | ((uint8_t)decode->op[0].val >> (8 - count));
-
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
- /* set eflags:
- * ROL count affects the following flags: C, O
- */
- bit0 = (res & 1);
- bit7 = (res >> 7);
+ case 1:
+ {
+ uint32_t bit0, bit7;
+ uint8_t res;
+
+ if ((count & 0x07) == 0) {
+ if (count & 0x18) {
+ bit0 = ((uint8_t)decode->op[0].val & 1);
+ bit7 = ((uint8_t)decode->op[0].val >> 7);
SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
}
- break;
+ } else {
+ count &= 0x7; /* use only lowest 3 bits */
+ res = ((uint8_t)decode->op[0].val << count) |
+ ((uint8_t)decode->op[0].val >> (8 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ /* set eflags:
+ * ROL count affects the following flags: C, O
+ */
+ bit0 = (res & 1);
+ bit7 = (res >> 7);
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
}
- case 2:
- {
- uint32_t bit0, bit15;
- uint16_t res;
-
- if ((count & 0x0f) == 0) {
- if (count & 0x10) {
- bit0 = ((uint16_t)decode->op[0].val & 0x1);
- bit15 = ((uint16_t)decode->op[0].val >> 15);
- // of = cf ^ result15
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
- }
- } else {
- count &= 0x0f; // only use bottom 4 bits
- res = ((uint16_t)decode->op[0].val << count) | ((uint16_t)decode->op[0].val >> (16 - count));
-
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
- bit0 = (res & 0x1);
- bit15 = (res >> 15);
- // of = cf ^ result15
+ break;
+ }
+ case 2:
+ {
+ uint32_t bit0, bit15;
+ uint16_t res;
+
+ if ((count & 0x0f) == 0) {
+ if (count & 0x10) {
+ bit0 = ((uint16_t)decode->op[0].val & 0x1);
+ bit15 = ((uint16_t)decode->op[0].val >> 15);
+ /* of = cf ^ result15 */
SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
}
- break;
+ } else {
+ count &= 0x0f; /* only use bottom 4 bits */
+ res = ((uint16_t)decode->op[0].val << count) |
+ ((uint16_t)decode->op[0].val >> (16 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ bit0 = (res & 0x1);
+ bit15 = (res >> 15);
+ /* of = cf ^ result15 */
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
}
- case 4:
- {
- uint32_t bit0, bit31;
- uint32_t res;
-
- count &= 0x1f;
- if (count) {
- res = ((uint32_t)decode->op[0].val << count) | ((uint32_t)decode->op[0].val >> (32 - count));
-
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
- bit0 = (res & 0x1);
- bit31 = (res >> 31);
- // of = cf ^ result31
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit31, bit0);
- }
- break;
+ break;
+ }
+ case 4:
+ {
+ uint32_t bit0, bit31;
+ uint32_t res;
+
+ count &= 0x1f;
+ if (count) {
+ res = ((uint32_t)decode->op[0].val << count) |
+ ((uint32_t)decode->op[0].val >> (32 - count));
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ bit0 = (res & 0x1);
+ bit31 = (res >> 31);
+ /* of = cf ^ result31 */
+ SET_FLAGS_OxxxxC(cpu, bit0 ^ bit31, bit0);
+ }
+ break;
}
}
RIP(cpu) += decode->len;
@@ -1184,70 +1230,79 @@ void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
fetch_operands(cpu, decode, 2, true, true, false);
count = decode->op[1].val & 0x1f;
- switch(decode->operand_size) {
- case 1:
- {
- uint8_t op1_8 = decode->op[0].val;
- uint8_t res;
- count %= 9;
- if (!count)
- break;
+ switch (decode->operand_size) {
+ case 1:
+ {
+ uint8_t op1_8 = decode->op[0].val;
+ uint8_t res;
+ count %= 9;
+ if (!count) {
+ break;
+ }
+
+ if (1 == count) {
+ res = (op1_8 << 1) | get_CF(cpu);
+ } else {
+ res = (op1_8 << count) | (get_CF(cpu) << (count - 1)) |
+ (op1_8 >> (9 - count));
+ }
- if (1 == count)
- res = (op1_8 << 1) | get_CF(cpu);
- else
- res = (op1_8 << count) | (get_CF(cpu) << (count - 1)) | (op1_8 >> (9 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ cf = (op1_8 >> (8 - count)) & 0x01;
+ of = cf ^ (res >> 7); /* of = cf ^ result7 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 2:
+ {
+ uint16_t res;
+ uint16_t op1_16 = decode->op[0].val;
- cf = (op1_8 >> (8 - count)) & 0x01;
- of = cf ^ (res >> 7); // of = cf ^ result7
- SET_FLAGS_OxxxxC(cpu, of, cf);
- break;
- }
- case 2:
- {
- uint16_t res;
- uint16_t op1_16 = decode->op[0].val;
-
- count %= 17;
- if (!count)
- break;
-
- if (1 == count)
- res = (op1_16 << 1) | get_CF(cpu);
- else if (count == 16)
- res = (get_CF(cpu) << 15) | (op1_16 >> 1);
- else // 2..15
- res = (op1_16 << count) | (get_CF(cpu) << (count - 1)) | (op1_16 >> (17 - count));
-
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
-
- cf = (op1_16 >> (16 - count)) & 0x1;
- of = cf ^ (res >> 15); // of = cf ^ result15
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ count %= 17;
+ if (!count) {
break;
}
- case 4:
- {
- uint32_t res;
- uint32_t op1_32 = decode->op[0].val;
- if (!count)
- break;
+ if (1 == count) {
+ res = (op1_16 << 1) | get_CF(cpu);
+ } else if (count == 16) {
+ res = (get_CF(cpu) << 15) | (op1_16 >> 1);
+ } else { /* 2..15 */
+ res = (op1_16 << count) | (get_CF(cpu) << (count - 1)) |
+ (op1_16 >> (17 - count));
+ }
- if (1 == count)
- res = (op1_32 << 1) | get_CF(cpu);
- else
- res = (op1_32 << count) | (get_CF(cpu) << (count - 1)) | (op1_32 >> (33 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ cf = (op1_16 >> (16 - count)) & 0x1;
+ of = cf ^ (res >> 15); /* of = cf ^ result15 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 4:
+ {
+ uint32_t res;
+ uint32_t op1_32 = decode->op[0].val;
- cf = (op1_32 >> (32 - count)) & 0x1;
- of = cf ^ (res >> 31); // of = cf ^ result31
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ if (!count) {
break;
}
+
+ if (1 == count) {
+ res = (op1_32 << 1) | get_CF(cpu);
+ } else {
+ res = (op1_32 << count) | (get_CF(cpu) << (count - 1)) |
+ (op1_32 >> (33 - count));
+ }
+
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+
+ cf = (op1_32 >> (32 - count)) & 0x1;
+ of = cf ^ (res >> 31); /* of = cf ^ result31 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
}
RIP(cpu) += decode->len;
}
@@ -1260,60 +1315,68 @@ void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
fetch_operands(cpu, decode, 2, true, true, false);
count = decode->op[1].val & 0x1f;
- switch(decode->operand_size) {
- case 1:
- {
- uint8_t op1_8 = decode->op[0].val;
- uint8_t res;
+ switch (decode->operand_size) {
+ case 1:
+ {
+ uint8_t op1_8 = decode->op[0].val;
+ uint8_t res;
- count %= 9;
- if (!count)
- break;
- res = (op1_8 >> count) | (get_CF(cpu) << (8 - count)) | (op1_8 << (9 - count));
+ count %= 9;
+ if (!count) {
+ break;
+ }
+ res = (op1_8 >> count) | (get_CF(cpu) << (8 - count)) |
+ (op1_8 << (9 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ write_val_ext(cpu, decode->op[0].ptr, res, 1);
+
+ cf = (op1_8 >> (count - 1)) & 0x1;
+ of = (((res << 1) ^ res) >> 7) & 0x1; /* of = result6 ^ result7 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 2:
+ {
+ uint16_t op1_16 = decode->op[0].val;
+ uint16_t res;
- cf = (op1_8 >> (count - 1)) & 0x1;
- of = (((res << 1) ^ res) >> 7) & 0x1; // of = result6 ^ result7
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ count %= 17;
+ if (!count) {
break;
}
- case 2:
- {
- uint16_t op1_16 = decode->op[0].val;
- uint16_t res;
+ res = (op1_16 >> count) | (get_CF(cpu) << (16 - count)) |
+ (op1_16 << (17 - count));
- count %= 17;
- if (!count)
- break;
- res = (op1_16 >> count) | (get_CF(cpu) << (16 - count)) | (op1_16 << (17 - count));
+ write_val_ext(cpu, decode->op[0].ptr, res, 2);
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ cf = (op1_16 >> (count - 1)) & 0x1;
+ of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; /* of = result15 ^
+ result14 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
+ }
+ case 4:
+ {
+ uint32_t res;
+ uint32_t op1_32 = decode->op[0].val;
- cf = (op1_16 >> (count - 1)) & 0x1;
- of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; // of = result15 ^ result14
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ if (!count) {
break;
}
- case 4:
- {
- uint32_t res;
- uint32_t op1_32 = decode->op[0].val;
-
- if (!count)
- break;
-
- if (1 == count)
- res = (op1_32 >> 1) | (get_CF(cpu) << 31);
- else
- res = (op1_32 >> count) | (get_CF(cpu) << (32 - count)) | (op1_32 << (33 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ if (1 == count) {
+ res = (op1_32 >> 1) | (get_CF(cpu) << 31);
+ } else {
+ res = (op1_32 >> count) | (get_CF(cpu) << (32 - count)) |
+ (op1_32 << (33 - count));
+ }
- cf = (op1_32 >> (count - 1)) & 0x1;
- of = ((res << 1) ^ res) >> 31; // of = result30 ^ result31
- SET_FLAGS_OxxxxC(cpu, of, cf);
- break;
+ write_val_ext(cpu, decode->op[0].ptr, res, 4);
+
+ cf = (op1_32 >> (count - 1)) & 0x1;
+ of = ((res << 1) ^ res) >> 31; /* of = result30 ^ result31 */
+ SET_FLAGS_OxxxxC(cpu, of, cf);
+ break;
}
}
RIP(cpu) += decode->len;
@@ -1323,8 +1386,10 @@ static void exec_xchg(struct CPUState *cpu, struct x86_decode *decode)
{
fetch_operands(cpu, decode, 2, true, true, false);
- write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
- write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val,
+ decode->operand_size);
+ write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val,
+ decode->operand_size);
RIP(cpu) += decode->len;
}
@@ -1332,7 +1397,8 @@ static void exec_xchg(struct CPUState *cpu, struct x86_decode *decode)
static void exec_xadd(struct CPUState *cpu, struct x86_decode *decode)
{
EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
- write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
+ write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val,
+ decode->operand_size);
RIP(cpu) += decode->len;
}
@@ -1388,13 +1454,9 @@ static struct cmd_handler _cmd_handler[X86_DECODE_CMD_LAST];
static void init_cmd_handler(CPUState *cpu)
{
int i;
- for (i = 0; i < ARRAY_SIZE(handlers); i++)
+ for (i = 0; i < ARRAY_SIZE(handlers); i++) {
_cmd_handler[handlers[i].cmd] = handlers[i];
-}
-
-static void print_debug(struct CPUState *cpu)
-{
- printf("%llx: eax %llx ebx %llx ecx %llx edx %llx esi %llx edi %llx ebp %llx esp %llx flags %llx\n", RIP(cpu), RAX(cpu), RBX(cpu), RCX(cpu), RDX(cpu), RSI(cpu), RDI(cpu), RBP(cpu), RSP(cpu), EFLAGS(cpu));
+ }
}
void load_regs(struct CPUState *cpu)
@@ -1408,14 +1470,13 @@ void load_regs(struct CPUState *cpu)
RRX(cpu, REG_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI);
RRX(cpu, REG_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP);
RRX(cpu, REG_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP);
- for (i = 8; i < 16; i++)
+ for (i = 8; i < 16; i++) {
RRX(cpu, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
-
+ }
+
RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
rflags_to_lflags(cpu);
RIP(cpu) = rreg(cpu->hvf_fd, HV_X86_RIP);
-
- //print_debug(cpu);
}
void store_regs(struct CPUState *cpu)
@@ -1429,32 +1490,36 @@ void store_regs(struct CPUState *cpu)
wreg(cpu->hvf_fd, HV_X86_RDI, RDI(cpu));
wreg(cpu->hvf_fd, HV_X86_RBP, RBP(cpu));
wreg(cpu->hvf_fd, HV_X86_RSP, RSP(cpu));
- for (i = 8; i < 16; i++)
+ for (i = 8; i < 16; i++) {
wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(cpu, i));
-
+ }
+
lflags_to_rflags(cpu);
wreg(cpu->hvf_fd, HV_X86_RFLAGS, RFLAGS(cpu));
macvm_set_rip(cpu, RIP(cpu));
-
- //print_debug(cpu);
}
bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins)
{
- //if (hvf_vcpu_id(cpu))
- //printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu), decode_cmd_to_string(ins->cmd));
-
+ /*if (hvf_vcpu_id(cpu))
+ printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu),
+ decode_cmd_to_string(ins->cmd));*/
+
if (0 && ins->is_fpu) {
VM_PANIC("emulate fpu\n");
} else {
if (!_cmd_handler[ins->cmd].handler) {
- printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0],
- ins->opcode_len > 1 ? ins->opcode[1] : 0);
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu),
+ ins->cmd, ins->opcode[0],
+ ins->opcode_len > 1 ? ins->opcode[1] : 0);
RIP(cpu) += ins->len;
return true;
}
-
- VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler, "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0);
+
+ VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler,
+ "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu),
+ ins->cmd, ins->opcode[0],
+ ins->opcode_len > 1 ? ins->opcode[1] : 0);
_cmd_handler[ins->cmd].handler(cpu, ins);
}
return true;
diff --git a/target/i386/hvf-utils/x86_emu.h b/target/i386/hvf-utils/x86_emu.h
index c56b2798fa..f7a739bb0a 100644
--- a/target/i386/hvf-utils/x86_emu.h
+++ b/target/i386/hvf-utils/x86_emu.h
@@ -13,4 +13,19 @@ void store_regs(struct CPUState *cpu);
void simulate_rdmsr(struct CPUState *cpu);
void simulate_wrmsr(struct CPUState *cpu);
+addr_t read_reg(struct CPUState *cpu, int reg, int size);
+void write_reg(struct CPUState *cpu, int reg, addr_t val, int size);
+addr_t read_val_from_reg(addr_t reg_ptr, int size);
+void write_val_to_reg(addr_t reg_ptr, addr_t val, int size);
+void write_val_ext(struct CPUState *cpu, addr_t ptr, addr_t val, int size);
+uint8_t *read_mmio(struct CPUState *cpu, addr_t ptr, int bytes);
+addr_t read_val_ext(struct CPUState *cpu, addr_t ptr, int size);
+
+void exec_movzx(struct CPUState *cpu, struct x86_decode *decode);
+void exec_shl(struct CPUState *cpu, struct x86_decode *decode);
+void exec_movsx(struct CPUState *cpu, struct x86_decode *decode);
+void exec_ror(struct CPUState *cpu, struct x86_decode *decode);
+void exec_rol(struct CPUState *cpu, struct x86_decode *decode);
+void exec_rcl(struct CPUState *cpu, struct x86_decode *decode);
+void exec_rcr(struct CPUState *cpu, struct x86_decode *decode);
#endif
diff --git a/target/i386/hvf-utils/x86_flags.c b/target/i386/hvf-utils/x86_flags.c
index ca876d03dd..187ab9b56b 100644
--- a/target/i386/hvf-utils/x86_flags.c
+++ b/target/i386/hvf-utils/x86_flags.c
@@ -32,65 +32,78 @@ void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf)
{
uint32_t temp_po = new_of ^ new_cf;
cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PO | LF_MASK_CF);
- cpu->hvf_x86->lflags.auxbits |= (temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF);
+ cpu->hvf_x86->lflags.auxbits |= (temp_po << LF_BIT_PO) |
+ (new_cf << LF_BIT_CF);
}
-void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff)
{
SET_FLAGS_OSZAPC_SUB_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff)
{
SET_FLAGS_OSZAPC_SUB_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff)
{
SET_FLAGS_OSZAPC_SUB_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff)
{
SET_FLAGS_OSZAPC_ADD_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff)
{
SET_FLAGS_OSZAPC_ADD_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff)
{
SET_FLAGS_OSZAPC_ADD_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff)
{
SET_FLAGS_OSZAP_SUB_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff)
{
SET_FLAGS_OSZAP_SUB_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff)
{
SET_FLAGS_OSZAP_SUB_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
+void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff)
{
SET_FLAGS_OSZAP_ADD_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
+void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff)
{
SET_FLAGS_OSZAP_ADD_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
+void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff)
{
SET_FLAGS_OSZAP_ADD_8(v1, v2, diff);
}
@@ -264,19 +277,22 @@ bool get_ZF(struct CPUState *cpu)
void set_ZF(struct CPUState *cpu, bool val)
{
if (val) {
- cpu->hvf_x86->lflags.auxbits ^= (((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
- // merge the parity bits into the Parity Delta Byte
+ cpu->hvf_x86->lflags.auxbits ^=
+ (((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
+ /* merge the parity bits into the Parity Delta Byte */
uint32_t temp_pdb = (255 & cpu->hvf_x86->lflags.result);
cpu->hvf_x86->lflags.auxbits ^= (temp_pdb << LF_BIT_PDB);
- // now zero the .result value
+ /* now zero the .result value */
cpu->hvf_x86->lflags.result = 0;
- } else
+ } else {
cpu->hvf_x86->lflags.result |= (1 << 8);
+ }
}
bool get_SF(struct CPUState *cpu)
{
- return ((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) ^ (cpu->hvf_x86->lflags.auxbits >> LF_BIT_SD)) & 1;
+ return ((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) ^
+ (cpu->hvf_x86->lflags.auxbits >> LF_BIT_SD)) & 1;
}
void set_SF(struct CPUState *cpu, bool val)
diff --git a/target/i386/hvf-utils/x86_flags.h b/target/i386/hvf-utils/x86_flags.h
index f963f8ad1b..68a0c10b90 100644
--- a/target/i386/hvf-utils/x86_flags.h
+++ b/target/i386/hvf-utils/x86_flags.h
@@ -55,19 +55,24 @@ typedef struct lazy_flags {
#define GET_ADD_OVERFLOW(op1, op2, result, mask) \
((((op1) ^ (result)) & ((op2) ^ (result))) & (mask))
-// *******************
-// OSZAPC
-// *******************
+/* ******************* */
+/* OSZAPC */
+/* ******************* */
/* size, carries, result */
#define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \
addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
(((lf_carries) >> (size - 2)) << LF_BIT_PO); \
cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
- if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
- else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
- else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
- else VM_PANIC("unimplemented"); \
+ if ((size) == 32) { \
+ temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
+ } else if ((size) == 16) { \
+ temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
+ } else if ((size) == 8) { \
+ temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
+ } else { \
+ VM_PANIC("unimplemented"); \
+ } \
cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)temp; \
}
@@ -87,10 +92,15 @@ typedef struct lazy_flags {
#define SET_FLAGS_OSZAPC_LOGIC_32(result_32) \
SET_FLAGS_OSZAPC_32(0, (result_32))
#define SET_FLAGS_OSZAPC_LOGIC_SIZE(size, result) { \
- if (32 == size) {SET_FLAGS_OSZAPC_LOGIC_32(result);} \
- else if (16 == size) {SET_FLAGS_OSZAPC_LOGIC_16(result);} \
- else if (8 == size) {SET_FLAGS_OSZAPC_LOGIC_8(result);} \
- else VM_PANIC("unimplemented"); \
+ if (32 == size) { \
+ SET_FLAGS_OSZAPC_LOGIC_32(result); \
+ } else if (16 == size) { \
+ SET_FLAGS_OSZAPC_LOGIC_16(result); \
+ } else if (8 == size) { \
+ SET_FLAGS_OSZAPC_LOGIC_8(result); \
+ } else { \
+ VM_PANIC("unimplemented"); \
+ } \
}
/* op1, op2, result */
@@ -109,17 +119,22 @@ typedef struct lazy_flags {
#define SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32) \
SET_FLAGS_OSZAPC_32(SUB_COUT_VEC((op1_32), (op2_32), (diff_32)), (diff_32))
-// *******************
-// OSZAP
-// *******************
+/* ******************* */
+/* OSZAP */
+/* ******************* */
/* size, carries, result */
#define SET_FLAGS_OSZAP_SIZE(size, lf_carries, lf_result) { \
addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
(((lf_carries) >> (size - 2)) << LF_BIT_PO); \
- if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
- else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
- else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
- else VM_PANIC("unimplemented"); \
+ if ((size) == 32) { \
+ temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
+ } else if ((size) == 16) { \
+ temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
+ } else if ((size) == 8) { \
+ temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
+ } else { \
+ VM_PANIC("unimplemented"); \
+ } \
cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
addr_t delta_c = (cpu->hvf_x86->lflags.auxbits ^ temp) & LF_MASK_CF; \
delta_c ^= (delta_c >> 1); \
@@ -150,9 +165,9 @@ typedef struct lazy_flags {
#define SET_FLAGS_OSZAP_SUB_32(op1_32, op2_32, diff_32) \
SET_FLAGS_OSZAP_32(SUB_COUT_VEC((op1_32), (op2_32), (diff_32)), (diff_32))
-// *******************
-// OSZAxC
-// *******************
+/* ******************* */
+/* OSZAxC */
+/* ******************* */
/* size, carries, result */
#define SET_FLAGS_OSZAxC_LOGIC_SIZE(size, lf_result) { \
bool saved_PF = getB_PF(); \
@@ -183,21 +198,33 @@ void set_OSZAPC(struct CPUState *cpu, uint32_t flags32);
void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf);
-void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
-void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
-void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
-
-void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
-void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
-void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
-
-void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
-void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
-void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
-
-void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
-void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
-void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
+void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff);
+void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff);
+void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff);
+
+void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff);
+void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff);
+void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff);
+
+void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff);
+void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff);
+void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff);
+
+void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+ uint32_t diff);
+void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+ uint16_t diff);
+void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+ uint8_t diff);
void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff);
void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff);
@@ -215,4 +242,6 @@ void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
+bool _get_OF(struct CPUState *cpu);
+bool _get_CF(struct CPUState *cpu);
#endif /* __X86_FLAGS_H__ */
diff --git a/target/i386/hvf-utils/x86_mmu.c b/target/i386/hvf-utils/x86_mmu.c
index 00fae735be..4c9958ef4c 100644
--- a/target/i386/hvf-utils/x86_mmu.c
+++ b/target/i386/hvf-utils/x86_mmu.c
@@ -54,10 +54,12 @@ struct gpt_translation {
static int gpt_top_level(struct CPUState *cpu, bool pae)
{
- if (!pae)
+ if (!pae) {
return 2;
- if (x86_is_long_mode(cpu))
+ }
+ if (x86_is_long_mode(cpu)) {
return 4;
+ }
return 3;
}
@@ -74,18 +76,21 @@ static inline int pte_size(bool pae)
}
-static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool pae)
+static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
+ int level, bool pae)
{
int index;
uint64_t pte = 0;
addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
addr_t gpa = pt->pte[level] & page_mask;
- if (level == 3 && !x86_is_long_mode(cpu))
+ if (level == 3 && !x86_is_long_mode(cpu)) {
gpa = pt->pte[level];
+ }
index = gpt_entry(pt->gva, level, pae);
- address_space_rw(&address_space_memory, gpa + index * pte_size(pae), MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0);
+ address_space_rw(&address_space_memory, gpa + index * pte_size(pae),
+ MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0);
pt->pte[level - 1] = pte;
@@ -93,32 +98,38 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int l
}
/* test page table entry */
-static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae)
+static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt,
+ int level, bool *is_large, bool pae)
{
uint64_t pte = pt->pte[level];
-
- if (pt->write_access)
+
+ if (pt->write_access) {
pt->err_code |= MMU_PAGE_WT;
- if (pt->user_access)
+ }
+ if (pt->user_access) {
pt->err_code |= MMU_PAGE_US;
- if (pt->exec_access)
+ }
+ if (pt->exec_access) {
pt->err_code |= MMU_PAGE_NX;
+ }
if (!pte_present(pte)) {
- addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
+ /* addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK; */
return false;
}
-
- if (pae && !x86_is_long_mode(cpu) && 2 == level)
+
+ if (pae && !x86_is_long_mode(cpu) && 2 == level) {
goto exit;
-
+ }
+
if (1 == level && pte_large_page(pte)) {
pt->err_code |= MMU_PAGE_PT;
*is_large = true;
}
- if (!level)
+ if (!level) {
pt->err_code |= MMU_PAGE_PT;
-
+ }
+
addr_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
/* check protection */
if (cr0 & CR0_WP) {
@@ -134,7 +145,7 @@ static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int
if (pae && pt->exec_access && !pte_exec_access(pte)) {
return false;
}
-
+
exit:
/* TODO: check reserved bits */
return true;
@@ -149,22 +160,24 @@ static inline uint64_t large_page_gpa(struct gpt_translation *pt, bool pae)
{
VM_PANIC_ON(!pte_large_page(pt->pte[1]))
/* 2Mb large page */
- if (pae)
+ if (pae) {
return (pt->pte[1] & PAE_PTE_LARGE_PAGE_MASK) | (pt->gva & 0x1fffff);
-
+ }
+
/* 4Mb large page */
return pse_pte_to_page(pt->pte[1]) | (pt->gva & 0x3fffff);
}
-static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code, struct gpt_translation* pt, bool pae)
+static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code,
+ struct gpt_translation *pt, bool pae)
{
int top_level, level;
bool is_large = false;
addr_t cr3 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3);
addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
-
+
memset(pt, 0, sizeof(*pt));
top_level = gpt_top_level(cpu, pae);
@@ -173,7 +186,7 @@ static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code, struct gpt
pt->user_access = (err_code & MMU_PAGE_US);
pt->write_access = (err_code & MMU_PAGE_WT);
pt->exec_access = (err_code & MMU_PAGE_NX);
-
+
for (level = top_level; level > 0; level--) {
get_pt_entry(cpu, pt, level, pae);
@@ -181,14 +194,16 @@ static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code, struct gpt
return false;
}
- if (is_large)
+ if (is_large) {
break;
+ }
}
- if (!is_large)
+ if (!is_large) {
pt->gpa = (pt->pte[0] & page_mask) | (pt->gva & 0xfff);
- else
+ } else {
pt->gpa = large_page_gpa(pt, pae);
+ }
return true;
}
@@ -214,18 +229,20 @@ bool mmu_gva_to_gpa(struct CPUState *cpu, addr_t gva, addr_t *gpa)
return false;
}
-void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes)
+void vmx_write_mem(struct CPUState *cpu, addr_t gva, void *data, int bytes)
{
addr_t gpa;
while (bytes > 0) {
- // copy page
+ /* copy page */
int copy = MIN(bytes, 0x1000 - (gva & 0xfff));
if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
- VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __func__,
+ gva);
} else {
- address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 1);
+ address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
+ data, copy, 1);
}
bytes -= copy;
@@ -234,18 +251,20 @@ void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes)
}
}
-void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes)
+void vmx_read_mem(struct CPUState *cpu, void *data, addr_t gva, int bytes)
{
addr_t gpa;
while (bytes > 0) {
- // copy page
+ /* copy page */
int copy = MIN(bytes, 0x1000 - (gva & 0xfff));
if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
- VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __func__,
+ gva);
}
- address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 0);
+ address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED,
+ data, copy, 0);
bytes -= copy;
gva += copy;
diff --git a/target/i386/hvf-utils/x86_mmu.h b/target/i386/hvf-utils/x86_mmu.h
index c31bf28982..b5d2d59067 100644
--- a/target/i386/hvf-utils/x86_mmu.h
+++ b/target/i386/hvf-utils/x86_mmu.h
@@ -14,7 +14,7 @@
#define PT_GLOBAL (1 << 8)
#define PT_NX (1llu << 63)
-// error codes
+/* error codes */
#define MMU_PAGE_PT (1 << 0)
#define MMU_PAGE_WT (1 << 1)
#define MMU_PAGE_US (1 << 2)
@@ -22,7 +22,7 @@
bool mmu_gva_to_gpa(struct CPUState *cpu, addr_t gva, addr_t *gpa);
-void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes);
-void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes);
+void vmx_write_mem(struct CPUState *cpu, addr_t gva, void *data, int bytes);
+void vmx_read_mem(struct CPUState *cpu, void *data, addr_t gva, int bytes);
#endif /* __X86_MMU_H__ */
diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c
index 5c1d5ece36..819d760624 100644
--- a/target/i386/hvf-utils/x86hvf.c
+++ b/target/i386/hvf-utils/x86hvf.c
@@ -35,16 +35,16 @@
#include <Hypervisor/hv_vmx.h>
#include <stdint.h>
-void hvf_cpu_synchronize_state(struct CPUState* cpu_state);
-
-void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr)
+void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
+ SegmentCache *qseg, bool is_tr)
{
vmx_seg->sel = qseg->selector;
vmx_seg->base = qseg->base;
vmx_seg->limit = qseg->limit;
if (!qseg->selector && !x86_is_real(cpu) && !is_tr) {
- // the TR register is usable after processor reset despite having a null selector
+ /* the TR register is usable after processor reset despite
+ * having a null selector */
vmx_seg->ar = 1 << 16;
return;
}
@@ -87,19 +87,18 @@ void hvf_put_xsave(CPUState *cpu_state)
}
}
-void vmx_update_tpr(CPUState *cpu);
void hvf_put_segments(CPUState *cpu_state)
{
CPUX86State *env = &X86_CPU(cpu_state)->env;
struct vmx_segment seg;
-
+
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
- //wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]);
+ /* wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]); */
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]);
vmx_update_tpr(cpu_state);
wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer);
@@ -109,7 +108,7 @@ void hvf_put_segments(CPUState *cpu_state)
hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);
vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_CS);
-
+
hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false);
vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_DS);
@@ -130,17 +129,20 @@ void hvf_put_segments(CPUState *cpu_state)
hvf_set_segment(cpu_state, &seg, &env->ldt, false);
vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR);
-
+
hv_vcpu_flush(cpu_state->hvf_fd);
}
-
+
void hvf_put_msrs(CPUState *cpu_state)
{
CPUX86State *env = &X86_CPU(cpu_state)->env;
- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
- hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS,
+ env->sysenter_cs);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP,
+ env->sysenter_esp);
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP,
+ env->sysenter_eip);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star);
@@ -154,8 +156,8 @@ void hvf_put_msrs(CPUState *cpu_state)
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base);
hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base);
- // if (!osx_is_sierra())
- // wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());
+ /* if (!osx_is_sierra())
+ wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());*/
hv_vm_sync_tsc(env->tsc);
}
@@ -183,7 +185,7 @@ void hvf_get_segments(CPUState *cpu_state)
vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_CS);
hvf_get_segment(&env->segs[R_CS], &seg);
-
+
vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_DS);
hvf_get_segment(&env->segs[R_DS], &seg);
@@ -214,7 +216,7 @@ void hvf_get_segments(CPUState *cpu_state)
env->cr[2] = 0;
env->cr[3] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3);
env->cr[4] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4);
-
+
env->efer = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER);
}
@@ -222,10 +224,10 @@ void hvf_get_msrs(CPUState *cpu_state)
{
CPUX86State *env = &X86_CPU(cpu_state)->env;
uint64_t tmp;
-
+
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp);
env->sysenter_cs = tmp;
-
+
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp);
env->sysenter_esp = tmp;
@@ -242,7 +244,7 @@ void hvf_get_msrs(CPUState *cpu_state)
#endif
hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp);
-
+
env->tsc = rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET);
}
@@ -269,15 +271,15 @@ int hvf_put_registers(CPUState *cpu_state)
wreg(cpu_state->hvf_fd, HV_X86_R15, env->regs[15]);
wreg(cpu_state->hvf_fd, HV_X86_RFLAGS, env->eflags);
wreg(cpu_state->hvf_fd, HV_X86_RIP, env->eip);
-
+
wreg(cpu_state->hvf_fd, HV_X86_XCR0, env->xcr0);
-
+
hvf_put_xsave(cpu_state);
-
+
hvf_put_segments(cpu_state);
-
+
hvf_put_msrs(cpu_state);
-
+
wreg(cpu_state->hvf_fd, HV_X86_DR0, env->dr[0]);
wreg(cpu_state->hvf_fd, HV_X86_DR1, env->dr[1]);
wreg(cpu_state->hvf_fd, HV_X86_DR2, env->dr[2]);
@@ -286,7 +288,7 @@ int hvf_put_registers(CPUState *cpu_state)
wreg(cpu_state->hvf_fd, HV_X86_DR5, env->dr[5]);
wreg(cpu_state->hvf_fd, HV_X86_DR6, env->dr[6]);
wreg(cpu_state->hvf_fd, HV_X86_DR7, env->dr[7]);
-
+
return 0;
}
@@ -312,16 +314,16 @@ int hvf_get_registers(CPUState *cpu_state)
env->regs[13] = rreg(cpu_state->hvf_fd, HV_X86_R13);
env->regs[14] = rreg(cpu_state->hvf_fd, HV_X86_R14);
env->regs[15] = rreg(cpu_state->hvf_fd, HV_X86_R15);
-
+
env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
env->eip = rreg(cpu_state->hvf_fd, HV_X86_RIP);
-
+
hvf_get_xsave(cpu_state);
env->xcr0 = rreg(cpu_state->hvf_fd, HV_X86_XCR0);
-
+
hvf_get_segments(cpu_state);
hvf_get_msrs(cpu_state);
-
+
env->dr[0] = rreg(cpu_state->hvf_fd, HV_X86_DR0);
env->dr[1] = rreg(cpu_state->hvf_fd, HV_X86_DR1);
env->dr[2] = rreg(cpu_state->hvf_fd, HV_X86_DR2);
@@ -330,7 +332,7 @@ int hvf_get_registers(CPUState *cpu_state)
env->dr[5] = rreg(cpu_state->hvf_fd, HV_X86_DR5);
env->dr[6] = rreg(cpu_state->hvf_fd, HV_X86_DR6);
env->dr[7] = rreg(cpu_state->hvf_fd, HV_X86_DR7);
-
+
return 0;
}
@@ -338,14 +340,16 @@ static void vmx_set_int_window_exiting(CPUState *cpu)
{
uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val |
+ VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
}
void vmx_clear_int_window_exiting(CPUState *cpu)
{
uint64_t val;
val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
- wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val &
+ ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
}
#define NMI_VEC 2
@@ -353,28 +357,30 @@ void vmx_clear_int_window_exiting(CPUState *cpu)
void hvf_inject_interrupts(CPUState *cpu_state)
{
X86CPU *x86cpu = X86_CPU(cpu_state);
- int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
+ int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
+ VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);
uint64_t info = 0;
-
+
if (idt_info & VMCS_IDT_VEC_VALID) {
uint8_t vector = idt_info & 0xff;
uint64_t intr_type = idt_info & VMCS_INTR_T_MASK;
info = idt_info;
-
+
uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON);
if (intr_type == VMCS_INTR_T_NMI && reason != EXIT_REASON_TASK_SWITCH) {
allow_nmi = 1;
vmx_clear_nmi_blocking(cpu_state);
}
-
+
if ((allow_nmi || intr_type != VMCS_INTR_T_NMI)) {
info &= ~(1 << 12); /* clear undefined bit */
if (intr_type == VMCS_INTR_T_SWINTR ||
intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||
intr_type == VMCS_INTR_T_SWEXCEPTION) {
- uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ uint64_t ins_len = rvmcs(cpu_state->hvf_fd,
+ VMCS_EXIT_INSTRUCTION_LENGTH);
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
}
if (vector == EXCEPTION_BP || vector == EXCEPTION_OF) {
@@ -384,16 +390,17 @@ void hvf_inject_interrupts(CPUState *cpu_state)
*/
info &= ~VMCS_INTR_T_MASK;
info |= VMCS_INTR_T_SWEXCEPTION;
- uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ uint64_t ins_len = rvmcs(cpu_state->hvf_fd,
+ VMCS_EXIT_INSTRUCTION_LENGTH);
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
}
-
+
uint64_t err = 0;
if (idt_info & VMCS_INTR_DEL_ERRCODE) {
err = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR);
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err);
}
- //printf("reinject %lx err %d\n", info, err);
+ /*printf("reinject %lx err %d\n", info, err);*/
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
};
}
@@ -408,22 +415,26 @@ void hvf_inject_interrupts(CPUState *cpu_state)
}
}
- if (cpu_state->hvf_x86->interruptable && (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
+ if (cpu_state->hvf_x86->interruptable &&
+ (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
(EFLAGS(cpu_state) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
int line = cpu_get_pic_interrupt(&x86cpu->env);
cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
- if (line >= 0)
- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
+ if (line >= 0) {
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line |
+ VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
+ }
}
- if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD)
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) {
vmx_set_int_window_exiting(cpu_state);
+ }
}
int hvf_process_events(CPUState *cpu_state)
{
X86CPU *cpu = X86_CPU(cpu_state);
CPUX86State *env = &cpu->env;
-
+
EFLAGS(cpu_state) = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
@@ -435,7 +446,8 @@ int hvf_process_events(CPUState *cpu_state)
cpu_state->interrupt_request &= ~CPU_INTERRUPT_POLL;
apic_poll_irq(cpu->apic_state);
}
- if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu_state) & IF_MASK)) ||
+ if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (EFLAGS(cpu_state) & IF_MASK)) ||
(cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) {
cpu_state->halted = 0;
}
diff --git a/target/i386/hvf-utils/x86hvf.h b/target/i386/hvf-utils/x86hvf.h
index b4cb4c4d26..a81f7c41c7 100644
--- a/target/i386/hvf-utils/x86hvf.h
+++ b/target/i386/hvf-utils/x86hvf.h
@@ -7,7 +7,8 @@ int hvf_process_events(CPUState *);
int hvf_put_registers(CPUState *);
int hvf_get_registers(CPUState *);
void hvf_inject_interrupts(CPUState *);
-void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr);
+void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
+ SegmentCache *qseg, bool is_tr);
void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg);
void hvf_put_xsave(CPUState *cpu_state);
void hvf_put_segments(CPUState *cpu_state);
@@ -16,4 +17,6 @@ void hvf_get_xsave(CPUState *cpu_state);
void hvf_get_msrs(CPUState *cpu_state);
void vmx_clear_int_window_exiting(CPUState *cpu);
void hvf_get_segments(CPUState *cpu_state);
+void vmx_update_tpr(CPUState *cpu);
+void hvf_cpu_synchronize_state(CPUState *cpu_state);
#endif
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 08/14] apic: add function to apic that will be used by hvf
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (6 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 07/14] hvf: run hvf code through checkpatch.pl and fix style issues Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:36 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 09/14] hvf: implement hvf_get_supported_cpuid Sergio Andres Gomez Del Real
` (8 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit moves (hides) the function apic_get_highest_priority_irr to
apic.c and exports it through the interface in apic.h for use by hvf.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
hw/intc/apic.c | 11 +++++++++++
include/hw/i386/apic.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index fe15fb6024..3de59d07fd 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -305,6 +305,17 @@ static void apic_set_tpr(APICCommonState *s, uint8_t val)
}
}
+int apic_get_highest_priority_irr(DeviceState *dev)
+{
+ APICCommonState *s;
+
+ if (!dev) {
+ return -1;
+ }
+ s = APIC_COMMON(dev);
+ return get_highest_priority_int(s->irr);
+}
+
static uint8_t apic_get_tpr(APICCommonState *s)
{
apic_sync_vapic(s, SYNC_FROM_VAPIC);
diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h
index ea48ea9389..a9f6c0aa33 100644
--- a/include/hw/i386/apic.h
+++ b/include/hw/i386/apic.h
@@ -20,6 +20,7 @@ void apic_init_reset(DeviceState *s);
void apic_sipi(DeviceState *s);
void apic_poll_irq(DeviceState *d);
void apic_designate_bsp(DeviceState *d, bool bsp);
+int apic_get_highest_priority_irr(DeviceState *dev);
/* pc.c */
DeviceState *cpu_get_current_apic(void);
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 09/14] hvf: implement hvf_get_supported_cpuid
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (7 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 08/14] apic: add function to apic that will be used by hvf Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code Sergio Andres Gomez Del Real
` (7 subsequent siblings)
16 siblings, 0 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit implements hvf_get_supported_cpuid, which returns the set of
features supported by both the host processor and the hypervisor.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
target/i386/hvf-utils/x86_cpuid.c | 138 ++++++++++++++++++++++++++++++++++++++
1 file changed, 138 insertions(+)
diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf-utils/x86_cpuid.c
index 5d63bca8fd..6d405cd9dd 100644
--- a/target/i386/hvf-utils/x86_cpuid.c
+++ b/target/i386/hvf-utils/x86_cpuid.c
@@ -24,6 +24,7 @@
#include "x86_cpuid.h"
#include "x86.h"
#include "vmx.h"
+#include "sysemu/hvf.h"
#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
@@ -94,6 +95,27 @@ struct x86_cpuid builtin_cpus[] = {
static struct x86_cpuid *_cpuid;
+static uint64_t xgetbv(uint32_t xcr)
+{
+ uint32_t eax, edx;
+
+ __asm__ volatile ("xgetbv"
+ : "=a" (eax), "=d" (edx)
+ : "c" (xcr));
+
+ return (((uint64_t)edx) << 32) | eax;
+}
+
+static bool vmx_mpx_supported()
+{
+ uint64_t cap_exit, cap_entry;
+
+ hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cap_entry);
+ hv_vmx_read_capability(HV_VMX_CAP_EXIT, &cap_exit);
+
+ return ((cap_exit & (1 << 23)) && (cap_entry & (1 << 16)));
+}
+
void init_cpuid(struct CPUState *cpu)
{
_cpuid = &builtin_cpus[2]; /* core2duo */
@@ -277,3 +299,119 @@ void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax,
break;
}
}
+
+uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
+ int reg)
+{
+ uint64_t cap;
+ uint32_t eax, ebx, ecx, edx;
+
+ host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);
+
+ switch (func) {
+ case 0:
+ eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;
+ break;
+ case 1:
+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |
+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS;
+ ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |
+ CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |
+ CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE |
+ CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;
+ break;
+ case 6:
+ eax = 4;
+ ebx = 0;
+ ecx = 0;
+ edx = 0;
+ break;
+ case 7:
+ if (idx == 0) {
+ ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |
+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |
+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |
+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |
+ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_MPX;
+
+ if (!vmx_mpx_supported()) {
+ ebx &= ~CPUID_7_0_EBX_MPX;
+ }
+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
+ if (!(cap & CPU_BASED2_INVPCID)) {
+ ebx &= ~CPUID_7_0_EBX_INVPCID;
+ }
+
+ ecx &= CPUID_7_0_ECX_AVX512BMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;
+ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;
+ } else {
+ ebx = 0;
+ ecx = 0;
+ edx = 0;
+ }
+ eax = 0;
+ break;
+ case 0xD:
+ if (idx == 0) {
+ uint64_t host_xcr0 = xgetbv(0);
+ uint64_t supp_xcr0 = host_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK |
+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK |
+ XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |
+ XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK);
+ eax &= supp_xcr0;
+ if (!vmx_mpx_supported()) {
+ eax &= ~(XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK);
+ }
+ } else if (idx == 1) {
+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
+ eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;
+ if (!(cap & CPU_BASED2_XSAVES_XRSTORS)) {
+ eax &= ~CPUID_XSAVE_XSAVES;
+ }
+ }
+ break;
+ case 0x80000001:
+ /* LM only if HVF in 64-bit mode */
+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
+ CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |
+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |
+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;
+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);
+ if (!(cap & CPU_BASED_TSC_OFFSET)) {
+ edx &= ~CPUID_EXT2_RDTSCP;
+ }
+ ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |
+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |
+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |
+ CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;
+ break;
+ default:
+ return 0;
+ }
+
+ switch (reg) {
+ case R_EAX:
+ return eax;
+ case R_EBX:
+ return ebx;
+ case R_ECX:
+ return ecx;
+ case R_EDX:
+ return edx;
+ default:
+ return 0;
+ }
+}
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (8 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 09/14] hvf: implement hvf_get_supported_cpuid Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-29 9:44 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 11/14] hvf: implement vga dirty page tracking Sergio Andres Gomez Del Real
` (6 subsequent siblings)
16 siblings, 1 reply; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit adds code to request the cpuid features supported by the
host and hvf; it calls hvf_get_supported_cpuid if hvf is compiled with
QEMU and enabled.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
cpus.c | 2 +
include/qom/cpu.h | 6 +--
include/sysemu/hvf.h | 18 ++++++---
target/i386/cpu-qom.h | 4 +-
target/i386/cpu.c | 108 ++++++++++++++++++++++++++++++++++++++++----------
target/i386/hvf-all.c | 20 +++++-----
6 files changed, 113 insertions(+), 45 deletions(-)
diff --git a/cpus.c b/cpus.c
index 6754ce17cc..2411dfcd3f 100644
--- a/cpus.c
+++ b/cpus.c
@@ -37,7 +37,9 @@
#include "sysemu/hw_accel.h"
#include "sysemu/kvm.h"
#include "sysemu/hax.h"
+#ifdef CONFIG_HVF
#include "sysemu/hvf.h"
+#endif
#include "qmp-commands.h"
#include "exec/exec-all.h"
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index c46eb61240..ef74c2ce3c 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -408,13 +408,9 @@ struct CPUState {
*/
uint16_t pending_tlb_flush;
- // HVF
bool hvf_vcpu_dirty;
uint64_t hvf_fd; // fd of vcpu created by HVF
- // Supporting data structures for VMCS capabilities
- // and x86 emulation state
- struct hvf_vcpu_caps* hvf_caps;
- struct hvf_x86_state* hvf_x86;
+ struct hvf_x86_state *hvf_x86;
};
QTAILQ_HEAD(CPUTailQ, CPUState);
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index f9a5a9c5d3..5b92769b16 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -34,12 +34,6 @@ typedef struct hvf_slot {
int slot_id;
} hvf_slot;
-typedef struct HVFState {
- AccelState parent;
- hvf_slot slots[32];
- int num_slots;
-} HVFState;
-
struct hvf_vcpu_caps {
uint64_t vmx_cap_pinbased;
uint64_t vmx_cap_procbased;
@@ -49,6 +43,15 @@ struct hvf_vcpu_caps {
uint64_t vmx_cap_preemption_timer;
};
+typedef struct HVFState {
+ AccelState parent;
+ hvf_slot slots[32];
+ int num_slots;
+
+ struct hvf_vcpu_caps *hvf_caps;
+} HVFState;
+extern HVFState *hvf_state;
+
void hvf_set_phys_mem(MemoryRegionSection *, bool);
void hvf_handle_io(CPUArchState *, uint16_t, void *,
int, int, int);
@@ -87,6 +90,9 @@ void update_apic_tpr(CPUState *);
int hvf_put_registers(CPUState *);
void vmx_clear_int_window_exiting(CPUState *cpu);
+uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
+ int reg);
+
#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
#define HVF_STATE(obj) \
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index c2205e6077..22f95eb3a4 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -47,7 +47,7 @@ typedef struct X86CPUDefinition X86CPUDefinition;
/**
* X86CPUClass:
* @cpu_def: CPU model definition
- * @kvm_required: Whether CPU model requires KVM to be enabled.
+ * @host_cpuid_required: Whether CPU model requires cpuid from host.
* @ordering: Ordering on the "-cpu help" CPU model list.
* @migration_safe: See CpuDefinitionInfo::migration_safe
* @static_model: See CpuDefinitionInfo::static
@@ -66,7 +66,7 @@ typedef struct X86CPUClass {
*/
X86CPUDefinition *cpu_def;
- bool kvm_required;
+ bool host_cpuid_required;
int ordering;
bool migration_safe;
bool static_model;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ddc45abd70..8c531a0ffa 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -22,6 +22,9 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
+#ifdef CONFIG_HVF
+#include "sysemu/hvf.h"
+#endif
#include "sysemu/cpus.h"
#include "kvm_i386.h"
@@ -613,6 +616,23 @@ static uint32_t xsave_area_size(uint64_t mask)
return ret;
}
+static inline bool accel_uses_host_cpuid(void)
+{
+ bool enabled;
+#if defined(CONFIG_KVM)
+ enabled = kvm_enabled();
+#elif defined(CONFIG_HVF)
+ enabled = hvf_enabled();
+#else
+ enabled = 0;
+#endif
+ if (enabled) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
{
return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
@@ -1643,10 +1663,15 @@ static void max_x86_cpu_initfn(Object *obj)
*/
cpu->max_features = true;
- if (kvm_enabled()) {
+ if (accel_uses_host_cpuid()) {
char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
int family, model, stepping;
+ X86CPUDefinition host_cpudef = { };
+ uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
+
+ host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
+ x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
host_vendor_fms(vendor, &family, &model, &stepping);
@@ -1660,12 +1685,23 @@ static void max_x86_cpu_initfn(Object *obj)
object_property_set_str(OBJECT(cpu), model_id, "model-id",
&error_abort);
- env->cpuid_min_level =
- kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
- env->cpuid_min_xlevel =
- kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
- env->cpuid_min_xlevel2 =
- kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
+ if (kvm_enabled()) {
+ env->cpuid_min_level =
+ kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
+ } else {
+#if defined(CONFIG_HVF)
+ env->cpuid_min_level =
+ hvf_get_supported_cpuid(0x0, 0, R_EAX);
+ env->cpuid_min_xlevel =
+ hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
+ env->cpuid_min_xlevel2 =
+ hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
+#endif
+ }
if (lmce_supported()) {
object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
@@ -1691,18 +1727,25 @@ static const TypeInfo max_x86_cpu_type_info = {
.class_init = max_x86_cpu_class_init,
};
-#ifdef CONFIG_KVM
-
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
- xcc->kvm_required = true;
+ xcc->host_cpuid_required = true;
xcc->ordering = 8;
- xcc->model_description =
- "KVM processor with all supported host features "
- "(only available in KVM mode)";
+#if defined(CONFIG_KVM)
+ if (kvm_enabled()) {
+ xcc->model_description =
+ "KVM processor with all supported host features ";
+ }
+#elif defined(CONFIG_HVF)
+ if (hvf_enabled()) {
+ xcc->model_description =
+ "HVF processor with all supported host features ";
+ }
+#endif
}
static const TypeInfo host_x86_cpu_type_info = {
@@ -1724,7 +1767,7 @@ static void report_unavailable_features(FeatureWord w, uint32_t mask)
assert(reg);
fprintf(stderr, "warning: %s doesn't support requested feature: "
"CPUID.%02XH:%s%s%s [bit %d]\n",
- kvm_enabled() ? "host" : "TCG",
+ accel_uses_host_cpuid() ? "host" : "TCG",
f->cpuid_eax, reg,
f->feat_names[i] ? "." : "",
f->feat_names[i] ? f->feat_names[i] : "", i);
@@ -2175,7 +2218,7 @@ static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
Error *err = NULL;
strList **next = missing_feats;
- if (xcc->kvm_required && !kvm_enabled()) {
+ if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
strList *new = g_new0(strList, 1);
new->value = g_strdup("kvm");;
*missing_feats = new;
@@ -2337,7 +2380,15 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
wi->cpuid_ecx,
wi->cpuid_reg);
- } else if (tcg_enabled()) {
+ }
+#if defined(CONFIG_HVF)
+ else if (hvf_enabled()) {
+ r = hvf_get_supported_cpuid(wi->cpuid_eax,
+ wi->cpuid_ecx,
+ wi->cpuid_reg);
+ }
+#endif
+ else if (tcg_enabled()) {
r = wi->tcg_features;
} else {
return ~0;
@@ -2396,6 +2447,7 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
}
/* Special cases not set in the X86CPUDefinition structs: */
+ /* TODO: implement for hvf */
if (kvm_enabled()) {
if (!kvm_irqchip_in_kernel()) {
x86_cpu_change_kvm_default("x2apic", "off");
@@ -2416,7 +2468,7 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
* when doing cross vendor migration
*/
vendor = def->vendor;
- if (kvm_enabled()) {
+ if (accel_uses_host_cpuid()) {
uint32_t ebx = 0, ecx = 0, edx = 0;
host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
@@ -2872,7 +2924,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
- } else {
+ }
+#if defined(CONFIG_HVF)
+ else if (hvf_enabled() && cpu->enable_pmu) {
+ *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
+ *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
+ *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
+ *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
+ }
+#endif
+ else {
*eax = 0;
*ebx = 0;
*ecx = 0;
@@ -3220,6 +3281,7 @@ static void x86_cpu_reset(CPUState *s)
s->halted = !cpu_is_bsp(cpu);
+ /* TODO: implement for hvf */
if (kvm_enabled()) {
kvm_arch_reset_vcpu(cpu);
}
@@ -3262,6 +3324,7 @@ APICCommonClass *apic_get_class(void)
{
const char *apic_type = "apic";
+ /* TODO: implement for hvf */
if (kvm_apic_in_kernel()) {
apic_type = "kvm-apic";
} else if (xen_enabled()) {
@@ -3492,6 +3555,7 @@ static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
}
}
+ /* TODO: implement for hvf */
if (!kvm_enabled() || !cpu->expose_kvm) {
env->features[FEAT_KVM] = 0;
}
@@ -3575,7 +3639,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
Error *local_err = NULL;
static bool ht_warned;
- if (xcc->kvm_required && !kvm_enabled()) {
+ if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
char *name = x86_cpu_class_get_model_name(xcc);
error_setg(&local_err, "CPU model '%s' requires KVM", name);
g_free(name);
@@ -3597,7 +3661,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
x86_cpu_report_filtered_features(cpu);
if (cpu->enforce_cpuid) {
error_setg(&local_err,
- kvm_enabled() ?
+ accel_uses_host_cpuid() ?
"Host doesn't support requested features" :
"TCG doesn't support requested features");
goto out;
@@ -3620,7 +3684,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
* consumer AMD devices but nothing else.
*/
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
- if (kvm_enabled()) {
+ if (accel_uses_host_cpuid()) {
uint32_t host_phys_bits = x86_host_phys_bits();
static bool warned;
@@ -4207,7 +4271,7 @@ static void x86_cpu_register_types(void)
}
type_register_static(&max_x86_cpu_type_info);
type_register_static(&x86_base_cpu_type_info);
-#ifdef CONFIG_KVM
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
type_register_static(&host_x86_cpu_type_info);
#endif
}
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
index 88b5281975..11d20671f7 100644
--- a/target/i386/hvf-all.c
+++ b/target/i386/hvf-all.c
@@ -604,7 +604,7 @@ int hvf_init_vcpu(CPUState *cpu)
init_decoder(cpu);
init_cpuid(cpu);
- cpu->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
+ hvf_state->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
cpu->hvf_x86 = (struct hvf_x86_state *)g_malloc0(sizeof(struct hvf_x86_state));
r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);
@@ -612,37 +612,37 @@ int hvf_init_vcpu(CPUState *cpu)
assert_hvf_ok(r);
if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED,
- &cpu->hvf_caps->vmx_cap_pinbased)) {
+ &hvf_state->hvf_caps->vmx_cap_pinbased)) {
abort();
}
if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED,
- &cpu->hvf_caps->vmx_cap_procbased)) {
+ &hvf_state->hvf_caps->vmx_cap_procbased)) {
abort();
}
if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2,
- &cpu->hvf_caps->vmx_cap_procbased2)) {
+ &hvf_state->hvf_caps->vmx_cap_procbased2)) {
abort();
}
if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY,
- &cpu->hvf_caps->vmx_cap_entry)) {
+ &hvf_state->hvf_caps->vmx_cap_entry)) {
abort();
}
/* set VMCS control fields */
wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS,
- cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));
+ cap2ctrl(hvf_state->hvf_caps->vmx_cap_pinbased, 0));
wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS,
- cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,
+ cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased,
VMCS_PRI_PROC_BASED_CTLS_HLT |
VMCS_PRI_PROC_BASED_CTLS_MWAIT |
VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,
- cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,
+ cap2ctrl(hvf_state->hvf_caps->vmx_cap_procbased2,
VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
- wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry,
+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
0));
wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
@@ -829,7 +829,7 @@ int hvf_vcpu_exec(CPUState *cpu)
uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
- cpu_x86_cpuid(cpu, rax, rcx, &rax, &rbx, &rcx, &rdx);
+ cpu_x86_cpuid(env, rax, rcx, &rax, &rbx, &rcx, &rdx);
wreg(cpu->hvf_fd, HV_X86_RAX, rax);
wreg(cpu->hvf_fd, HV_X86_RBX, rbx);
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 11/14] hvf: implement vga dirty page tracking
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (9 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 12/14] hvf: move fields from CPUState to CPUX86State Sergio Andres Gomez Del Real
` (5 subsequent siblings)
16 siblings, 0 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit implements setting the tracking of dirty pages, using hvf's
interface to protect guest memory. It uses the MemoryListener callback
mechanism through .log_start/stop/sync
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
include/sysemu/hvf.h | 5 ++++
target/i386/hvf-all.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++-----
2 files changed, 70 insertions(+), 7 deletions(-)
diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
index 5b92769b16..90e9ec174e 100644
--- a/include/sysemu/hvf.h
+++ b/include/sysemu/hvf.h
@@ -27,11 +27,16 @@
#include <Hypervisor/hv_error.h>
#endif
+/* hvf_slot flags */
+#define HVF_SLOT_LOG (1 << 0)
+
typedef struct hvf_slot {
uint64_t start;
uint64_t size;
uint8_t *mem;
int slot_id;
+ uint32_t flags;
+ MemoryRegion *region;
} hvf_slot;
struct hvf_vcpu_caps {
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
index 11d20671f7..20c796089d 100644
--- a/target/i386/hvf-all.c
+++ b/target/i386/hvf-all.c
@@ -172,6 +172,7 @@ void hvf_set_phys_mem(MemoryRegionSection *section, bool add)
mem->size = int128_get64(section->size);
mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region;
mem->start = section->offset_within_address_space;
+ mem->region = area;
if (do_hvf_set_memory(mem)) {
fprintf(stderr, "Error registering new memory slot\n");
@@ -441,8 +442,7 @@ void hvf_cpu_synchronize_post_init(CPUState *cpu_state)
run_on_cpu(cpu_state, _hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
}
-/* TODO: ept fault handlig */
-static bool ept_emulation_fault(uint64_t ept_qual)
+static bool ept_emulation_fault(hvf_slot *slot, addr_t gpa, uint64_t ept_qual)
{
int read, write;
@@ -458,6 +458,14 @@ static bool ept_emulation_fault(uint64_t ept_qual)
return false;
}
+ if (write && slot) {
+ if (slot->flags & HVF_SLOT_LOG) {
+ memory_region_set_dirty(slot->region, gpa - slot->start, 1);
+ hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
+ HV_MEMORY_READ | HV_MEMORY_WRITE);
+ }
+ }
+
/*
* The EPT violation must have been caused by accessing a
* guest-physical address that is a translation of a guest-linear
@@ -468,7 +476,57 @@ static bool ept_emulation_fault(uint64_t ept_qual)
return false;
}
- return true;
+ return !slot;
+}
+
+static void hvf_set_dirty_tracking(MemoryRegionSection *section, bool on)
+{
+ struct mac_slot *macslot;
+ hvf_slot *slot;
+
+ slot = hvf_find_overlap_slot(
+ section->offset_within_address_space,
+ section->offset_within_address_space + int128_get64(section->size));
+
+ /* protect region against writes; begin tracking it */
+ if (on) {
+ slot->flags |= HVF_SLOT_LOG;
+ hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
+ HV_MEMORY_READ);
+ /* stop tracking region*/
+ } else {
+ slot->flags &= ~HVF_SLOT_LOG;
+ hv_vm_protect((hv_gpaddr_t)slot->start, (size_t)slot->size,
+ HV_MEMORY_READ | HV_MEMORY_WRITE);
+ }
+}
+
+static void hvf_log_start(MemoryListener *listener,
+ MemoryRegionSection *section, int old, int new)
+{
+ if (old != 0)
+ return;
+
+ hvf_set_dirty_tracking(section, 1);
+}
+
+static void hvf_log_stop(MemoryListener *listener,
+ MemoryRegionSection *section, int old, int new)
+{
+ if (new != 0)
+ return;
+
+ hvf_set_dirty_tracking(section, 0);
+}
+
+static void hvf_log_sync(MemoryListener *listener,
+ MemoryRegionSection *section)
+{
+ /*
+ * sync of dirty pages is handled elsewhere; just make sure we keep
+ * tracking the region.
+ */
+ hvf_set_dirty_tracking(section, 1);
}
static void hvf_region_add(MemoryListener *listener,
@@ -487,6 +545,9 @@ static MemoryListener hvf_memory_listener = {
.priority = 10,
.region_add = hvf_region_add,
.region_del = hvf_region_del,
+ .log_start = hvf_log_start,
+ .log_stop = hvf_log_stop,
+ .log_sync = hvf_log_sync,
};
void vmx_reset_vcpu(CPUState *cpu) {
@@ -763,7 +824,7 @@ int hvf_vcpu_exec(CPUState *cpu)
slot = hvf_find_overlap_slot(gpa, gpa);
/* mmio */
- if (ept_emulation_fault(exit_qual) && !slot) {
+ if (ept_emulation_fault(slot, gpa, exit_qual)) {
struct x86_decode decode;
load_regs(cpu);
@@ -774,9 +835,6 @@ int hvf_vcpu_exec(CPUState *cpu)
store_regs(cpu);
break;
}
-#ifdef DIRTY_VGA_TRACKING
- /* TODO: handle dirty page tracking */
-#endif
break;
}
case EXIT_REASON_INOUT:
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 12/14] hvf: move fields from CPUState to CPUX86State
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (10 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 11/14] hvf: implement vga dirty page tracking Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 13/14] hvf: refactor event injection code for hvf Sergio Andres Gomez Del Real
` (4 subsequent siblings)
16 siblings, 0 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit is a small refactoring of hvf's emulation code: it moves the
HVFX86EmulatorState field to CPUX86State, and in general changes, for
the emulation functions, the parameter with signature 'CPUState *' for
'CPUX86State *' so we don't have to get the 'env' (which is what we
really need) through the 'cpu' everytime.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
include/qom/cpu.h | 2 -
target/i386/cpu.h | 7 +
target/i386/hvf-all.c | 125 +++----
target/i386/hvf-utils/x86.c | 4 +-
target/i386/hvf-utils/x86.h | 34 +-
target/i386/hvf-utils/x86_decode.c | 357 ++++++++++----------
target/i386/hvf-utils/x86_decode.h | 23 +-
target/i386/hvf-utils/x86_emu.c | 673 +++++++++++++++++++------------------
target/i386/hvf-utils/x86_emu.h | 29 +-
target/i386/hvf-utils/x86_flags.c | 194 +++++------
target/i386/hvf-utils/x86_flags.h | 106 +++---
target/i386/hvf-utils/x86hvf.c | 14 +-
12 files changed, 794 insertions(+), 774 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index ef74c2ce3c..abe82a5b7c 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -408,9 +408,7 @@ struct CPUState {
*/
uint16_t pending_tlb_flush;
- bool hvf_vcpu_dirty;
uint64_t hvf_fd; // fd of vcpu created by HVF
- struct hvf_x86_state *hvf_x86;
};
QTAILQ_HEAD(CPUTailQ, CPUState);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7d90f08b98..1d056ee343 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -23,6 +23,9 @@
#include "qemu-common.h"
#include "cpu-qom.h"
#include "standard-headers/asm-x86/hyperv.h"
+#if defined(CONFIG_HVF)
+#include "target/i386/hvf-utils/x86.h"
+#endif
#ifdef TARGET_X86_64
#define TARGET_LONG_BITS 64
@@ -1187,11 +1190,15 @@ typedef struct CPUX86State {
int32_t interrupt_injected;
uint8_t soft_interrupt;
uint8_t has_error_code;
+ uint32_t ins_len;
uint32_t sipi_vector;
bool tsc_valid;
int64_t tsc_khz;
int64_t user_tsc_khz; /* for sanity check only */
void *kvm_xsave_buf;
+#if defined(CONFIG_HVF)
+ HVFX86EmulatorState *hvf_emul;
+#endif
uint64_t mcg_cap;
uint64_t mcg_ctl;
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
index 20c796089d..8a75723dcf 100644
--- a/target/i386/hvf-all.c
+++ b/target/i386/hvf-all.c
@@ -208,17 +208,20 @@ void update_apic_tpr(CPUState *cpu)
/* TODO: taskswitch handling */
static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
/* CR3 and ldt selector are not saved intentionally */
- tss->eip = EIP(cpu);
- tss->eflags = EFLAGS(cpu);
- tss->eax = EAX(cpu);
- tss->ecx = ECX(cpu);
- tss->edx = EDX(cpu);
- tss->ebx = EBX(cpu);
- tss->esp = ESP(cpu);
- tss->ebp = EBP(cpu);
- tss->esi = ESI(cpu);
- tss->edi = EDI(cpu);
+ tss->eip = EIP(env);
+ tss->eflags = EFLAGS(env);
+ tss->eax = EAX(env);
+ tss->ecx = ECX(env);
+ tss->edx = EDX(env);
+ tss->ebx = EBX(env);
+ tss->esp = ESP(env);
+ tss->ebp = EBP(env);
+ tss->esi = ESI(env);
+ tss->edi = EDI(env);
tss->es = vmx_read_segment_selector(cpu, REG_SEG_ES).sel;
tss->cs = vmx_read_segment_selector(cpu, REG_SEG_CS).sel;
@@ -230,20 +233,23 @@ static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3);
- RIP(cpu) = tss->eip;
- EFLAGS(cpu) = tss->eflags | 2;
+ RIP(env) = tss->eip;
+ EFLAGS(env) = tss->eflags | 2;
/* General purpose registers */
- RAX(cpu) = tss->eax;
- RCX(cpu) = tss->ecx;
- RDX(cpu) = tss->edx;
- RBX(cpu) = tss->ebx;
- RSP(cpu) = tss->esp;
- RBP(cpu) = tss->ebp;
- RSI(cpu) = tss->esi;
- RDI(cpu) = tss->edi;
+ RAX(env) = tss->eax;
+ RCX(env) = tss->ecx;
+ RDX(env) = tss->edx;
+ RBX(env) = tss->ebx;
+ RSP(env) = tss->esp;
+ RBP(env) = tss->ebp;
+ RSI(env) = tss->esi;
+ RDI(env) = tss->edi;
vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}},
REG_SEG_LDTR);
@@ -319,6 +325,8 @@ static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
uint32_t desc_limit;
struct x86_call_gate task_gate_desc;
struct vmx_segment vmx_seg;
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel);
x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
@@ -347,7 +355,7 @@ static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel,
}
if (reason == TSR_IRET) {
- EFLAGS(cpu) &= ~RFLAGS_NT;
+ EFLAGS(env) &= ~RFLAGS_NT;
}
if (reason != TSR_CALL && reason != TSR_IDT_GATE) {
@@ -404,16 +412,16 @@ void hvf_handle_io(CPUArchState *env, uint16_t port, void *buffer,
static void do_hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
{
CPUState *cpu_state = cpu;
- if (cpu_state->hvf_vcpu_dirty == 0) {
+ if (cpu_state->vcpu_dirty == 0) {
hvf_get_registers(cpu_state);
}
- cpu_state->hvf_vcpu_dirty = 1;
+ cpu_state->vcpu_dirty = 1;
}
void hvf_cpu_synchronize_state(CPUState *cpu_state)
{
- if (cpu_state->hvf_vcpu_dirty == 0) {
+ if (cpu_state->vcpu_dirty == 0) {
run_on_cpu(cpu_state, do_hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
}
}
@@ -422,7 +430,7 @@ static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg
{
CPUState *cpu_state = cpu;
hvf_put_registers(cpu_state);
- cpu_state->hvf_vcpu_dirty = false;
+ cpu_state->vcpu_dirty = false;
}
void hvf_cpu_synchronize_post_reset(CPUState *cpu_state)
@@ -434,7 +442,7 @@ void _hvf_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
{
CPUState *cpu_state = cpu;
hvf_put_registers(cpu_state);
- cpu_state->hvf_vcpu_dirty = false;
+ cpu_state->vcpu_dirty = false;
}
void hvf_cpu_synchronize_post_init(CPUState *cpu_state)
@@ -647,7 +655,8 @@ static void dummy_signal(int sig)
int hvf_init_vcpu(CPUState *cpu)
{
- X86CPU *x86cpu;
+ X86CPU *x86cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86cpu->env;
/* init cpu signals */
sigset_t set;
@@ -661,15 +670,15 @@ int hvf_init_vcpu(CPUState *cpu)
sigdelset(&set, SIG_IPI);
int r;
- init_emu(cpu);
- init_decoder(cpu);
+ init_emu();
+ init_decoder();
init_cpuid(cpu);
hvf_state->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
- cpu->hvf_x86 = (struct hvf_x86_state *)g_malloc0(sizeof(struct hvf_x86_state));
+ env->hvf_emul = (HVFX86EmulatorState *)g_malloc0(sizeof(HVFX86EmulatorState));
r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);
- cpu->hvf_vcpu_dirty = 1;
+ cpu->vcpu_dirty = 1;
assert_hvf_ok(r);
if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED,
@@ -755,12 +764,12 @@ int hvf_vcpu_exec(CPUState *cpu)
}
do {
- if (cpu->hvf_vcpu_dirty) {
+ if (cpu->vcpu_dirty) {
hvf_put_registers(cpu);
- cpu->hvf_vcpu_dirty = false;
+ cpu->vcpu_dirty = false;
}
- cpu->hvf_x86->interruptable =
+ env->hvf_emul->interruptable =
!(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
(VMCS_INTERRUPTIBILITY_STI_BLOCKING |
VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
@@ -785,8 +794,8 @@ int hvf_vcpu_exec(CPUState *cpu)
VMCS_EXIT_INSTRUCTION_LENGTH);
uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
rip = rreg(cpu->hvf_fd, HV_X86_RIP);
- RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
- env->eflags = RFLAGS(cpu);
+ RFLAGS(env) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
+ env->eflags = RFLAGS(env);
qemu_mutex_lock_iothread();
@@ -798,7 +807,7 @@ int hvf_vcpu_exec(CPUState *cpu)
case EXIT_REASON_HLT: {
macvm_set_rip(cpu, rip + ins_len);
if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
- (EFLAGS(cpu) & IF_MASK))
+ (EFLAGS(env) & IF_MASK))
&& !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
!(idtvec_info & VMCS_IDT_VEC_VALID)) {
cpu->halted = 1;
@@ -828,10 +837,10 @@ int hvf_vcpu_exec(CPUState *cpu)
struct x86_decode decode;
load_regs(cpu);
- cpu->hvf_x86->fetch_rip = rip;
+ env->hvf_emul->fetch_rip = rip;
- decode_instruction(cpu, &decode);
- exec_instruction(cpu, &decode);
+ decode_instruction(env, &decode);
+ exec_instruction(env, &decode);
store_regs(cpu);
break;
}
@@ -851,20 +860,20 @@ int hvf_vcpu_exec(CPUState *cpu)
load_regs(cpu);
hvf_handle_io(env, port, &val, 0, size, 1);
if (size == 1) {
- AL(cpu) = val;
+ AL(env) = val;
} else if (size == 2) {
- AX(cpu) = val;
+ AX(env) = val;
} else if (size == 4) {
- RAX(cpu) = (uint32_t)val;
+ RAX(env) = (uint32_t)val;
} else {
VM_PANIC("size");
}
- RIP(cpu) += ins_len;
+ RIP(env) += ins_len;
store_regs(cpu);
break;
} else if (!string && !in) {
- RAX(cpu) = rreg(cpu->hvf_fd, HV_X86_RAX);
- hvf_handle_io(env, port, &RAX(cpu), 1, size, 1);
+ RAX(env) = rreg(cpu->hvf_fd, HV_X86_RAX);
+ hvf_handle_io(env, port, &RAX(env), 1, size, 1);
macvm_set_rip(cpu, rip + ins_len);
break;
}
@@ -872,11 +881,11 @@ int hvf_vcpu_exec(CPUState *cpu)
struct x86_decode decode;
load_regs(cpu);
- cpu->hvf_x86->fetch_rip = rip;
+ env->hvf_emul->fetch_rip = rip;
- decode_instruction(cpu, &decode);
+ decode_instruction(env, &decode);
VM_PANIC_ON(ins_len != decode.len);
- exec_instruction(cpu, &decode);
+ exec_instruction(env, &decode);
store_regs(cpu);
break;
@@ -934,7 +943,7 @@ int hvf_vcpu_exec(CPUState *cpu)
} else {
simulate_wrmsr(cpu);
}
- RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
+ RIP(env) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
store_regs(cpu);
break;
}
@@ -948,19 +957,19 @@ int hvf_vcpu_exec(CPUState *cpu)
switch (cr) {
case 0x0: {
- macvm_set_cr0(cpu->hvf_fd, RRX(cpu, reg));
+ macvm_set_cr0(cpu->hvf_fd, RRX(env, reg));
break;
}
case 4: {
- macvm_set_cr4(cpu->hvf_fd, RRX(cpu, reg));
+ macvm_set_cr4(cpu->hvf_fd, RRX(env, reg));
break;
}
case 8: {
X86CPU *x86_cpu = X86_CPU(cpu);
if (exit_qual & 0x10) {
- RRX(cpu, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
+ RRX(env, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
} else {
- int tpr = RRX(cpu, reg);
+ int tpr = RRX(env, reg);
cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
ret = EXCP_INTERRUPT;
}
@@ -970,7 +979,7 @@ int hvf_vcpu_exec(CPUState *cpu)
fprintf(stderr, "Unrecognized CR %d\n", cr);
abort();
}
- RIP(cpu) += ins_len;
+ RIP(env) += ins_len;
store_regs(cpu);
break;
}
@@ -978,10 +987,10 @@ int hvf_vcpu_exec(CPUState *cpu)
struct x86_decode decode;
load_regs(cpu);
- cpu->hvf_x86->fetch_rip = rip;
+ env->hvf_emul->fetch_rip = rip;
- decode_instruction(cpu, &decode);
- exec_instruction(cpu, &decode);
+ decode_instruction(env, &decode);
+ exec_instruction(env, &decode);
store_regs(cpu);
break;
}
diff --git a/target/i386/hvf-utils/x86.c b/target/i386/hvf-utils/x86.c
index 07eb5a8586..0df3d23ec9 100644
--- a/target/i386/hvf-utils/x86.c
+++ b/target/i386/hvf-utils/x86.c
@@ -127,7 +127,9 @@ bool x86_is_real(struct CPUState *cpu)
bool x86_is_v8086(struct CPUState *cpu)
{
- return x86_is_protected(cpu) && (RFLAGS(cpu) & RFLAGS_VM);
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+ return x86_is_protected(cpu) && (RFLAGS(env) & RFLAGS_VM);
}
bool x86_is_long_mode(struct CPUState *cpu)
diff --git a/target/i386/hvf-utils/x86.h b/target/i386/hvf-utils/x86.h
index 435b49ae04..59a21b6e41 100644
--- a/target/i386/hvf-utils/x86.h
+++ b/target/i386/hvf-utils/x86.h
@@ -23,7 +23,7 @@
#include <sys/mman.h>
#include <stdarg.h>
#include "qemu-common.h"
-#include "x86_flags.h"
+#include "x86_gen.h"
/* exceptions */
typedef enum x86_exception {
@@ -356,13 +356,14 @@ typedef struct x68_segment_selector {
};
} __attribute__ ((__packed__)) x68_segment_selector;
-/* Definition of hvf_x86_state is here */
-struct hvf_x86_state {
- int hlt;
- uint64_t init_tsc;
+typedef struct lazy_flags {
+ addr_t result;
+ addr_t auxbits;
+} lazy_flags;
+/* Definition of hvf_x86_state is here */
+typedef struct HVFX86EmulatorState {
int interruptable;
- uint64_t exp_rip;
uint64_t fetch_rip;
uint64_t rip;
struct x86_register regs[16];
@@ -370,8 +371,7 @@ struct hvf_x86_state {
struct lazy_flags lflags;
struct x86_efer efer;
uint8_t mmio_buf[4096];
- uint8_t *apic_page;
-};
+} HVFX86EmulatorState;
/*
* hvf xsave area
@@ -381,12 +381,12 @@ struct hvf_xsave_buf {
};
/* useful register access macros */
-#define RIP(cpu) (cpu->hvf_x86->rip)
-#define EIP(cpu) ((uint32_t)cpu->hvf_x86->rip)
-#define RFLAGS(cpu) (cpu->hvf_x86->rflags.rflags)
-#define EFLAGS(cpu) (cpu->hvf_x86->rflags.eflags)
+#define RIP(cpu) (cpu->hvf_emul->rip)
+#define EIP(cpu) ((uint32_t)cpu->hvf_emul->rip)
+#define RFLAGS(cpu) (cpu->hvf_emul->rflags.rflags)
+#define EFLAGS(cpu) (cpu->hvf_emul->rflags.eflags)
-#define RRX(cpu, reg) (cpu->hvf_x86->regs[reg].rrx)
+#define RRX(cpu, reg) (cpu->hvf_emul->regs[reg].rrx)
#define RAX(cpu) RRX(cpu, REG_RAX)
#define RCX(cpu) RRX(cpu, REG_RCX)
#define RDX(cpu) RRX(cpu, REG_RDX)
@@ -404,7 +404,7 @@ struct hvf_xsave_buf {
#define R14(cpu) RRX(cpu, REG_R14)
#define R15(cpu) RRX(cpu, REG_R15)
-#define ERX(cpu, reg) (cpu->hvf_x86->regs[reg].erx)
+#define ERX(cpu, reg) (cpu->hvf_emul->regs[reg].erx)
#define EAX(cpu) ERX(cpu, REG_RAX)
#define ECX(cpu) ERX(cpu, REG_RCX)
#define EDX(cpu) ERX(cpu, REG_RDX)
@@ -414,7 +414,7 @@ struct hvf_xsave_buf {
#define ESI(cpu) ERX(cpu, REG_RSI)
#define EDI(cpu) ERX(cpu, REG_RDI)
-#define RX(cpu, reg) (cpu->hvf_x86->regs[reg].rx)
+#define RX(cpu, reg) (cpu->hvf_emul->regs[reg].rx)
#define AX(cpu) RX(cpu, REG_RAX)
#define CX(cpu) RX(cpu, REG_RCX)
#define DX(cpu) RX(cpu, REG_RDX)
@@ -424,13 +424,13 @@ struct hvf_xsave_buf {
#define SI(cpu) RX(cpu, REG_RSI)
#define DI(cpu) RX(cpu, REG_RDI)
-#define RL(cpu, reg) (cpu->hvf_x86->regs[reg].lx)
+#define RL(cpu, reg) (cpu->hvf_emul->regs[reg].lx)
#define AL(cpu) RL(cpu, REG_RAX)
#define CL(cpu) RL(cpu, REG_RCX)
#define DL(cpu) RL(cpu, REG_RDX)
#define BL(cpu) RL(cpu, REG_RBX)
-#define RH(cpu, reg) (cpu->hvf_x86->regs[reg].hx)
+#define RH(cpu, reg) (cpu->hvf_emul->regs[reg].hx)
#define AH(cpu) RH(cpu, REG_RAX)
#define CH(cpu) RH(cpu, REG_RCX)
#define DH(cpu) RH(cpu, REG_RDX)
diff --git a/target/i386/hvf-utils/x86_decode.c b/target/i386/hvf-utils/x86_decode.c
index 4faf82f721..e28b1ddade 100644
--- a/target/i386/hvf-utils/x86_decode.c
+++ b/target/i386/hvf-utils/x86_decode.c
@@ -27,9 +27,9 @@
#define OPCODE_ESCAPE 0xf
-static void decode_invalid(CPUState *cpu, struct x86_decode *decode)
+static void decode_invalid(CPUX86State *env, struct x86_decode *decode)
{
- printf("%llx: failed to decode instruction ", cpu->hvf_x86->fetch_rip -
+ printf("%llx: failed to decode instruction ", env->hvf_emul->fetch_rip -
decode->len);
for (int i = 0; i < decode->opcode_len; i++) {
printf("%x ", decode->opcode[i]);
@@ -60,7 +60,7 @@ uint64_t sign(uint64_t val, int size)
return val;
}
-static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode,
+static inline uint64_t decode_bytes(CPUX86State *env, struct x86_decode *decode,
int size)
{
addr_t val = 0;
@@ -75,129 +75,129 @@ static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode,
VM_PANIC_EX("%s invalid size %d\n", __func__, size);
break;
}
- addr_t va = linear_rip(cpu, RIP(cpu)) + decode->len;
- vmx_read_mem(cpu, &val, va, size);
+ addr_t va = linear_rip(ENV_GET_CPU(env), RIP(env)) + decode->len;
+ vmx_read_mem(ENV_GET_CPU(env), &val, va, size);
decode->len += size;
return val;
}
-static inline uint8_t decode_byte(CPUState *cpu, struct x86_decode *decode)
+static inline uint8_t decode_byte(CPUX86State *env, struct x86_decode *decode)
{
- return (uint8_t)decode_bytes(cpu, decode, 1);
+ return (uint8_t)decode_bytes(env, decode, 1);
}
-static inline uint16_t decode_word(CPUState *cpu, struct x86_decode *decode)
+static inline uint16_t decode_word(CPUX86State *env, struct x86_decode *decode)
{
- return (uint16_t)decode_bytes(cpu, decode, 2);
+ return (uint16_t)decode_bytes(env, decode, 2);
}
-static inline uint32_t decode_dword(CPUState *cpu, struct x86_decode *decode)
+static inline uint32_t decode_dword(CPUX86State *env, struct x86_decode *decode)
{
- return (uint32_t)decode_bytes(cpu, decode, 4);
+ return (uint32_t)decode_bytes(env, decode, 4);
}
-static inline uint64_t decode_qword(CPUState *cpu, struct x86_decode *decode)
+static inline uint64_t decode_qword(CPUX86State *env, struct x86_decode *decode)
{
- return decode_bytes(cpu, decode, 8);
+ return decode_bytes(env, decode, 8);
}
-static void decode_modrm_rm(CPUState *cpu, struct x86_decode *decode,
+static void decode_modrm_rm(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_RM;
}
-static void decode_modrm_reg(CPUState *cpu, struct x86_decode *decode,
+static void decode_modrm_reg(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = decode->modrm.reg;
- op->ptr = get_reg_ref(cpu, op->reg, decode->rex.r, decode->operand_size);
+ op->ptr = get_reg_ref(env, op->reg, decode->rex.r, decode->operand_size);
}
-static void decode_rax(CPUState *cpu, struct x86_decode *decode,
+static void decode_rax(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = REG_RAX;
- op->ptr = get_reg_ref(cpu, op->reg, 0, decode->operand_size);
+ op->ptr = get_reg_ref(env, op->reg, 0, decode->operand_size);
}
-static inline void decode_immediate(CPUState *cpu, struct x86_decode *decode,
+static inline void decode_immediate(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *var, int size)
{
var->type = X86_VAR_IMMEDIATE;
var->size = size;
switch (size) {
case 1:
- var->val = decode_byte(cpu, decode);
+ var->val = decode_byte(env, decode);
break;
case 2:
- var->val = decode_word(cpu, decode);
+ var->val = decode_word(env, decode);
break;
case 4:
- var->val = decode_dword(cpu, decode);
+ var->val = decode_dword(env, decode);
break;
case 8:
- var->val = decode_qword(cpu, decode);
+ var->val = decode_qword(env, decode);
break;
default:
VM_PANIC_EX("bad size %d\n", size);
}
}
-static void decode_imm8(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm8(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
- decode_immediate(cpu, decode, op, 1);
+ decode_immediate(env, decode, op, 1);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm8_signed(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm8_signed(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
- decode_immediate(cpu, decode, op, 1);
+ decode_immediate(env, decode, op, 1);
op->val = sign(op->val, 1);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm16(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm16(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
- decode_immediate(cpu, decode, op, 2);
+ decode_immediate(env, decode, op, 2);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
if (8 == decode->operand_size) {
- decode_immediate(cpu, decode, op, 4);
+ decode_immediate(env, decode, op, 4);
op->val = sign(op->val, decode->operand_size);
} else {
- decode_immediate(cpu, decode, op, decode->operand_size);
+ decode_immediate(env, decode, op, decode->operand_size);
}
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm_signed(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm_signed(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
- decode_immediate(cpu, decode, op, decode->operand_size);
+ decode_immediate(env, decode, op, decode->operand_size);
op->val = sign(op->val, decode->operand_size);
op->type = X86_VAR_IMMEDIATE;
}
-static void decode_imm_1(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm_1(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_IMMEDIATE;
op->val = 1;
}
-static void decode_imm_0(CPUState *cpu, struct x86_decode *decode,
+static void decode_imm_0(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_IMMEDIATE;
@@ -205,7 +205,7 @@ static void decode_imm_0(CPUState *cpu, struct x86_decode *decode,
}
-static void decode_pushseg(CPUState *cpu, struct x86_decode *decode)
+static void decode_pushseg(CPUX86State *env, struct x86_decode *decode)
{
uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
@@ -232,7 +232,7 @@ static void decode_pushseg(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_popseg(CPUState *cpu, struct x86_decode *decode)
+static void decode_popseg(CPUX86State *env, struct x86_decode *decode)
{
uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
@@ -259,23 +259,23 @@ static void decode_popseg(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_incgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_incgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x40;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
}
-static void decode_decgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_decgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x48;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
}
-static void decode_incgroup2(CPUState *cpu, struct x86_decode *decode)
+static void decode_incgroup2(CPUX86State *env, struct x86_decode *decode)
{
if (!decode->modrm.reg) {
decode->cmd = X86_DECODE_CMD_INC;
@@ -284,36 +284,36 @@ static void decode_incgroup2(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_pushgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_pushgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x50;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
}
-static void decode_popgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_popgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x58;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
}
-static void decode_jxx(CPUState *cpu, struct x86_decode *decode)
+static void decode_jxx(CPUX86State *env, struct x86_decode *decode)
{
- decode->displacement = decode_bytes(cpu, decode, decode->operand_size);
+ decode->displacement = decode_bytes(env, decode, decode->operand_size);
decode->displacement_size = decode->operand_size;
}
-static void decode_farjmp(CPUState *cpu, struct x86_decode *decode)
+static void decode_farjmp(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_IMMEDIATE;
- decode->op[0].val = decode_bytes(cpu, decode, decode->operand_size);
- decode->displacement = decode_word(cpu, decode);
+ decode->op[0].val = decode_bytes(env, decode, decode->operand_size);
+ decode->displacement = decode_word(env, decode);
}
-static void decode_addgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_addgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_ADD,
@@ -328,7 +328,7 @@ static void decode_addgroup(CPUState *cpu, struct x86_decode *decode)
decode->cmd = group[decode->modrm.reg];
}
-static void decode_rotgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_rotgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_ROL,
@@ -343,7 +343,7 @@ static void decode_rotgroup(CPUState *cpu, struct x86_decode *decode)
decode->cmd = group[decode->modrm.reg];
}
-static void decode_f7group(CPUState *cpu, struct x86_decode *decode)
+static void decode_f7group(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_TST,
@@ -356,12 +356,12 @@ static void decode_f7group(CPUState *cpu, struct x86_decode *decode)
X86_DECODE_CMD_IDIV
};
decode->cmd = group[decode->modrm.reg];
- decode_modrm_rm(cpu, decode, &decode->op[0]);
+ decode_modrm_rm(env, decode, &decode->op[0]);
switch (decode->modrm.reg) {
case 0:
case 1:
- decode_imm(cpu, decode, &decode->op[1]);
+ decode_imm(env, decode, &decode->op[1]);
break;
case 2:
break;
@@ -374,45 +374,45 @@ static void decode_f7group(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_xchgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_xchgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0x90;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
}
-static void decode_movgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_movgroup(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0xb8;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
- decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
+ decode_immediate(env, decode, &decode->op[1], decode->operand_size);
}
-static void fetch_moffs(CPUState *cpu, struct x86_decode *decode,
+static void fetch_moffs(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_OFFSET;
- op->ptr = decode_bytes(cpu, decode, decode->addressing_size);
+ op->ptr = decode_bytes(env, decode, decode->addressing_size);
}
-static void decode_movgroup8(CPUState *cpu, struct x86_decode *decode)
+static void decode_movgroup8(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[0] - 0xb0;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
- decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
+ decode_immediate(env, decode, &decode->op[1], decode->operand_size);
}
-static void decode_rcx(CPUState *cpu, struct x86_decode *decode,
+static void decode_rcx(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X86_VAR_REG;
op->reg = REG_RCX;
- op->ptr = get_reg_ref(cpu, op->reg, decode->rex.b, decode->operand_size);
+ op->ptr = get_reg_ref(env, op->reg, decode->rex.b, decode->operand_size);
}
struct decode_tbl {
@@ -420,15 +420,15 @@ struct decode_tbl {
enum x86_decode_cmd cmd;
uint8_t operand_size;
bool is_modrm;
- void (*decode_op1)(CPUState *cpu, struct x86_decode *decode,
+ void (*decode_op1)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op1);
- void (*decode_op2)(CPUState *cpu, struct x86_decode *decode,
+ void (*decode_op2)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op2);
- void (*decode_op3)(CPUState *cpu, struct x86_decode *decode,
+ void (*decode_op3)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op3);
- void (*decode_op4)(CPUState *cpu, struct x86_decode *decode,
+ void (*decode_op4)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op4);
- void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
+ void (*decode_postfix)(CPUX86State *env, struct x86_decode *decode);
addr_t flags_mask;
};
@@ -440,11 +440,11 @@ struct decode_x87_tbl {
uint8_t operand_size;
bool rev;
bool pop;
- void (*decode_op1)(CPUState *cpu, struct x86_decode *decode,
+ void (*decode_op1)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op1);
- void (*decode_op2)(CPUState *cpu, struct x86_decode *decode,
+ void (*decode_op2)(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op2);
- void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
+ void (*decode_postfix)(CPUX86State *env, struct x86_decode *decode);
addr_t flags_mask;
};
@@ -455,7 +455,7 @@ struct decode_tbl _decode_tbl1[255];
struct decode_tbl _decode_tbl2[255];
struct decode_x87_tbl _decode_tbl3[255];
-static void decode_x87_ins(CPUState *cpu, struct x86_decode *decode)
+static void decode_x87_ins(CPUX86State *env, struct x86_decode *decode)
{
struct decode_x87_tbl *decoder;
@@ -475,13 +475,13 @@ static void decode_x87_ins(CPUState *cpu, struct x86_decode *decode)
decode->frev = decoder->rev;
if (decoder->decode_op1) {
- decoder->decode_op1(cpu, decode, &decode->op[0]);
+ decoder->decode_op1(env, decode, &decode->op[0]);
}
if (decoder->decode_op2) {
- decoder->decode_op2(cpu, decode, &decode->op[1]);
+ decoder->decode_op2(env, decode, &decode->op[1]);
}
if (decoder->decode_postfix) {
- decoder->decode_postfix(cpu, decode);
+ decoder->decode_postfix(env, decode);
}
VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n",
@@ -489,7 +489,7 @@ static void decode_x87_ins(CPUState *cpu, struct x86_decode *decode)
decoder->modrm_mod);
}
-static void decode_ffgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_ffgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_INC,
@@ -508,8 +508,9 @@ static void decode_ffgroup(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_sldtgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_sldtgroup(CPUX86State *env, struct x86_decode *decode)
{
+
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_SLDT,
X86_DECODE_CMD_STR,
@@ -521,11 +522,11 @@ static void decode_sldtgroup(CPUState *cpu, struct x86_decode *decode)
X86_DECODE_CMD_INVL
};
decode->cmd = group[decode->modrm.reg];
- printf("%llx: decode_sldtgroup: %d\n", cpu->hvf_x86->fetch_rip,
+ printf("%llx: decode_sldtgroup: %d\n", env->hvf_emul->fetch_rip,
decode->modrm.reg);
}
-static void decode_lidtgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_lidtgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_SGDT,
@@ -544,7 +545,7 @@ static void decode_lidtgroup(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_btgroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_btgroup(CPUX86State *env, struct x86_decode *decode)
{
enum x86_decode_cmd group[] = {
X86_DECODE_CMD_INVL,
@@ -559,37 +560,37 @@ static void decode_btgroup(CPUState *cpu, struct x86_decode *decode)
decode->cmd = group[decode->modrm.reg];
}
-static void decode_x87_general(CPUState *cpu, struct x86_decode *decode)
+static void decode_x87_general(CPUX86State *env, struct x86_decode *decode)
{
decode->is_fpu = true;
}
-static void decode_x87_modrm_floatp(CPUState *cpu, struct x86_decode *decode,
+static void decode_x87_modrm_floatp(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_FLOATP;
}
-static void decode_x87_modrm_intp(CPUState *cpu, struct x86_decode *decode,
+static void decode_x87_modrm_intp(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_INTP;
}
-static void decode_x87_modrm_bytep(CPUState *cpu, struct x86_decode *decode,
+static void decode_x87_modrm_bytep(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_BYTEP;
}
-static void decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode,
+static void decode_x87_modrm_st0(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
op->type = X87_VAR_REG;
op->reg = 0;
}
-static void decode_decode_x87_modrm_st0(CPUState *cpu,
+static void decode_decode_x87_modrm_st0(CPUX86State *env,
struct x86_decode *decode,
struct x86_decode_op *op)
{
@@ -598,16 +599,16 @@ static void decode_decode_x87_modrm_st0(CPUState *cpu,
}
-static void decode_aegroup(CPUState *cpu, struct x86_decode *decode)
+static void decode_aegroup(CPUX86State *env, struct x86_decode *decode)
{
decode->is_fpu = true;
switch (decode->modrm.reg) {
case 0:
decode->cmd = X86_DECODE_CMD_FXSAVE;
- decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
+ decode_x87_modrm_bytep(env, decode, &decode->op[0]);
break;
case 1:
- decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
+ decode_x87_modrm_bytep(env, decode, &decode->op[0]);
decode->cmd = X86_DECODE_CMD_FXRSTOR;
break;
case 5:
@@ -634,15 +635,15 @@ static void decode_aegroup(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_bswap(CPUState *cpu, struct x86_decode *decode)
+static void decode_bswap(CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = decode->opcode[1] - 0xc8;
- decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b,
+ decode->op[0].ptr = get_reg_ref(env, decode->op[0].reg, decode->rex.b,
decode->operand_size);
}
-static void decode_d9_4(CPUState *cpu, struct x86_decode *decode)
+static void decode_d9_4(CPUX86State *env, struct x86_decode *decode)
{
switch (decode->modrm.modrm) {
case 0xe0:
@@ -665,7 +666,7 @@ static void decode_d9_4(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_db_4(CPUState *cpu, struct x86_decode *decode)
+static void decode_db_4(CPUX86State *env, struct x86_decode *decode)
{
switch (decode->modrm.modrm) {
case 0xe0:
@@ -1633,7 +1634,7 @@ struct decode_x87_tbl _x87_inst[] = {
decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
};
-void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode,
+void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
addr_t ptr = 0;
@@ -1650,42 +1651,42 @@ void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode,
switch (decode->modrm.rm) {
case 0:
- ptr += BX(cpu) + SI(cpu);
+ ptr += BX(env) + SI(env);
break;
case 1:
- ptr += BX(cpu) + DI(cpu);
+ ptr += BX(env) + DI(env);
break;
case 2:
- ptr += BP(cpu) + SI(cpu);
+ ptr += BP(env) + SI(env);
seg = REG_SEG_SS;
break;
case 3:
- ptr += BP(cpu) + DI(cpu);
+ ptr += BP(env) + DI(env);
seg = REG_SEG_SS;
break;
case 4:
- ptr += SI(cpu);
+ ptr += SI(env);
break;
case 5:
- ptr += DI(cpu);
+ ptr += DI(env);
break;
case 6:
- ptr += BP(cpu);
+ ptr += BP(env);
seg = REG_SEG_SS;
break;
case 7:
- ptr += BX(cpu);
+ ptr += BX(env);
break;
}
calc_addr:
if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = (uint16_t)ptr;
} else {
- op->ptr = decode_linear_addr(cpu, decode, (uint16_t)ptr, seg);
+ op->ptr = decode_linear_addr(env, decode, (uint16_t)ptr, seg);
}
}
-addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
+addr_t get_reg_ref(CPUX86State *env, int reg, int is_extended, int size)
{
addr_t ptr = 0;
int which = 0;
@@ -1699,28 +1700,28 @@ addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
case 1:
if (is_extended || reg < 4) {
which = 1;
- ptr = (addr_t)&RL(cpu, reg);
+ ptr = (addr_t)&RL(env, reg);
} else {
which = 2;
- ptr = (addr_t)&RH(cpu, reg - 4);
+ ptr = (addr_t)&RH(env, reg - 4);
}
break;
default:
which = 3;
- ptr = (addr_t)&RRX(cpu, reg);
+ ptr = (addr_t)&RRX(env, reg);
break;
}
return ptr;
}
-addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size)
+addr_t get_reg_val(CPUX86State *env, int reg, int is_extended, int size)
{
addr_t val = 0;
- memcpy(&val, (void *)get_reg_ref(cpu, reg, is_extended, size), size);
+ memcpy(&val, (void *)get_reg_ref(env, reg, is_extended, size), size);
return val;
}
-static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode,
+static addr_t get_sib_val(CPUX86State *env, struct x86_decode *decode,
x86_reg_segment *sel)
{
addr_t base = 0;
@@ -1738,7 +1739,7 @@ static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode,
if (REG_RSP == base_reg || REG_RBP == base_reg) {
*sel = REG_SEG_SS;
}
- base = get_reg_val(cpu, decode->sib.base, decode->rex.b, addr_size);
+ base = get_reg_val(env, decode->sib.base, decode->rex.b, addr_size);
}
if (decode->rex.x) {
@@ -1746,13 +1747,13 @@ static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode,
}
if (index_reg != REG_RSP) {
- scaled_index = get_reg_val(cpu, index_reg, decode->rex.x, addr_size) <<
+ scaled_index = get_reg_val(env, index_reg, decode->rex.x, addr_size) <<
decode->sib.scale;
}
return base + scaled_index;
}
-void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode,
+void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
x86_reg_segment seg = REG_SEG_DS;
@@ -1764,10 +1765,10 @@ void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode,
}
if (4 == decode->modrm.rm) {
- ptr += get_sib_val(cpu, decode, &seg);
+ ptr += get_sib_val(env, decode, &seg);
} else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
- if (x86_is_long_mode(cpu)) {
- ptr += RIP(cpu) + decode->len;
+ if (x86_is_long_mode(ENV_GET_CPU(env))) {
+ ptr += RIP(env) + decode->len;
} else {
ptr = decode->displacement;
}
@@ -1775,17 +1776,17 @@ void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode,
if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm) {
seg = REG_SEG_SS;
}
- ptr += get_reg_val(cpu, decode->modrm.rm, decode->rex.b, addr_size);
+ ptr += get_reg_val(env, decode->modrm.rm, decode->rex.b, addr_size);
}
if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = (uint32_t)ptr;
} else {
- op->ptr = decode_linear_addr(cpu, decode, (uint32_t)ptr, seg);
+ op->ptr = decode_linear_addr(env, decode, (uint32_t)ptr, seg);
}
}
-void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode,
+void calc_modrm_operand64(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
x86_reg_segment seg = REG_SEG_DS;
@@ -1800,41 +1801,41 @@ void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode,
}
if (4 == rm) {
- ptr = get_sib_val(cpu, decode, &seg) + offset;
+ ptr = get_sib_val(env, decode, &seg) + offset;
} else if (0 == mod && 5 == rm) {
- ptr = RIP(cpu) + decode->len + (int32_t) offset;
+ ptr = RIP(env) + decode->len + (int32_t) offset;
} else {
- ptr = get_reg_val(cpu, src, decode->rex.b, 8) + (int64_t) offset;
+ ptr = get_reg_val(env, src, decode->rex.b, 8) + (int64_t) offset;
}
if (X86_DECODE_CMD_LEA == decode->cmd) {
op->ptr = ptr;
} else {
- op->ptr = decode_linear_addr(cpu, decode, ptr, seg);
+ op->ptr = decode_linear_addr(env, decode, ptr, seg);
}
}
-void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode,
+void calc_modrm_operand(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op)
{
if (3 == decode->modrm.mod) {
op->reg = decode->modrm.reg;
op->type = X86_VAR_REG;
- op->ptr = get_reg_ref(cpu, decode->modrm.rm, decode->rex.b,
+ op->ptr = get_reg_ref(env, decode->modrm.rm, decode->rex.b,
decode->operand_size);
return;
}
switch (decode->addressing_size) {
case 2:
- calc_modrm_operand16(cpu, decode, op);
+ calc_modrm_operand16(env, decode, op);
break;
case 4:
- calc_modrm_operand32(cpu, decode, op);
+ calc_modrm_operand32(env, decode, op);
break;
case 8:
- calc_modrm_operand64(cpu, decode, op);
+ calc_modrm_operand64(env, decode, op);
break;
default:
VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
@@ -1842,10 +1843,10 @@ void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode,
}
}
-static void decode_prefix(CPUState *cpu, struct x86_decode *decode)
+static void decode_prefix(CPUX86State *env, struct x86_decode *decode)
{
while (1) {
- uint8_t byte = decode_byte(cpu, decode);
+ uint8_t byte = decode_byte(env, decode);
switch (byte) {
case PREFIX_LOCK:
decode->lock = byte;
@@ -1869,7 +1870,7 @@ static void decode_prefix(CPUState *cpu, struct x86_decode *decode)
decode->addr_size_override = byte;
break;
case PREFIX_REX ... (PREFIX_REX + 0xf):
- if (x86_is_long_mode(cpu)) {
+ if (x86_is_long_mode(ENV_GET_CPU(env))) {
decode->rex.rex = byte;
break;
}
@@ -1881,19 +1882,19 @@ static void decode_prefix(CPUState *cpu, struct x86_decode *decode)
}
}
-void set_addressing_size(CPUState *cpu, struct x86_decode *decode)
+void set_addressing_size(CPUX86State *env, struct x86_decode *decode)
{
decode->addressing_size = -1;
- if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
+ if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) {
if (decode->addr_size_override) {
decode->addressing_size = 4;
} else {
decode->addressing_size = 2;
}
- } else if (!x86_is_long_mode(cpu)) {
+ } else if (!x86_is_long_mode(ENV_GET_CPU(env))) {
/* protected */
struct vmx_segment cs;
- vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
+ vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, REG_SEG_CS);
/* check db */
if ((cs.ar >> 14) & 1) {
if (decode->addr_size_override) {
@@ -1918,19 +1919,19 @@ void set_addressing_size(CPUState *cpu, struct x86_decode *decode)
}
}
-void set_operand_size(CPUState *cpu, struct x86_decode *decode)
+void set_operand_size(CPUX86State *env, struct x86_decode *decode)
{
decode->operand_size = -1;
- if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
+ if (x86_is_real(ENV_GET_CPU(env)) || x86_is_v8086(ENV_GET_CPU(env))) {
if (decode->op_size_override) {
decode->operand_size = 4;
} else {
decode->operand_size = 2;
}
- } else if (!x86_is_long_mode(cpu)) {
+ } else if (!x86_is_long_mode(ENV_GET_CPU(env))) {
/* protected */
struct vmx_segment cs;
- vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
+ vmx_read_segment_descriptor(ENV_GET_CPU(env), &cs, REG_SEG_CS);
/* check db */
if ((cs.ar >> 14) & 1) {
if (decode->op_size_override) {
@@ -1959,11 +1960,11 @@ void set_operand_size(CPUState *cpu, struct x86_decode *decode)
}
}
-static void decode_sib(CPUState *cpu, struct x86_decode *decode)
+static void decode_sib(CPUX86State *env, struct x86_decode *decode)
{
if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) &&
(decode->addressing_size != 2)) {
- decode->sib.sib = decode_byte(cpu, decode);
+ decode->sib.sib = decode_byte(env, decode);
decode->sib_present = true;
}
}
@@ -1984,7 +1985,7 @@ int disp32_tbl[4][8] = {
{0, 0, 0, 0, 0, 0, 0, 0}
};
-static inline void decode_displacement(CPUState *cpu, struct x86_decode *decode)
+static inline void decode_displacement(CPUX86State *env, struct x86_decode *decode)
{
int addressing_size = decode->addressing_size;
int mod = decode->modrm.mod;
@@ -1995,7 +1996,7 @@ static inline void decode_displacement(CPUState *cpu, struct x86_decode *decode)
case 2:
decode->displacement_size = disp16_tbl[mod][rm];
if (decode->displacement_size) {
- decode->displacement = (uint16_t)decode_bytes(cpu, decode,
+ decode->displacement = (uint16_t)decode_bytes(env, decode,
decode->displacement_size);
}
break;
@@ -2010,23 +2011,23 @@ static inline void decode_displacement(CPUState *cpu, struct x86_decode *decode)
}
if (decode->displacement_size) {
- decode->displacement = (uint32_t)decode_bytes(cpu, decode,
+ decode->displacement = (uint32_t)decode_bytes(env, decode,
decode->displacement_size);
}
break;
}
}
-static inline void decode_modrm(CPUState *cpu, struct x86_decode *decode)
+static inline void decode_modrm(CPUX86State *env, struct x86_decode *decode)
{
- decode->modrm.modrm = decode_byte(cpu, decode);
+ decode->modrm.modrm = decode_byte(env, decode);
decode->is_modrm = true;
- decode_sib(cpu, decode);
- decode_displacement(cpu, decode);
+ decode_sib(env, decode);
+ decode_displacement(env, decode);
}
-static inline void decode_opcode_general(CPUState *cpu,
+static inline void decode_opcode_general(CPUX86State *env,
struct x86_decode *decode,
uint8_t opcode,
struct decode_tbl *inst_decoder)
@@ -2038,69 +2039,69 @@ static inline void decode_opcode_general(CPUState *cpu,
decode->flags_mask = inst_decoder->flags_mask;
if (inst_decoder->is_modrm) {
- decode_modrm(cpu, decode);
+ decode_modrm(env, decode);
}
if (inst_decoder->decode_op1) {
- inst_decoder->decode_op1(cpu, decode, &decode->op[0]);
+ inst_decoder->decode_op1(env, decode, &decode->op[0]);
}
if (inst_decoder->decode_op2) {
- inst_decoder->decode_op2(cpu, decode, &decode->op[1]);
+ inst_decoder->decode_op2(env, decode, &decode->op[1]);
}
if (inst_decoder->decode_op3) {
- inst_decoder->decode_op3(cpu, decode, &decode->op[2]);
+ inst_decoder->decode_op3(env, decode, &decode->op[2]);
}
if (inst_decoder->decode_op4) {
- inst_decoder->decode_op4(cpu, decode, &decode->op[3]);
+ inst_decoder->decode_op4(env, decode, &decode->op[3]);
}
if (inst_decoder->decode_postfix) {
- inst_decoder->decode_postfix(cpu, decode);
+ inst_decoder->decode_postfix(env, decode);
}
}
-static inline void decode_opcode_1(CPUState *cpu, struct x86_decode *decode,
+static inline void decode_opcode_1(CPUX86State *env, struct x86_decode *decode,
uint8_t opcode)
{
struct decode_tbl *inst_decoder = &_decode_tbl1[opcode];
- decode_opcode_general(cpu, decode, opcode, inst_decoder);
+ decode_opcode_general(env, decode, opcode, inst_decoder);
}
-static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode,
+static inline void decode_opcode_2(CPUX86State *env, struct x86_decode *decode,
uint8_t opcode)
{
struct decode_tbl *inst_decoder = &_decode_tbl2[opcode];
- decode_opcode_general(cpu, decode, opcode, inst_decoder);
+ decode_opcode_general(env, decode, opcode, inst_decoder);
}
-static void decode_opcodes(CPUState *cpu, struct x86_decode *decode)
+static void decode_opcodes(CPUX86State *env, struct x86_decode *decode)
{
uint8_t opcode;
- opcode = decode_byte(cpu, decode);
+ opcode = decode_byte(env, decode);
decode->opcode[decode->opcode_len++] = opcode;
if (opcode != OPCODE_ESCAPE) {
- decode_opcode_1(cpu, decode, opcode);
+ decode_opcode_1(env, decode, opcode);
} else {
- opcode = decode_byte(cpu, decode);
+ opcode = decode_byte(env, decode);
decode->opcode[decode->opcode_len++] = opcode;
- decode_opcode_2(cpu, decode, opcode);
+ decode_opcode_2(env, decode, opcode);
}
}
-uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode)
+uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode)
{
ZERO_INIT(*decode);
- decode_prefix(cpu, decode);
- set_addressing_size(cpu, decode);
- set_operand_size(cpu, decode);
+ decode_prefix(env, decode);
+ set_addressing_size(env, decode);
+ set_operand_size(env, decode);
- decode_opcodes(cpu, decode);
+ decode_opcodes(env, decode);
return decode->len;
}
-void init_decoder(CPUState *cpu)
+void init_decoder()
{
int i;
@@ -2156,7 +2157,7 @@ const char *decode_cmd_to_string(enum x86_decode_cmd cmd)
return cmds[cmd];
}
-addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode,
+addr_t decode_linear_addr(CPUX86State *env, struct x86_decode *decode,
addr_t addr, x86_reg_segment seg)
{
switch (decode->segment_override) {
@@ -2181,5 +2182,5 @@ addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode,
default:
break;
}
- return linear_addr_size(cpu, addr, decode->addressing_size, seg);
+ return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_size, seg);
}
diff --git a/target/i386/hvf-utils/x86_decode.h b/target/i386/hvf-utils/x86_decode.h
index b6763e1ba1..1c41cc9456 100644
--- a/target/i386/hvf-utils/x86_decode.h
+++ b/target/i386/hvf-utils/x86_decode.h
@@ -23,6 +23,7 @@
#include <stdarg.h>
#include "qemu-common.h"
#include "x86.h"
+#include "cpu.h"
typedef enum x86_prefix {
/* group 1 */
@@ -304,21 +305,21 @@ typedef struct x86_decode {
uint64_t sign(uint64_t val, int size);
-uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode);
+uint32_t decode_instruction(CPUX86State *env, struct x86_decode *decode);
-addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size);
-addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size);
-void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode,
+addr_t get_reg_ref(CPUX86State *env, int reg, int is_extended, int size);
+addr_t get_reg_val(CPUX86State *env, int reg, int is_extended, int size);
+void calc_modrm_operand(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op);
-addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode,
+addr_t decode_linear_addr(CPUX86State *env, struct x86_decode *decode,
addr_t addr, x86_reg_segment seg);
-void init_decoder(CPUState *cpu);
-void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode,
+void init_decoder(void);
+void calc_modrm_operand16(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op);
-void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode,
+void calc_modrm_operand32(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op);
-void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode,
+void calc_modrm_operand64(CPUX86State *env, struct x86_decode *decode,
struct x86_decode_op *op);
-void set_addressing_size(CPUState *cpu, struct x86_decode *decode);
-void set_operand_size(CPUState *cpu, struct x86_decode *decode);
+void set_addressing_size(CPUX86State *env, struct x86_decode *decode);
+void set_operand_size(CPUX86State *env, struct x86_decode *decode);
diff --git a/target/i386/hvf-utils/x86_emu.c b/target/i386/hvf-utils/x86_emu.c
index dc33cd2576..10eed3b606 100644
--- a/target/i386/hvf-utils/x86_emu.c
+++ b/target/i386/hvf-utils/x86_emu.c
@@ -42,15 +42,16 @@
#include "x86.h"
#include "x86_emu.h"
#include "x86_mmu.h"
+#include "x86_flags.h"
#include "vmcs.h"
#include "vmx.h"
void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
int direction, int size, uint32_t count);
-#define EXEC_2OP_LOGIC_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
+#define EXEC_2OP_LOGIC_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
{ \
- fetch_operands(cpu, decode, 2, true, true, false); \
+ fetch_operands(env, decode, 2, true, true, false); \
switch (decode->operand_size) { \
case 1: \
{ \
@@ -58,7 +59,7 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
uint8_t v2 = (uint8_t)decode->op[1].val; \
uint8_t diff = v1 cmd v2; \
if (save_res) { \
- write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
+ write_val_ext(env, decode->op[0].ptr, diff, 1); \
} \
FLAGS_FUNC##_8(diff); \
break; \
@@ -69,7 +70,7 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
uint16_t v2 = (uint16_t)decode->op[1].val; \
uint16_t diff = v1 cmd v2; \
if (save_res) { \
- write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
+ write_val_ext(env, decode->op[0].ptr, diff, 2); \
} \
FLAGS_FUNC##_16(diff); \
break; \
@@ -80,7 +81,7 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
uint32_t v2 = (uint32_t)decode->op[1].val; \
uint32_t diff = v1 cmd v2; \
if (save_res) { \
- write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
+ write_val_ext(env, decode->op[0].ptr, diff, 4); \
} \
FLAGS_FUNC##_32(diff); \
break; \
@@ -91,9 +92,9 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
} \
-#define EXEC_2OP_ARITH_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
+#define EXEC_2OP_ARITH_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \
{ \
- fetch_operands(cpu, decode, 2, true, true, false); \
+ fetch_operands(env, decode, 2, true, true, false); \
switch (decode->operand_size) { \
case 1: \
{ \
@@ -101,7 +102,7 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
uint8_t v2 = (uint8_t)decode->op[1].val; \
uint8_t diff = v1 cmd v2; \
if (save_res) { \
- write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
+ write_val_ext(env, decode->op[0].ptr, diff, 1); \
} \
FLAGS_FUNC##_8(v1, v2, diff); \
break; \
@@ -112,7 +113,7 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
uint16_t v2 = (uint16_t)decode->op[1].val; \
uint16_t diff = v1 cmd v2; \
if (save_res) { \
- write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
+ write_val_ext(env, decode->op[0].ptr, diff, 2); \
} \
FLAGS_FUNC##_16(v1, v2, diff); \
break; \
@@ -123,7 +124,7 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
uint32_t v2 = (uint32_t)decode->op[1].val; \
uint32_t diff = v1 cmd v2; \
if (save_res) { \
- write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
+ write_val_ext(env, decode->op[0].ptr, diff, 4); \
} \
FLAGS_FUNC##_32(v1, v2, diff); \
break; \
@@ -133,37 +134,37 @@ void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
} \
}
-addr_t read_reg(struct CPUState *cpu, int reg, int size)
+addr_t read_reg(CPUX86State *env, int reg, int size)
{
switch (size) {
case 1:
- return cpu->hvf_x86->regs[reg].lx;
+ return env->hvf_emul->regs[reg].lx;
case 2:
- return cpu->hvf_x86->regs[reg].rx;
+ return env->hvf_emul->regs[reg].rx;
case 4:
- return cpu->hvf_x86->regs[reg].erx;
+ return env->hvf_emul->regs[reg].erx;
case 8:
- return cpu->hvf_x86->regs[reg].rrx;
+ return env->hvf_emul->regs[reg].rrx;
default:
VM_PANIC_ON("read_reg size");
}
return 0;
}
-void write_reg(struct CPUState *cpu, int reg, addr_t val, int size)
+void write_reg(CPUX86State *env, int reg, addr_t val, int size)
{
switch (size) {
case 1:
- cpu->hvf_x86->regs[reg].lx = val;
+ env->hvf_emul->regs[reg].lx = val;
break;
case 2:
- cpu->hvf_x86->regs[reg].rx = val;
+ env->hvf_emul->regs[reg].rx = val;
break;
case 4:
- cpu->hvf_x86->regs[reg].rrx = (uint32_t)val;
+ env->hvf_emul->regs[reg].rrx = (uint32_t)val;
break;
case 8:
- cpu->hvf_x86->regs[reg].rrx = val;
+ env->hvf_emul->regs[reg].rrx = val;
break;
default:
VM_PANIC_ON("write_reg size");
@@ -215,38 +216,36 @@ void write_val_to_reg(addr_t reg_ptr, addr_t val, int size)
}
}
-static bool is_host_reg(struct CPUState *cpu, addr_t ptr)
+static bool is_host_reg(struct CPUX86State *env, addr_t ptr)
{
- return (ptr > (addr_t)cpu && ptr < (addr_t)cpu + sizeof(struct CPUState)) ||
- (ptr > (addr_t)cpu->hvf_x86 && ptr <
- (addr_t)(cpu->hvf_x86 + sizeof(struct hvf_x86_state)));
+ return (ptr - (addr_t)&env->hvf_emul->regs[0]) < sizeof(env->hvf_emul->regs);
}
-void write_val_ext(struct CPUState *cpu, addr_t ptr, addr_t val, int size)
+void write_val_ext(struct CPUX86State *env, addr_t ptr, addr_t val, int size)
{
- if (is_host_reg(cpu, ptr)) {
+ if (is_host_reg(env, ptr)) {
write_val_to_reg(ptr, val, size);
return;
}
- vmx_write_mem(cpu, ptr, &val, size);
+ vmx_write_mem(ENV_GET_CPU(env), ptr, &val, size);
}
-uint8_t *read_mmio(struct CPUState *cpu, addr_t ptr, int bytes)
+uint8_t *read_mmio(struct CPUX86State *env, addr_t ptr, int bytes)
{
- vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, ptr, bytes);
- return cpu->hvf_x86->mmio_buf;
+ vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, ptr, bytes);
+ return env->hvf_emul->mmio_buf;
}
-addr_t read_val_ext(struct CPUState *cpu, addr_t ptr, int size)
+addr_t read_val_ext(struct CPUX86State *env, addr_t ptr, int size)
{
addr_t val;
uint8_t *mmio_ptr;
- if (is_host_reg(cpu, ptr)) {
+ if (is_host_reg(env, ptr)) {
return read_val_from_reg(ptr, size);
}
- mmio_ptr = read_mmio(cpu, ptr, size);
+ mmio_ptr = read_mmio(env, ptr, size);
switch (size) {
case 1:
val = *(uint8_t *)mmio_ptr;
@@ -267,7 +266,7 @@ addr_t read_val_ext(struct CPUState *cpu, addr_t ptr, int size)
return val;
}
-static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode,
+static void fetch_operands(struct CPUX86State *env, struct x86_decode *decode,
int n, bool val_op0, bool val_op1, bool val_op2)
{
int i;
@@ -285,18 +284,18 @@ static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode,
}
break;
case X86_VAR_RM:
- calc_modrm_operand(cpu, decode, &decode->op[i]);
+ calc_modrm_operand(env, decode, &decode->op[i]);
if (calc_val[i]) {
- decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr,
+ decode->op[i].val = read_val_ext(env, decode->op[i].ptr,
decode->operand_size);
}
break;
case X86_VAR_OFFSET:
- decode->op[i].ptr = decode_linear_addr(cpu, decode,
+ decode->op[i].ptr = decode_linear_addr(env, decode,
decode->op[i].ptr,
REG_SEG_DS);
if (calc_val[i]) {
- decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr,
+ decode->op[i].val = read_val_ext(env, decode->op[i].ptr,
decode->operand_size);
}
break;
@@ -306,65 +305,65 @@ static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode,
}
}
-static void exec_mov(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_mov(struct CPUX86State *env, struct x86_decode *decode)
{
- fetch_operands(cpu, decode, 2, false, true, false);
- write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val,
+ fetch_operands(env, decode, 2, false, true, false);
+ write_val_ext(env, decode->op[0].ptr, decode->op[1].val,
decode->operand_size);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_add(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_add(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_ARITH_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true);
+ RIP(env) += decode->len;
}
-static void exec_or(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_or(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_LOGIC_CMD(cpu, decode, |, SET_FLAGS_OSZAPC_LOGIC, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_LOGIC_CMD(env, decode, |, SET_FLAGS_OSZAPC_LOGIC, true);
+ RIP(env) += decode->len;
}
-static void exec_adc(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_adc(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_ARITH_CMD(cpu, decode, +get_CF(cpu)+, SET_FLAGS_OSZAPC_ADD, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_ARITH_CMD(env, decode, +get_CF(env)+, SET_FLAGS_OSZAPC_ADD, true);
+ RIP(env) += decode->len;
}
-static void exec_sbb(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_sbb(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_ARITH_CMD(cpu, decode, -get_CF(cpu)-, SET_FLAGS_OSZAPC_SUB, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_ARITH_CMD(env, decode, -get_CF(env)-, SET_FLAGS_OSZAPC_SUB, true);
+ RIP(env) += decode->len;
}
-static void exec_and(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_and(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_LOGIC_CMD(cpu, decode, &, SET_FLAGS_OSZAPC_LOGIC, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_LOGIC_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, true);
+ RIP(env) += decode->len;
}
-static void exec_sub(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_sub(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, true);
+ RIP(env) += decode->len;
}
-static void exec_xor(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_xor(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_LOGIC_CMD(cpu, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_LOGIC_CMD(env, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true);
+ RIP(env) += decode->len;
}
-static void exec_neg(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_neg(struct CPUX86State *env, struct x86_decode *decode)
{
- /*EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/
+ /*EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);*/
int32_t val;
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
val = 0 - sign(decode->op[1].val, decode->operand_size);
- write_val_ext(cpu, decode->op[1].ptr, val, decode->operand_size);
+ write_val_ext(env, decode->op[1].ptr, val, decode->operand_size);
if (4 == decode->operand_size) {
SET_FLAGS_OSZAPC_SUB_32(0, 0 - val, val);
@@ -376,56 +375,56 @@ static void exec_neg(struct CPUState *cpu, struct x86_decode *decode)
VM_PANIC("bad op size\n");
}
- /*lflags_to_rflags(cpu);*/
- RIP(cpu) += decode->len;
+ /*lflags_to_rflags(env);*/
+ RIP(env) += decode->len;
}
-static void exec_cmp(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_cmp(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
- RIP(cpu) += decode->len;
+ EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ RIP(env) += decode->len;
}
-static void exec_inc(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_inc(struct CPUX86State *env, struct x86_decode *decode)
{
decode->op[1].type = X86_VAR_IMMEDIATE;
decode->op[1].val = 0;
- EXEC_2OP_ARITH_CMD(cpu, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
+ EXEC_2OP_ARITH_CMD(env, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_dec(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_dec(struct CPUX86State *env, struct x86_decode *decode)
{
decode->op[1].type = X86_VAR_IMMEDIATE;
decode->op[1].val = 0;
- EXEC_2OP_ARITH_CMD(cpu, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
- RIP(cpu) += decode->len;
+ EXEC_2OP_ARITH_CMD(env, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
+ RIP(env) += decode->len;
}
-static void exec_tst(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_tst(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_LOGIC_CMD(cpu, decode, &, SET_FLAGS_OSZAPC_LOGIC, false);
- RIP(cpu) += decode->len;
+ EXEC_2OP_LOGIC_CMD(env, decode, &, SET_FLAGS_OSZAPC_LOGIC, false);
+ RIP(env) += decode->len;
}
-static void exec_not(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_not(struct CPUX86State *env, struct x86_decode *decode)
{
- fetch_operands(cpu, decode, 1, true, false, false);
+ fetch_operands(env, decode, 1, true, false, false);
- write_val_ext(cpu, decode->op[0].ptr, ~decode->op[0].val,
+ write_val_ext(env, decode->op[0].ptr, ~decode->op[0].val,
decode->operand_size);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-void exec_movzx(struct CPUState *cpu, struct x86_decode *decode)
+void exec_movzx(struct CPUX86State *env, struct x86_decode *decode)
{
int src_op_size;
int op_size = decode->operand_size;
- fetch_operands(cpu, decode, 1, false, false, false);
+ fetch_operands(env, decode, 1, false, false, false);
if (0xb6 == decode->opcode[1]) {
src_op_size = 1;
@@ -433,60 +432,60 @@ void exec_movzx(struct CPUState *cpu, struct x86_decode *decode)
src_op_size = 2;
}
decode->operand_size = src_op_size;
- calc_modrm_operand(cpu, decode, &decode->op[1]);
- decode->op[1].val = read_val_ext(cpu, decode->op[1].ptr, src_op_size);
- write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
+ calc_modrm_operand(env, decode, &decode->op[1]);
+ decode->op[1].val = read_val_ext(env, decode->op[1].ptr, src_op_size);
+ write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_out(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_out(struct CPUX86State *env, struct x86_decode *decode)
{
switch (decode->opcode[0]) {
case 0xe6:
- hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 1, 1, 1);
+ hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 1, 1, 1);
break;
case 0xe7:
- hvf_handle_io(cpu, decode->op[0].val, &RAX(cpu), 1,
+ hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &RAX(env), 1,
decode->operand_size, 1);
break;
case 0xee:
- hvf_handle_io(cpu, DX(cpu), &AL(cpu), 1, 1, 1);
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 1, 1, 1);
break;
case 0xef:
- hvf_handle_io(cpu, DX(cpu), &RAX(cpu), 1, decode->operand_size, 1);
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), &RAX(env), 1, decode->operand_size, 1);
break;
default:
VM_PANIC("Bad out opcode\n");
break;
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_in(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_in(struct CPUX86State *env, struct x86_decode *decode)
{
addr_t val = 0;
switch (decode->opcode[0]) {
case 0xe4:
- hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 0, 1, 1);
+ hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &AL(env), 0, 1, 1);
break;
case 0xe5:
- hvf_handle_io(cpu, decode->op[0].val, &val, 0, decode->operand_size, 1);
+ hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &val, 0, decode->operand_size, 1);
if (decode->operand_size == 2) {
- AX(cpu) = val;
+ AX(env) = val;
} else {
- RAX(cpu) = (uint32_t)val;
+ RAX(env) = (uint32_t)val;
}
break;
case 0xec:
- hvf_handle_io(cpu, DX(cpu), &AL(cpu), 0, 1, 1);
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), &AL(env), 0, 1, 1);
break;
case 0xed:
- hvf_handle_io(cpu, DX(cpu), &val, 0, decode->operand_size, 1);
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), &val, 0, decode->operand_size, 1);
if (decode->operand_size == 2) {
- AX(cpu) = val;
+ AX(env) = val;
} else {
- RAX(cpu) = (uint32_t)val;
+ RAX(env) = (uint32_t)val;
}
break;
@@ -495,212 +494,212 @@ static void exec_in(struct CPUState *cpu, struct x86_decode *decode)
break;
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static inline void string_increment_reg(struct CPUState *cpu, int reg,
+static inline void string_increment_reg(struct CPUX86State *env, int reg,
struct x86_decode *decode)
{
- addr_t val = read_reg(cpu, reg, decode->addressing_size);
- if (cpu->hvf_x86->rflags.df) {
+ addr_t val = read_reg(env, reg, decode->addressing_size);
+ if (env->hvf_emul->rflags.df) {
val -= decode->operand_size;
} else {
val += decode->operand_size;
}
- write_reg(cpu, reg, val, decode->addressing_size);
+ write_reg(env, reg, val, decode->addressing_size);
}
-static inline void string_rep(struct CPUState *cpu, struct x86_decode *decode,
- void (*func)(struct CPUState *cpu,
+static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode,
+ void (*func)(struct CPUX86State *env,
struct x86_decode *ins), int rep)
{
- addr_t rcx = read_reg(cpu, REG_RCX, decode->addressing_size);
+ addr_t rcx = read_reg(env, REG_RCX, decode->addressing_size);
while (rcx--) {
- func(cpu, decode);
- write_reg(cpu, REG_RCX, rcx, decode->addressing_size);
- if ((PREFIX_REP == rep) && !get_ZF(cpu)) {
+ func(env, decode);
+ write_reg(env, REG_RCX, rcx, decode->addressing_size);
+ if ((PREFIX_REP == rep) && !get_ZF(env)) {
break;
}
- if ((PREFIX_REPN == rep) && get_ZF(cpu)) {
+ if ((PREFIX_REPN == rep) && get_ZF(env)) {
break;
}
}
}
-static void exec_ins_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_ins_single(struct CPUX86State *env, struct x86_decode *decode)
{
- addr_t addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size,
+ addr_t addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
REG_SEG_ES);
- hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 0,
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 0,
decode->operand_size, 1);
- vmx_write_mem(cpu, addr, cpu->hvf_x86->mmio_buf, decode->operand_size);
+ vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode->operand_size);
- string_increment_reg(cpu, REG_RDI, decode);
+ string_increment_reg(env, REG_RDI, decode);
}
-static void exec_ins(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_ins(struct CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
- string_rep(cpu, decode, exec_ins_single, 0);
+ string_rep(env, decode, exec_ins_single, 0);
} else {
- exec_ins_single(cpu, decode);
+ exec_ins_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_outs_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_outs_single(struct CPUX86State *env, struct x86_decode *decode)
{
- addr_t addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
+ addr_t addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS);
- vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, addr, decode->operand_size);
- hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 1,
+ vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->operand_size);
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), env->hvf_emul->mmio_buf, 1,
decode->operand_size, 1);
- string_increment_reg(cpu, REG_RSI, decode);
+ string_increment_reg(env, REG_RSI, decode);
}
-static void exec_outs(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_outs(struct CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
- string_rep(cpu, decode, exec_outs_single, 0);
+ string_rep(env, decode, exec_outs_single, 0);
} else {
- exec_outs_single(cpu, decode);
+ exec_outs_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_movs_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_movs_single(struct CPUX86State *env, struct x86_decode *decode)
{
addr_t src_addr;
addr_t dst_addr;
addr_t val;
- src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
- dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size,
+ src_addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS);
+ dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
REG_SEG_ES);
- val = read_val_ext(cpu, src_addr, decode->operand_size);
- write_val_ext(cpu, dst_addr, val, decode->operand_size);
+ val = read_val_ext(env, src_addr, decode->operand_size);
+ write_val_ext(env, dst_addr, val, decode->operand_size);
- string_increment_reg(cpu, REG_RSI, decode);
- string_increment_reg(cpu, REG_RDI, decode);
+ string_increment_reg(env, REG_RSI, decode);
+ string_increment_reg(env, REG_RDI, decode);
}
-static void exec_movs(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_movs(struct CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
- string_rep(cpu, decode, exec_movs_single, 0);
+ string_rep(env, decode, exec_movs_single, 0);
} else {
- exec_movs_single(cpu, decode);
+ exec_movs_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_cmps_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_cmps_single(struct CPUX86State *env, struct x86_decode *decode)
{
addr_t src_addr;
addr_t dst_addr;
- src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
- dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size,
+ src_addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS);
+ dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
REG_SEG_ES);
decode->op[0].type = X86_VAR_IMMEDIATE;
- decode->op[0].val = read_val_ext(cpu, src_addr, decode->operand_size);
+ decode->op[0].val = read_val_ext(env, src_addr, decode->operand_size);
decode->op[1].type = X86_VAR_IMMEDIATE;
- decode->op[1].val = read_val_ext(cpu, dst_addr, decode->operand_size);
+ decode->op[1].val = read_val_ext(env, dst_addr, decode->operand_size);
- EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
- string_increment_reg(cpu, REG_RSI, decode);
- string_increment_reg(cpu, REG_RDI, decode);
+ string_increment_reg(env, REG_RSI, decode);
+ string_increment_reg(env, REG_RDI, decode);
}
-static void exec_cmps(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_cmps(struct CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
- string_rep(cpu, decode, exec_cmps_single, decode->rep);
+ string_rep(env, decode, exec_cmps_single, decode->rep);
} else {
- exec_cmps_single(cpu, decode);
+ exec_cmps_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_stos_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_stos_single(struct CPUX86State *env, struct x86_decode *decode)
{
addr_t addr;
addr_t val;
- addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
- val = read_reg(cpu, REG_RAX, decode->operand_size);
- vmx_write_mem(cpu, addr, &val, decode->operand_size);
+ addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, REG_SEG_ES);
+ val = read_reg(env, REG_RAX, decode->operand_size);
+ vmx_write_mem(ENV_GET_CPU(env), addr, &val, decode->operand_size);
- string_increment_reg(cpu, REG_RDI, decode);
+ string_increment_reg(env, REG_RDI, decode);
}
-static void exec_stos(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_stos(struct CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
- string_rep(cpu, decode, exec_stos_single, 0);
+ string_rep(env, decode, exec_stos_single, 0);
} else {
- exec_stos_single(cpu, decode);
+ exec_stos_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_scas_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_scas_single(struct CPUX86State *env, struct x86_decode *decode)
{
addr_t addr;
- addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
+ addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, REG_SEG_ES);
decode->op[1].type = X86_VAR_IMMEDIATE;
- vmx_read_mem(cpu, &decode->op[1].val, addr, decode->operand_size);
+ vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->operand_size);
- EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
- string_increment_reg(cpu, REG_RDI, decode);
+ EXEC_2OP_ARITH_CMD(env, decode, -, SET_FLAGS_OSZAPC_SUB, false);
+ string_increment_reg(env, REG_RDI, decode);
}
-static void exec_scas(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_scas(struct CPUX86State *env, struct x86_decode *decode)
{
decode->op[0].type = X86_VAR_REG;
decode->op[0].reg = REG_RAX;
if (decode->rep) {
- string_rep(cpu, decode, exec_scas_single, decode->rep);
+ string_rep(env, decode, exec_scas_single, decode->rep);
} else {
- exec_scas_single(cpu, decode);
+ exec_scas_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_lods_single(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_lods_single(struct CPUX86State *env, struct x86_decode *decode)
{
addr_t addr;
addr_t val = 0;
- addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
- vmx_read_mem(cpu, &val, addr, decode->operand_size);
- write_reg(cpu, REG_RAX, val, decode->operand_size);
+ addr = decode_linear_addr(env, decode, RSI(env), REG_SEG_DS);
+ vmx_read_mem(ENV_GET_CPU(env), &val, addr, decode->operand_size);
+ write_reg(env, REG_RAX, val, decode->operand_size);
- string_increment_reg(cpu, REG_RSI, decode);
+ string_increment_reg(env, REG_RSI, decode);
}
-static void exec_lods(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
{
if (decode->rep) {
- string_rep(cpu, decode, exec_lods_single, 0);
+ string_rep(env, decode, exec_lods_single, 0);
} else {
- exec_lods_single(cpu, decode);
+ exec_lods_single(env, decode);
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
#define MSR_IA32_UCODE_REV 0x00000017
@@ -709,7 +708,7 @@ void simulate_rdmsr(struct CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
- uint32_t msr = ECX(cpu);
+ uint32_t msr = ECX(env);
uint64_t val = 0;
switch (msr) {
@@ -754,7 +753,7 @@ void simulate_rdmsr(struct CPUState *cpu)
case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7):
- val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base;
+ val = env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base;
break;
case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1):
@@ -764,14 +763,14 @@ void simulate_rdmsr(struct CPUState *cpu)
case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7):
- val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask;
+ val = env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask;
break;
case MSR_MTRRfix64K_00000:
val = env->mtrr_fixed[0];
break;
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
- val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1];
+ val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1];
break;
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
@@ -781,7 +780,7 @@ void simulate_rdmsr(struct CPUState *cpu)
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
- val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3];
+ val = env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3];
break;
case MSR_MTRRdefType:
val = env->mtrr_deftype;
@@ -792,22 +791,22 @@ void simulate_rdmsr(struct CPUState *cpu)
break;
}
- RAX(cpu) = (uint32_t)val;
- RDX(cpu) = (uint32_t)(val >> 32);
+ RAX(env) = (uint32_t)val;
+ RDX(env) = (uint32_t)(val >> 32);
}
-static void exec_rdmsr(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_rdmsr(struct CPUX86State *env, struct x86_decode *decode)
{
- simulate_rdmsr(cpu);
- RIP(cpu) += decode->len;
+ simulate_rdmsr(ENV_GET_CPU(env));
+ RIP(env) += decode->len;
}
void simulate_wrmsr(struct CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
CPUX86State *env = &x86_cpu->env;
- uint32_t msr = ECX(cpu);
- uint64_t data = ((uint64_t)EDX(cpu) << 32) | EAX(cpu);
+ uint32_t msr = ECX(env);
+ uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
switch (msr) {
case MSR_IA32_TSC:
@@ -837,7 +836,7 @@ void simulate_wrmsr(struct CPUState *cpu)
abort();
break;
case MSR_EFER:
- cpu->hvf_x86->efer.efer = data;
+ env->hvf_emul->efer.efer = data;
/*printf("new efer %llx\n", EFER(cpu));*/
wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);
if (data & EFER_NXE) {
@@ -852,7 +851,7 @@ void simulate_wrmsr(struct CPUState *cpu)
case MSR_MTRRphysBase(5):
case MSR_MTRRphysBase(6):
case MSR_MTRRphysBase(7):
- env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base = data;
+ env->mtrr_var[(ECX(env) - MSR_MTRRphysBase(0)) / 2].base = data;
break;
case MSR_MTRRphysMask(0):
case MSR_MTRRphysMask(1):
@@ -862,14 +861,14 @@ void simulate_wrmsr(struct CPUState *cpu)
case MSR_MTRRphysMask(5):
case MSR_MTRRphysMask(6):
case MSR_MTRRphysMask(7):
- env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask = data;
+ env->mtrr_var[(ECX(env) - MSR_MTRRphysMask(0)) / 2].mask = data;
break;
case MSR_MTRRfix64K_00000:
- env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix64K_00000] = data;
+ env->mtrr_fixed[ECX(env) - MSR_MTRRfix64K_00000] = data;
break;
case MSR_MTRRfix16K_80000:
case MSR_MTRRfix16K_A0000:
- env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1] = data;
+ env->mtrr_fixed[ECX(env) - MSR_MTRRfix16K_80000 + 1] = data;
break;
case MSR_MTRRfix4K_C0000:
case MSR_MTRRfix4K_C8000:
@@ -879,7 +878,7 @@ void simulate_wrmsr(struct CPUState *cpu)
case MSR_MTRRfix4K_E8000:
case MSR_MTRRfix4K_F0000:
case MSR_MTRRfix4K_F8000:
- env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3] = data;
+ env->mtrr_fixed[ECX(env) - MSR_MTRRfix4K_C0000 + 3] = data;
break;
case MSR_MTRRdefType:
env->mtrr_deftype = data;
@@ -895,17 +894,17 @@ void simulate_wrmsr(struct CPUState *cpu)
printf("write msr %llx\n", RCX(cpu));*/
}
-static void exec_wrmsr(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_wrmsr(struct CPUX86State *env, struct x86_decode *decode)
{
- simulate_wrmsr(cpu);
- RIP(cpu) += decode->len;
+ simulate_wrmsr(ENV_GET_CPU(env));
+ RIP(env) += decode->len;
}
/*
* flag:
* 0 - bt, 1 - btc, 2 - bts, 3 - btr
*/
-static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
+static void do_bt(struct CPUX86State *env, struct x86_decode *decode, int flag)
{
int32_t displacement;
uint8_t index;
@@ -914,7 +913,7 @@ static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
VM_PANIC_ON(decode->rex.rex);
- fetch_operands(cpu, decode, 2, false, true, false);
+ fetch_operands(env, decode, 2, false, true, false);
index = decode->op[1].val & mask;
if (decode->op[0].type != X86_VAR_REG) {
@@ -928,13 +927,13 @@ static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
VM_PANIC("bt 64bit\n");
}
}
- decode->op[0].val = read_val_ext(cpu, decode->op[0].ptr,
+ decode->op[0].val = read_val_ext(env, decode->op[0].ptr,
decode->operand_size);
cf = (decode->op[0].val >> index) & 0x01;
switch (flag) {
case 0:
- set_CF(cpu, cf);
+ set_CF(env, cf);
return;
case 1:
decode->op[0].val ^= (1u << index);
@@ -946,41 +945,41 @@ static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
decode->op[0].val &= ~(1u << index);
break;
}
- write_val_ext(cpu, decode->op[0].ptr, decode->op[0].val,
+ write_val_ext(env, decode->op[0].ptr, decode->op[0].val,
decode->operand_size);
- set_CF(cpu, cf);
+ set_CF(env, cf);
}
-static void exec_bt(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_bt(struct CPUX86State *env, struct x86_decode *decode)
{
- do_bt(cpu, decode, 0);
- RIP(cpu) += decode->len;
+ do_bt(env, decode, 0);
+ RIP(env) += decode->len;
}
-static void exec_btc(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_btc(struct CPUX86State *env, struct x86_decode *decode)
{
- do_bt(cpu, decode, 1);
- RIP(cpu) += decode->len;
+ do_bt(env, decode, 1);
+ RIP(env) += decode->len;
}
-static void exec_btr(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_btr(struct CPUX86State *env, struct x86_decode *decode)
{
- do_bt(cpu, decode, 3);
- RIP(cpu) += decode->len;
+ do_bt(env, decode, 3);
+ RIP(env) += decode->len;
}
-static void exec_bts(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_bts(struct CPUX86State *env, struct x86_decode *decode)
{
- do_bt(cpu, decode, 2);
- RIP(cpu) += decode->len;
+ do_bt(env, decode, 2);
+ RIP(env) += decode->len;
}
-void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
+void exec_shl(struct CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
int of = 0, cf = 0;
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
count = decode->op[1].val;
count &= 0x1f; /* count is masked to 5 bits*/
@@ -998,9 +997,9 @@ void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
of = cf ^ (res >> 7);
}
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ write_val_ext(env, decode->op[0].ptr, res, 1);
SET_FLAGS_OSZAPC_LOGIC_8(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
case 2:
@@ -1014,20 +1013,20 @@ void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
of = cf ^ (res >> 15); /* of = cf ^ result15 */
}
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ write_val_ext(env, decode->op[0].ptr, res, 2);
SET_FLAGS_OSZAPC_LOGIC_16(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
case 4:
{
uint32_t res = decode->op[0].val << count;
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ write_val_ext(env, decode->op[0].ptr, res, 4);
SET_FLAGS_OSZAPC_LOGIC_32(res);
cf = (decode->op[0].val >> (32 - count)) & 0x1;
of = cf ^ (res >> 31); /* of = cf ^ result31 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
default:
@@ -1035,16 +1034,16 @@ void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
}
exit:
- /* lflags_to_rflags(cpu); */
- RIP(cpu) += decode->len;
+ /* lflags_to_rflags(env); */
+ RIP(env) += decode->len;
}
-void exec_movsx(struct CPUState *cpu, struct x86_decode *decode)
+void exec_movsx(CPUX86State *env, struct x86_decode *decode)
{
int src_op_size;
int op_size = decode->operand_size;
- fetch_operands(cpu, decode, 2, false, false, false);
+ fetch_operands(env, decode, 2, false, false, false);
if (0xbe == decode->opcode[1]) {
src_op_size = 1;
@@ -1053,20 +1052,20 @@ void exec_movsx(struct CPUState *cpu, struct x86_decode *decode)
}
decode->operand_size = src_op_size;
- calc_modrm_operand(cpu, decode, &decode->op[1]);
- decode->op[1].val = sign(read_val_ext(cpu, decode->op[1].ptr, src_op_size),
+ calc_modrm_operand(env, decode, &decode->op[1]);
+ decode->op[1].val = sign(read_val_ext(env, decode->op[1].ptr, src_op_size),
src_op_size);
- write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
+ write_val_ext(env, decode->op[0].ptr, decode->op[1].val, op_size);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
+void exec_ror(struct CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
count = decode->op[1].val;
switch (decode->operand_size) {
@@ -1079,17 +1078,17 @@ void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
if (count & 0x18) {
bit6 = ((uint8_t)decode->op[0].val >> 6) & 1;
bit7 = ((uint8_t)decode->op[0].val >> 7) & 1;
- SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
+ SET_FLAGS_OxxxxC(env, bit6 ^ bit7, bit7);
}
} else {
count &= 0x7; /* use only bottom 3 bits */
res = ((uint8_t)decode->op[0].val >> count) |
((uint8_t)decode->op[0].val << (8 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ write_val_ext(env, decode->op[0].ptr, res, 1);
bit6 = (res >> 6) & 1;
bit7 = (res >> 7) & 1;
/* set eflags: ROR count affects the following flags: C, O */
- SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
+ SET_FLAGS_OxxxxC(env, bit6 ^ bit7, bit7);
}
break;
}
@@ -1103,18 +1102,18 @@ void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
bit14 = ((uint16_t)decode->op[0].val >> 14) & 1;
bit15 = ((uint16_t)decode->op[0].val >> 15) & 1;
/* of = result14 ^ result15 */
- SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
+ SET_FLAGS_OxxxxC(env, bit14 ^ bit15, bit15);
}
} else {
count &= 0x0f; /* use only 4 LSB's */
res = ((uint16_t)decode->op[0].val >> count) |
((uint16_t)decode->op[0].val << (16 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ write_val_ext(env, decode->op[0].ptr, res, 2);
bit14 = (res >> 14) & 1;
bit15 = (res >> 15) & 1;
/* of = result14 ^ result15 */
- SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
+ SET_FLAGS_OxxxxC(env, bit14 ^ bit15, bit15);
}
break;
}
@@ -1127,24 +1126,24 @@ void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
if (count) {
res = ((uint32_t)decode->op[0].val >> count) |
((uint32_t)decode->op[0].val << (32 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ write_val_ext(env, decode->op[0].ptr, res, 4);
bit31 = (res >> 31) & 1;
bit30 = (res >> 30) & 1;
/* of = result30 ^ result31 */
- SET_FLAGS_OxxxxC(cpu, bit30 ^ bit31, bit31);
+ SET_FLAGS_OxxxxC(env, bit30 ^ bit31, bit31);
}
break;
}
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
+void exec_rol(struct CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
count = decode->op[1].val;
switch (decode->operand_size) {
@@ -1157,20 +1156,20 @@ void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
if (count & 0x18) {
bit0 = ((uint8_t)decode->op[0].val & 1);
bit7 = ((uint8_t)decode->op[0].val >> 7);
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
+ SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0);
}
} else {
count &= 0x7; /* use only lowest 3 bits */
res = ((uint8_t)decode->op[0].val << count) |
((uint8_t)decode->op[0].val >> (8 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ write_val_ext(env, decode->op[0].ptr, res, 1);
/* set eflags:
* ROL count affects the following flags: C, O
*/
bit0 = (res & 1);
bit7 = (res >> 7);
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
+ SET_FLAGS_OxxxxC(env, bit0 ^ bit7, bit0);
}
break;
}
@@ -1184,18 +1183,18 @@ void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
bit0 = ((uint16_t)decode->op[0].val & 0x1);
bit15 = ((uint16_t)decode->op[0].val >> 15);
/* of = cf ^ result15 */
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
+ SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0);
}
} else {
count &= 0x0f; /* only use bottom 4 bits */
res = ((uint16_t)decode->op[0].val << count) |
((uint16_t)decode->op[0].val >> (16 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ write_val_ext(env, decode->op[0].ptr, res, 2);
bit0 = (res & 0x1);
bit15 = (res >> 15);
/* of = cf ^ result15 */
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
+ SET_FLAGS_OxxxxC(env, bit0 ^ bit15, bit0);
}
break;
}
@@ -1209,25 +1208,25 @@ void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
res = ((uint32_t)decode->op[0].val << count) |
((uint32_t)decode->op[0].val >> (32 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ write_val_ext(env, decode->op[0].ptr, res, 4);
bit0 = (res & 0x1);
bit31 = (res >> 31);
/* of = cf ^ result31 */
- SET_FLAGS_OxxxxC(cpu, bit0 ^ bit31, bit0);
+ SET_FLAGS_OxxxxC(env, bit0 ^ bit31, bit0);
}
break;
}
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
+void exec_rcl(struct CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
int of = 0, cf = 0;
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
count = decode->op[1].val & 0x1f;
switch (decode->operand_size) {
@@ -1241,17 +1240,17 @@ void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
}
if (1 == count) {
- res = (op1_8 << 1) | get_CF(cpu);
+ res = (op1_8 << 1) | get_CF(env);
} else {
- res = (op1_8 << count) | (get_CF(cpu) << (count - 1)) |
+ res = (op1_8 << count) | (get_CF(env) << (count - 1)) |
(op1_8 >> (9 - count));
}
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ write_val_ext(env, decode->op[0].ptr, res, 1);
cf = (op1_8 >> (8 - count)) & 0x01;
of = cf ^ (res >> 7); /* of = cf ^ result7 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
case 2:
@@ -1265,19 +1264,19 @@ void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
}
if (1 == count) {
- res = (op1_16 << 1) | get_CF(cpu);
+ res = (op1_16 << 1) | get_CF(env);
} else if (count == 16) {
- res = (get_CF(cpu) << 15) | (op1_16 >> 1);
+ res = (get_CF(env) << 15) | (op1_16 >> 1);
} else { /* 2..15 */
- res = (op1_16 << count) | (get_CF(cpu) << (count - 1)) |
+ res = (op1_16 << count) | (get_CF(env) << (count - 1)) |
(op1_16 >> (17 - count));
}
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ write_val_ext(env, decode->op[0].ptr, res, 2);
cf = (op1_16 >> (16 - count)) & 0x1;
of = cf ^ (res >> 15); /* of = cf ^ result15 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
case 4:
@@ -1290,29 +1289,29 @@ void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
}
if (1 == count) {
- res = (op1_32 << 1) | get_CF(cpu);
+ res = (op1_32 << 1) | get_CF(env);
} else {
- res = (op1_32 << count) | (get_CF(cpu) << (count - 1)) |
+ res = (op1_32 << count) | (get_CF(env) << (count - 1)) |
(op1_32 >> (33 - count));
}
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ write_val_ext(env, decode->op[0].ptr, res, 4);
cf = (op1_32 >> (32 - count)) & 0x1;
of = cf ^ (res >> 31); /* of = cf ^ result31 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
+void exec_rcr(struct CPUX86State *env, struct x86_decode *decode)
{
uint8_t count;
int of = 0, cf = 0;
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
count = decode->op[1].val & 0x1f;
switch (decode->operand_size) {
@@ -1325,14 +1324,14 @@ void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
if (!count) {
break;
}
- res = (op1_8 >> count) | (get_CF(cpu) << (8 - count)) |
+ res = (op1_8 >> count) | (get_CF(env) << (8 - count)) |
(op1_8 << (9 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 1);
+ write_val_ext(env, decode->op[0].ptr, res, 1);
cf = (op1_8 >> (count - 1)) & 0x1;
of = (((res << 1) ^ res) >> 7) & 0x1; /* of = result6 ^ result7 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
case 2:
@@ -1344,15 +1343,15 @@ void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
if (!count) {
break;
}
- res = (op1_16 >> count) | (get_CF(cpu) << (16 - count)) |
+ res = (op1_16 >> count) | (get_CF(env) << (16 - count)) |
(op1_16 << (17 - count));
- write_val_ext(cpu, decode->op[0].ptr, res, 2);
+ write_val_ext(env, decode->op[0].ptr, res, 2);
cf = (op1_16 >> (count - 1)) & 0x1;
of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; /* of = result15 ^
result14 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
case 4:
@@ -1365,47 +1364,47 @@ void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
}
if (1 == count) {
- res = (op1_32 >> 1) | (get_CF(cpu) << 31);
+ res = (op1_32 >> 1) | (get_CF(env) << 31);
} else {
- res = (op1_32 >> count) | (get_CF(cpu) << (32 - count)) |
+ res = (op1_32 >> count) | (get_CF(env) << (32 - count)) |
(op1_32 << (33 - count));
}
- write_val_ext(cpu, decode->op[0].ptr, res, 4);
+ write_val_ext(env, decode->op[0].ptr, res, 4);
cf = (op1_32 >> (count - 1)) & 0x1;
of = ((res << 1) ^ res) >> 31; /* of = result30 ^ result31 */
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
break;
}
}
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_xchg(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_xchg(struct CPUX86State *env, struct x86_decode *decode)
{
- fetch_operands(cpu, decode, 2, true, true, false);
+ fetch_operands(env, decode, 2, true, true, false);
- write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val,
+ write_val_ext(env, decode->op[0].ptr, decode->op[1].val,
decode->operand_size);
- write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val,
+ write_val_ext(env, decode->op[1].ptr, decode->op[0].val,
decode->operand_size);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
-static void exec_xadd(struct CPUState *cpu, struct x86_decode *decode)
+static void exec_xadd(struct CPUX86State *env, struct x86_decode *decode)
{
- EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
- write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val,
+ EXEC_2OP_ARITH_CMD(env, decode, +, SET_FLAGS_OSZAPC_ADD, true);
+ write_val_ext(env, decode->op[1].ptr, decode->op[0].val,
decode->operand_size);
- RIP(cpu) += decode->len;
+ RIP(env) += decode->len;
}
static struct cmd_handler {
enum x86_decode_cmd cmd;
- void (*handler)(struct CPUState *cpu, struct x86_decode *ins);
+ void (*handler)(struct CPUX86State *env, struct x86_decode *ins);
} handlers[] = {
{X86_DECODE_CMD_INVL, NULL,},
{X86_DECODE_CMD_MOV, exec_mov},
@@ -1451,7 +1450,7 @@ static struct cmd_handler {
static struct cmd_handler _cmd_handler[X86_DECODE_CMD_LAST];
-static void init_cmd_handler(CPUState *cpu)
+static void init_cmd_handler()
{
int i;
for (i = 0; i < ARRAY_SIZE(handlers); i++) {
@@ -1461,45 +1460,51 @@ static void init_cmd_handler(CPUState *cpu)
void load_regs(struct CPUState *cpu)
{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
int i = 0;
- RRX(cpu, REG_RAX) = rreg(cpu->hvf_fd, HV_X86_RAX);
- RRX(cpu, REG_RBX) = rreg(cpu->hvf_fd, HV_X86_RBX);
- RRX(cpu, REG_RCX) = rreg(cpu->hvf_fd, HV_X86_RCX);
- RRX(cpu, REG_RDX) = rreg(cpu->hvf_fd, HV_X86_RDX);
- RRX(cpu, REG_RSI) = rreg(cpu->hvf_fd, HV_X86_RSI);
- RRX(cpu, REG_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI);
- RRX(cpu, REG_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP);
- RRX(cpu, REG_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP);
+ RRX(env, REG_RAX) = rreg(cpu->hvf_fd, HV_X86_RAX);
+ RRX(env, REG_RBX) = rreg(cpu->hvf_fd, HV_X86_RBX);
+ RRX(env, REG_RCX) = rreg(cpu->hvf_fd, HV_X86_RCX);
+ RRX(env, REG_RDX) = rreg(cpu->hvf_fd, HV_X86_RDX);
+ RRX(env, REG_RSI) = rreg(cpu->hvf_fd, HV_X86_RSI);
+ RRX(env, REG_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI);
+ RRX(env, REG_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP);
+ RRX(env, REG_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP);
for (i = 8; i < 16; i++) {
- RRX(cpu, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
+ RRX(env, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
}
- RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
- rflags_to_lflags(cpu);
- RIP(cpu) = rreg(cpu->hvf_fd, HV_X86_RIP);
+ RFLAGS(env) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
+ rflags_to_lflags(env);
+ RIP(env) = rreg(cpu->hvf_fd, HV_X86_RIP);
}
void store_regs(struct CPUState *cpu)
{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
int i = 0;
- wreg(cpu->hvf_fd, HV_X86_RAX, RAX(cpu));
- wreg(cpu->hvf_fd, HV_X86_RBX, RBX(cpu));
- wreg(cpu->hvf_fd, HV_X86_RCX, RCX(cpu));
- wreg(cpu->hvf_fd, HV_X86_RDX, RDX(cpu));
- wreg(cpu->hvf_fd, HV_X86_RSI, RSI(cpu));
- wreg(cpu->hvf_fd, HV_X86_RDI, RDI(cpu));
- wreg(cpu->hvf_fd, HV_X86_RBP, RBP(cpu));
- wreg(cpu->hvf_fd, HV_X86_RSP, RSP(cpu));
+ wreg(cpu->hvf_fd, HV_X86_RAX, RAX(env));
+ wreg(cpu->hvf_fd, HV_X86_RBX, RBX(env));
+ wreg(cpu->hvf_fd, HV_X86_RCX, RCX(env));
+ wreg(cpu->hvf_fd, HV_X86_RDX, RDX(env));
+ wreg(cpu->hvf_fd, HV_X86_RSI, RSI(env));
+ wreg(cpu->hvf_fd, HV_X86_RDI, RDI(env));
+ wreg(cpu->hvf_fd, HV_X86_RBP, RBP(env));
+ wreg(cpu->hvf_fd, HV_X86_RSP, RSP(env));
for (i = 8; i < 16; i++) {
- wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(cpu, i));
+ wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(env, i));
}
- lflags_to_rflags(cpu);
- wreg(cpu->hvf_fd, HV_X86_RFLAGS, RFLAGS(cpu));
- macvm_set_rip(cpu, RIP(cpu));
+ lflags_to_rflags(env);
+ wreg(cpu->hvf_fd, HV_X86_RFLAGS, RFLAGS(env));
+ macvm_set_rip(cpu, RIP(env));
}
-bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins)
+bool exec_instruction(struct CPUX86State *env, struct x86_decode *ins)
{
/*if (hvf_vcpu_id(cpu))
printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu),
@@ -1509,23 +1514,23 @@ bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins)
VM_PANIC("emulate fpu\n");
} else {
if (!_cmd_handler[ins->cmd].handler) {
- printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu),
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env),
ins->cmd, ins->opcode[0],
ins->opcode_len > 1 ? ins->opcode[1] : 0);
- RIP(cpu) += ins->len;
+ RIP(env) += ins->len;
return true;
}
VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler,
- "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu),
+ "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env),
ins->cmd, ins->opcode[0],
ins->opcode_len > 1 ? ins->opcode[1] : 0);
- _cmd_handler[ins->cmd].handler(cpu, ins);
+ _cmd_handler[ins->cmd].handler(env, ins);
}
return true;
}
-void init_emu(struct CPUState *cpu)
+void init_emu()
{
- init_cmd_handler(cpu);
+ init_cmd_handler();
}
diff --git a/target/i386/hvf-utils/x86_emu.h b/target/i386/hvf-utils/x86_emu.h
index f7a739bb0a..27d1f5b4d4 100644
--- a/target/i386/hvf-utils/x86_emu.h
+++ b/target/i386/hvf-utils/x86_emu.h
@@ -3,9 +3,10 @@
#include "x86.h"
#include "x86_decode.h"
+#include "cpu.h"
-void init_emu(struct CPUState *cpu);
-bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins);
+void init_emu(void);
+bool exec_instruction(struct CPUX86State *env, struct x86_decode *ins);
void load_regs(struct CPUState *cpu);
void store_regs(struct CPUState *cpu);
@@ -13,19 +14,19 @@ void store_regs(struct CPUState *cpu);
void simulate_rdmsr(struct CPUState *cpu);
void simulate_wrmsr(struct CPUState *cpu);
-addr_t read_reg(struct CPUState *cpu, int reg, int size);
-void write_reg(struct CPUState *cpu, int reg, addr_t val, int size);
+addr_t read_reg(CPUX86State *env, int reg, int size);
+void write_reg(CPUX86State *env, int reg, addr_t val, int size);
addr_t read_val_from_reg(addr_t reg_ptr, int size);
void write_val_to_reg(addr_t reg_ptr, addr_t val, int size);
-void write_val_ext(struct CPUState *cpu, addr_t ptr, addr_t val, int size);
-uint8_t *read_mmio(struct CPUState *cpu, addr_t ptr, int bytes);
-addr_t read_val_ext(struct CPUState *cpu, addr_t ptr, int size);
+void write_val_ext(struct CPUX86State *env, addr_t ptr, addr_t val, int size);
+uint8_t *read_mmio(struct CPUX86State *env, addr_t ptr, int bytes);
+addr_t read_val_ext(struct CPUX86State *env, addr_t ptr, int size);
-void exec_movzx(struct CPUState *cpu, struct x86_decode *decode);
-void exec_shl(struct CPUState *cpu, struct x86_decode *decode);
-void exec_movsx(struct CPUState *cpu, struct x86_decode *decode);
-void exec_ror(struct CPUState *cpu, struct x86_decode *decode);
-void exec_rol(struct CPUState *cpu, struct x86_decode *decode);
-void exec_rcl(struct CPUState *cpu, struct x86_decode *decode);
-void exec_rcr(struct CPUState *cpu, struct x86_decode *decode);
+void exec_movzx(struct CPUX86State *env, struct x86_decode *decode);
+void exec_shl(struct CPUX86State *env, struct x86_decode *decode);
+void exec_movsx(struct CPUX86State *env, struct x86_decode *decode);
+void exec_ror(struct CPUX86State *env, struct x86_decode *decode);
+void exec_rol(struct CPUX86State *env, struct x86_decode *decode);
+void exec_rcl(struct CPUX86State *env, struct x86_decode *decode);
+void exec_rcr(struct CPUX86State *env, struct x86_decode *decode);
#endif
diff --git a/target/i386/hvf-utils/x86_flags.c b/target/i386/hvf-utils/x86_flags.c
index 187ab9b56b..c833774485 100644
--- a/target/i386/hvf-utils/x86_flags.c
+++ b/target/i386/hvf-utils/x86_flags.c
@@ -28,155 +28,155 @@
#include "x86_flags.h"
#include "x86.h"
-void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf)
+void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf)
{
uint32_t temp_po = new_of ^ new_cf;
- cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PO | LF_MASK_CF);
- cpu->hvf_x86->lflags.auxbits |= (temp_po << LF_BIT_PO) |
+ env->hvf_emul->lflags.auxbits &= ~(LF_MASK_PO | LF_MASK_CF);
+ env->hvf_emul->lflags.auxbits |= (temp_po << LF_BIT_PO) |
(new_cf << LF_BIT_CF);
}
-void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff)
{
SET_FLAGS_OSZAPC_SUB_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAPC_SUB16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff)
{
SET_FLAGS_OSZAPC_SUB_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAPC_SUB8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff)
{
SET_FLAGS_OSZAPC_SUB_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAPC_ADD32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff)
{
SET_FLAGS_OSZAPC_ADD_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAPC_ADD16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff)
{
SET_FLAGS_OSZAPC_ADD_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAPC_ADD8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff)
{
SET_FLAGS_OSZAPC_ADD_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAP_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff)
{
SET_FLAGS_OSZAP_SUB_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAP_SUB16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff)
{
SET_FLAGS_OSZAP_SUB_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAP_SUB8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff)
{
SET_FLAGS_OSZAP_SUB_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAP_ADD32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff)
{
SET_FLAGS_OSZAP_ADD_32(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAP_ADD16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff)
{
SET_FLAGS_OSZAP_ADD_16(v1, v2, diff);
}
-void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAP_ADD8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff)
{
SET_FLAGS_OSZAP_ADD_8(v1, v2, diff);
}
-void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff)
+void SET_FLAGS_OSZAPC_LOGIC32(CPUX86State *env, uint32_t diff)
{
SET_FLAGS_OSZAPC_LOGIC_32(diff);
}
-void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff)
+void SET_FLAGS_OSZAPC_LOGIC16(CPUX86State *env, uint16_t diff)
{
SET_FLAGS_OSZAPC_LOGIC_16(diff);
}
-void SET_FLAGS_OSZAPC_LOGIC8(struct CPUState *cpu, uint8_t diff)
+void SET_FLAGS_OSZAPC_LOGIC8(CPUX86State *env, uint8_t diff)
{
SET_FLAGS_OSZAPC_LOGIC_8(diff);
}
-void SET_FLAGS_SHR32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
+void SET_FLAGS_SHR32(CPUX86State *env, uint32_t v, int count, uint32_t res)
{
int cf = (v >> (count - 1)) & 0x1;
int of = (((res << 1) ^ res) >> 31);
SET_FLAGS_OSZAPC_LOGIC_32(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
}
-void SET_FLAGS_SHR16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
+void SET_FLAGS_SHR16(CPUX86State *env, uint16_t v, int count, uint16_t res)
{
int cf = (v >> (count - 1)) & 0x1;
int of = (((res << 1) ^ res) >> 15);
SET_FLAGS_OSZAPC_LOGIC_16(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
}
-void SET_FLAGS_SHR8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
+void SET_FLAGS_SHR8(CPUX86State *env, uint8_t v, int count, uint8_t res)
{
int cf = (v >> (count - 1)) & 0x1;
int of = (((res << 1) ^ res) >> 7);
SET_FLAGS_OSZAPC_LOGIC_8(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
}
-void SET_FLAGS_SAR32(struct CPUState *cpu, int32_t v, int count, uint32_t res)
+void SET_FLAGS_SAR32(CPUX86State *env, int32_t v, int count, uint32_t res)
{
int cf = (v >> (count - 1)) & 0x1;
SET_FLAGS_OSZAPC_LOGIC_32(res);
- SET_FLAGS_OxxxxC(cpu, 0, cf);
+ SET_FLAGS_OxxxxC(env, 0, cf);
}
-void SET_FLAGS_SAR16(struct CPUState *cpu, int16_t v, int count, uint16_t res)
+void SET_FLAGS_SAR16(CPUX86State *env, int16_t v, int count, uint16_t res)
{
int cf = (v >> (count - 1)) & 0x1;
SET_FLAGS_OSZAPC_LOGIC_16(res);
- SET_FLAGS_OxxxxC(cpu, 0, cf);
+ SET_FLAGS_OxxxxC(env, 0, cf);
}
-void SET_FLAGS_SAR8(struct CPUState *cpu, int8_t v, int count, uint8_t res)
+void SET_FLAGS_SAR8(CPUX86State *env, int8_t v, int count, uint8_t res)
{
int cf = (v >> (count - 1)) & 0x1;
SET_FLAGS_OSZAPC_LOGIC_8(res);
- SET_FLAGS_OxxxxC(cpu, 0, cf);
+ SET_FLAGS_OxxxxC(env, 0, cf);
}
-void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
+void SET_FLAGS_SHL32(CPUX86State *env, uint32_t v, int count, uint32_t res)
{
int of, cf;
@@ -184,10 +184,10 @@ void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
of = cf ^ (res >> 31);
SET_FLAGS_OSZAPC_LOGIC_32(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
}
-void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
+void SET_FLAGS_SHL16(CPUX86State *env, uint16_t v, int count, uint16_t res)
{
int of = 0, cf = 0;
@@ -197,10 +197,10 @@ void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
}
SET_FLAGS_OSZAPC_LOGIC_16(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
}
-void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
+void SET_FLAGS_SHL8(CPUX86State *env, uint8_t v, int count, uint8_t res)
{
int of = 0, cf = 0;
@@ -210,124 +210,124 @@ void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
}
SET_FLAGS_OSZAPC_LOGIC_8(res);
- SET_FLAGS_OxxxxC(cpu, of, cf);
+ SET_FLAGS_OxxxxC(env, of, cf);
}
-bool get_PF(struct CPUState *cpu)
+bool get_PF(CPUX86State *env)
{
- uint32_t temp = (255 & cpu->hvf_x86->lflags.result);
- temp = temp ^ (255 & (cpu->hvf_x86->lflags.auxbits >> LF_BIT_PDB));
+ uint32_t temp = (255 & env->hvf_emul->lflags.result);
+ temp = temp ^ (255 & (env->hvf_emul->lflags.auxbits >> LF_BIT_PDB));
temp = (temp ^ (temp >> 4)) & 0x0F;
return (0x9669U >> temp) & 1;
}
-void set_PF(struct CPUState *cpu, bool val)
+void set_PF(CPUX86State *env, bool val)
{
- uint32_t temp = (255 & cpu->hvf_x86->lflags.result) ^ (!val);
- cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PDB);
- cpu->hvf_x86->lflags.auxbits |= (temp << LF_BIT_PDB);
+ uint32_t temp = (255 & env->hvf_emul->lflags.result) ^ (!val);
+ env->hvf_emul->lflags.auxbits &= ~(LF_MASK_PDB);
+ env->hvf_emul->lflags.auxbits |= (temp << LF_BIT_PDB);
}
-bool _get_OF(struct CPUState *cpu)
+bool _get_OF(CPUX86State *env)
{
- return ((cpu->hvf_x86->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
+ return ((env->hvf_emul->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
}
-bool get_OF(struct CPUState *cpu)
+bool get_OF(CPUX86State *env)
{
- return _get_OF(cpu);
+ return _get_OF(env);
}
-bool _get_CF(struct CPUState *cpu)
+bool _get_CF(CPUX86State *env)
{
- return (cpu->hvf_x86->lflags.auxbits >> LF_BIT_CF) & 1;
+ return (env->hvf_emul->lflags.auxbits >> LF_BIT_CF) & 1;
}
-bool get_CF(struct CPUState *cpu)
+bool get_CF(CPUX86State *env)
{
- return _get_CF(cpu);
+ return _get_CF(env);
}
-void set_OF(struct CPUState *cpu, bool val)
+void set_OF(CPUX86State *env, bool val)
{
- SET_FLAGS_OxxxxC(cpu, val, _get_CF(cpu));
+ SET_FLAGS_OxxxxC(env, val, _get_CF(env));
}
-void set_CF(struct CPUState *cpu, bool val)
+void set_CF(CPUX86State *env, bool val)
{
- SET_FLAGS_OxxxxC(cpu, _get_OF(cpu), (val));
+ SET_FLAGS_OxxxxC(env, _get_OF(env), (val));
}
-bool get_AF(struct CPUState *cpu)
+bool get_AF(CPUX86State *env)
{
- return (cpu->hvf_x86->lflags.auxbits >> LF_BIT_AF) & 1;
+ return (env->hvf_emul->lflags.auxbits >> LF_BIT_AF) & 1;
}
-void set_AF(struct CPUState *cpu, bool val)
+void set_AF(CPUX86State *env, bool val)
{
- cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_AF);
- cpu->hvf_x86->lflags.auxbits |= (val) << LF_BIT_AF;
+ env->hvf_emul->lflags.auxbits &= ~(LF_MASK_AF);
+ env->hvf_emul->lflags.auxbits |= (val) << LF_BIT_AF;
}
-bool get_ZF(struct CPUState *cpu)
+bool get_ZF(CPUX86State *env)
{
- return !cpu->hvf_x86->lflags.result;
+ return !env->hvf_emul->lflags.result;
}
-void set_ZF(struct CPUState *cpu, bool val)
+void set_ZF(CPUX86State *env, bool val)
{
if (val) {
- cpu->hvf_x86->lflags.auxbits ^=
- (((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
+ env->hvf_emul->lflags.auxbits ^=
+ (((env->hvf_emul->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
/* merge the parity bits into the Parity Delta Byte */
- uint32_t temp_pdb = (255 & cpu->hvf_x86->lflags.result);
- cpu->hvf_x86->lflags.auxbits ^= (temp_pdb << LF_BIT_PDB);
+ uint32_t temp_pdb = (255 & env->hvf_emul->lflags.result);
+ env->hvf_emul->lflags.auxbits ^= (temp_pdb << LF_BIT_PDB);
/* now zero the .result value */
- cpu->hvf_x86->lflags.result = 0;
+ env->hvf_emul->lflags.result = 0;
} else {
- cpu->hvf_x86->lflags.result |= (1 << 8);
+ env->hvf_emul->lflags.result |= (1 << 8);
}
}
-bool get_SF(struct CPUState *cpu)
+bool get_SF(CPUX86State *env)
{
- return ((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) ^
- (cpu->hvf_x86->lflags.auxbits >> LF_BIT_SD)) & 1;
+ return ((env->hvf_emul->lflags.result >> LF_SIGN_BIT) ^
+ (env->hvf_emul->lflags.auxbits >> LF_BIT_SD)) & 1;
}
-void set_SF(struct CPUState *cpu, bool val)
+void set_SF(CPUX86State *env, bool val)
{
- bool temp_sf = get_SF(cpu);
- cpu->hvf_x86->lflags.auxbits ^= (temp_sf ^ val) << LF_BIT_SD;
+ bool temp_sf = get_SF(env);
+ env->hvf_emul->lflags.auxbits ^= (temp_sf ^ val) << LF_BIT_SD;
}
-void set_OSZAPC(struct CPUState *cpu, uint32_t flags32)
+void set_OSZAPC(CPUX86State *env, uint32_t flags32)
{
- set_OF(cpu, cpu->hvf_x86->rflags.of);
- set_SF(cpu, cpu->hvf_x86->rflags.sf);
- set_ZF(cpu, cpu->hvf_x86->rflags.zf);
- set_AF(cpu, cpu->hvf_x86->rflags.af);
- set_PF(cpu, cpu->hvf_x86->rflags.pf);
- set_CF(cpu, cpu->hvf_x86->rflags.cf);
+ set_OF(env, env->hvf_emul->rflags.of);
+ set_SF(env, env->hvf_emul->rflags.sf);
+ set_ZF(env, env->hvf_emul->rflags.zf);
+ set_AF(env, env->hvf_emul->rflags.af);
+ set_PF(env, env->hvf_emul->rflags.pf);
+ set_CF(env, env->hvf_emul->rflags.cf);
}
-void lflags_to_rflags(struct CPUState *cpu)
+void lflags_to_rflags(CPUX86State *env)
{
- cpu->hvf_x86->rflags.cf = get_CF(cpu);
- cpu->hvf_x86->rflags.pf = get_PF(cpu);
- cpu->hvf_x86->rflags.af = get_AF(cpu);
- cpu->hvf_x86->rflags.zf = get_ZF(cpu);
- cpu->hvf_x86->rflags.sf = get_SF(cpu);
- cpu->hvf_x86->rflags.of = get_OF(cpu);
+ env->hvf_emul->rflags.cf = get_CF(env);
+ env->hvf_emul->rflags.pf = get_PF(env);
+ env->hvf_emul->rflags.af = get_AF(env);
+ env->hvf_emul->rflags.zf = get_ZF(env);
+ env->hvf_emul->rflags.sf = get_SF(env);
+ env->hvf_emul->rflags.of = get_OF(env);
}
-void rflags_to_lflags(struct CPUState *cpu)
+void rflags_to_lflags(CPUX86State *env)
{
- cpu->hvf_x86->lflags.auxbits = cpu->hvf_x86->lflags.result = 0;
- set_OF(cpu, cpu->hvf_x86->rflags.of);
- set_SF(cpu, cpu->hvf_x86->rflags.sf);
- set_ZF(cpu, cpu->hvf_x86->rflags.zf);
- set_AF(cpu, cpu->hvf_x86->rflags.af);
- set_PF(cpu, cpu->hvf_x86->rflags.pf);
- set_CF(cpu, cpu->hvf_x86->rflags.cf);
+ env->hvf_emul->lflags.auxbits = env->hvf_emul->lflags.result = 0;
+ set_OF(env, env->hvf_emul->rflags.of);
+ set_SF(env, env->hvf_emul->rflags.sf);
+ set_ZF(env, env->hvf_emul->rflags.zf);
+ set_AF(env, env->hvf_emul->rflags.af);
+ set_PF(env, env->hvf_emul->rflags.pf);
+ set_CF(env, env->hvf_emul->rflags.cf);
}
diff --git a/target/i386/hvf-utils/x86_flags.h b/target/i386/hvf-utils/x86_flags.h
index 68a0c10b90..57a524240c 100644
--- a/target/i386/hvf-utils/x86_flags.h
+++ b/target/i386/hvf-utils/x86_flags.h
@@ -24,14 +24,10 @@
#define __X86_FLAGS_H__
#include "x86_gen.h"
+#include "cpu.h"
/* this is basically bocsh code */
-typedef struct lazy_flags {
- addr_t result;
- addr_t auxbits;
-} lazy_flags;
-
#define LF_SIGN_BIT 31
#define LF_BIT_SD (0) /* lazy Sign Flag Delta */
@@ -63,7 +59,7 @@ typedef struct lazy_flags {
#define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \
addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
(((lf_carries) >> (size - 2)) << LF_BIT_PO); \
- cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
+ env->hvf_emul->lflags.result = (addr_t)(int##size##_t)(lf_result); \
if ((size) == 32) { \
temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
} else if ((size) == 16) { \
@@ -73,7 +69,7 @@ typedef struct lazy_flags {
} else { \
VM_PANIC("unimplemented"); \
} \
- cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)temp; \
+ env->hvf_emul->lflags.auxbits = (addr_t)(uint32_t)temp; \
}
/* carries, result */
@@ -135,10 +131,10 @@ typedef struct lazy_flags {
} else { \
VM_PANIC("unimplemented"); \
} \
- cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
- addr_t delta_c = (cpu->hvf_x86->lflags.auxbits ^ temp) & LF_MASK_CF; \
+ env->hvf_emul->lflags.result = (addr_t)(int##size##_t)(lf_result); \
+ addr_t delta_c = (env->hvf_emul->lflags.auxbits ^ temp) & LF_MASK_CF; \
delta_c ^= (delta_c >> 1); \
- cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)(temp ^ delta_c); \
+ env->hvf_emul->lflags.auxbits = (addr_t)(uint32_t)(temp ^ delta_c); \
}
/* carries, result */
@@ -179,69 +175,69 @@ typedef struct lazy_flags {
#define SET_FLAGS_OSZAxC_LOGIC_32(result_32) \
SET_FLAGS_OSZAxC_LOGIC_SIZE(32, (result_32))
-void lflags_to_rflags(struct CPUState *cpu);
-void rflags_to_lflags(struct CPUState *cpu);
-
-bool get_PF(struct CPUState *cpu);
-void set_PF(struct CPUState *cpu, bool val);
-bool get_CF(struct CPUState *cpu);
-void set_CF(struct CPUState *cpu, bool val);
-bool get_AF(struct CPUState *cpu);
-void set_AF(struct CPUState *cpu, bool val);
-bool get_ZF(struct CPUState *cpu);
-void set_ZF(struct CPUState *cpu, bool val);
-bool get_SF(struct CPUState *cpu);
-void set_SF(struct CPUState *cpu, bool val);
-bool get_OF(struct CPUState *cpu);
-void set_OF(struct CPUState *cpu, bool val);
-void set_OSZAPC(struct CPUState *cpu, uint32_t flags32);
-
-void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf);
-
-void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void lflags_to_rflags(CPUX86State *env);
+void rflags_to_lflags(CPUX86State *env);
+
+bool get_PF(CPUX86State *env);
+void set_PF(CPUX86State *env, bool val);
+bool get_CF(CPUX86State *env);
+void set_CF(CPUX86State *env, bool val);
+bool get_AF(CPUX86State *env);
+void set_AF(CPUX86State *env, bool val);
+bool get_ZF(CPUX86State *env);
+void set_ZF(CPUX86State *env, bool val);
+bool get_SF(CPUX86State *env);
+void set_SF(CPUX86State *env, bool val);
+bool get_OF(CPUX86State *env);
+void set_OF(CPUX86State *env, bool val);
+void set_OSZAPC(CPUX86State *env, uint32_t flags32);
+
+void SET_FLAGS_OxxxxC(CPUX86State *env, uint32_t new_of, uint32_t new_cf);
+
+void SET_FLAGS_OSZAPC_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff);
-void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAPC_SUB16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff);
-void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAPC_SUB8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff);
-void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAPC_ADD32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff);
-void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAPC_ADD16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff);
-void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAPC_ADD8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff);
-void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAP_SUB32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff);
-void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAP_SUB16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff);
-void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAP_SUB8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff);
-void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2,
+void SET_FLAGS_OSZAP_ADD32(CPUX86State *env, uint32_t v1, uint32_t v2,
uint32_t diff);
-void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2,
+void SET_FLAGS_OSZAP_ADD16(CPUX86State *env, uint16_t v1, uint16_t v2,
uint16_t diff);
-void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2,
+void SET_FLAGS_OSZAP_ADD8(CPUX86State *env, uint8_t v1, uint8_t v2,
uint8_t diff);
-void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff);
-void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff);
-void SET_FLAGS_OSZAPC_LOGIC8(struct CPUState *cpu, uint8_t diff);
+void SET_FLAGS_OSZAPC_LOGIC32(CPUX86State *env, uint32_t diff);
+void SET_FLAGS_OSZAPC_LOGIC16(CPUX86State *env, uint16_t diff);
+void SET_FLAGS_OSZAPC_LOGIC8(CPUX86State *env, uint8_t diff);
-void SET_FLAGS_SHR32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
-void SET_FLAGS_SHR16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
-void SET_FLAGS_SHR8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
+void SET_FLAGS_SHR32(CPUX86State *env, uint32_t v, int count, uint32_t res);
+void SET_FLAGS_SHR16(CPUX86State *env, uint16_t v, int count, uint16_t res);
+void SET_FLAGS_SHR8(CPUX86State *env, uint8_t v, int count, uint8_t res);
-void SET_FLAGS_SAR32(struct CPUState *cpu, int32_t v, int count, uint32_t res);
-void SET_FLAGS_SAR16(struct CPUState *cpu, int16_t v, int count, uint16_t res);
-void SET_FLAGS_SAR8(struct CPUState *cpu, int8_t v, int count, uint8_t res);
+void SET_FLAGS_SAR32(CPUX86State *env, int32_t v, int count, uint32_t res);
+void SET_FLAGS_SAR16(CPUX86State *env, int16_t v, int count, uint16_t res);
+void SET_FLAGS_SAR8(CPUX86State *env, int8_t v, int count, uint8_t res);
-void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
-void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
-void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
+void SET_FLAGS_SHL32(CPUX86State *env, uint32_t v, int count, uint32_t res);
+void SET_FLAGS_SHL16(CPUX86State *env, uint16_t v, int count, uint16_t res);
+void SET_FLAGS_SHL8(CPUX86State *env, uint8_t v, int count, uint8_t res);
-bool _get_OF(struct CPUState *cpu);
-bool _get_CF(struct CPUState *cpu);
+bool _get_OF(CPUX86State *env);
+bool _get_CF(CPUX86State *env);
#endif /* __X86_FLAGS_H__ */
diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c
index 819d760624..8986b4e5e5 100644
--- a/target/i386/hvf-utils/x86hvf.c
+++ b/target/i386/hvf-utils/x86hvf.c
@@ -356,9 +356,10 @@ void vmx_clear_int_window_exiting(CPUState *cpu)
void hvf_inject_interrupts(CPUState *cpu_state)
{
- X86CPU *x86cpu = X86_CPU(cpu_state);
int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
- VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
+ VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
+ X86CPU *x86cpu = X86_CPU(cpu_state);
+ CPUX86State *env = &x86cpu->env;
uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);
uint64_t info = 0;
@@ -415,9 +416,9 @@ void hvf_inject_interrupts(CPUState *cpu_state)
}
}
- if (cpu_state->hvf_x86->interruptable &&
+ if (env->hvf_emul->interruptable &&
(cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
- (EFLAGS(cpu_state) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
+ (EFLAGS(env) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
int line = cpu_get_pic_interrupt(&x86cpu->env);
cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
if (line >= 0) {
@@ -435,7 +436,7 @@ int hvf_process_events(CPUState *cpu_state)
X86CPU *cpu = X86_CPU(cpu_state);
CPUX86State *env = &cpu->env;
- EFLAGS(cpu_state) = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
+ EFLAGS(env) = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
hvf_cpu_synchronize_state(cpu_state);
@@ -447,7 +448,7 @@ int hvf_process_events(CPUState *cpu_state)
apic_poll_irq(cpu->apic_state);
}
if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
- (EFLAGS(cpu_state) & IF_MASK)) ||
+ (EFLAGS(env) & IF_MASK)) ||
(cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) {
cpu_state->halted = 0;
}
@@ -463,4 +464,3 @@ int hvf_process_events(CPUState *cpu_state)
}
return cpu_state->halted;
}
-
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 13/14] hvf: refactor event injection code for hvf
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (11 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 12/14] hvf: move fields from CPUState to CPUX86State Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 14/14] hvf: inject General Protection Fault when vmexit through vmcall Sergio Andres Gomez Del Real
` (3 subsequent siblings)
16 siblings, 0 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit refactors the event-injection code for hvf through using the
appropriate fields already provided by CPUX86State. At vmexit, it fills
these fields so that hvf_inject_interrupts can just retrieve them without
calling into hvf.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
target/i386/cpu.c | 3 ++
target/i386/hvf-all.c | 57 ++++++++++++++++++++++++++++++++++----
target/i386/hvf-utils/vmcs.h | 3 ++
target/i386/hvf-utils/vmx.h | 8 ++++++
target/i386/hvf-utils/x86hvf.c | 63 ++++++++++++++++++++----------------------
target/i386/kvm.c | 2 --
6 files changed, 96 insertions(+), 40 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8c531a0ffa..7d2080d023 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3275,6 +3275,9 @@ static void x86_cpu_reset(CPUState *s)
memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
+ env->interrupt_injected = -1;
+ env->exception_injected = -1;
+ env->nmi_injected = false;
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
index 8a75723dcf..25e4fd4eb2 100644
--- a/target/i386/hvf-all.c
+++ b/target/i386/hvf-all.c
@@ -750,6 +750,55 @@ void hvf_disable(int shouldDisable)
hvf_disabled = shouldDisable;
}
+static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info)
+{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
+ env->exception_injected = -1;
+ env->interrupt_injected = -1;
+ env->nmi_injected = false;
+ if (idtvec_info & VMCS_IDT_VEC_VALID) {
+ switch (idtvec_info & VMCS_IDT_VEC_TYPE) {
+ case VMCS_IDT_VEC_HWINTR:
+ case VMCS_IDT_VEC_SWINTR:
+ env->interrupt_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;
+ break;
+ case VMCS_IDT_VEC_NMI:
+ env->nmi_injected = true;
+ break;
+ case VMCS_IDT_VEC_HWEXCEPTION:
+ case VMCS_IDT_VEC_SWEXCEPTION:
+ env->exception_injected = idtvec_info & VMCS_IDT_VEC_VECNUM;
+ break;
+ case VMCS_IDT_VEC_PRIV_SWEXCEPTION:
+ default:
+ abort();
+ }
+ if ((idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWEXCEPTION ||
+ (idtvec_info & VMCS_IDT_VEC_TYPE) == VMCS_IDT_VEC_SWINTR) {
+ env->ins_len = ins_len;
+ }
+ if (idtvec_info & VMCS_INTR_DEL_ERRCODE) {
+ env->has_error_code = true;
+ env->error_code = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_ERROR);
+ }
+ }
+ if ((rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
+ VMCS_INTERRUPTIBILITY_NMI_BLOCKING)) {
+ env->hflags2 |= HF2_NMI_MASK;
+ } else {
+ env->hflags2 &= ~HF2_NMI_MASK;
+ }
+ if (rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
+ (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
+ VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING)) {
+ env->hflags |= HF_INHIBIT_IRQ_MASK;
+ } else {
+ env->hflags &= ~HF_INHIBIT_IRQ_MASK;
+ }
+}
+
int hvf_vcpu_exec(CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
@@ -769,11 +818,6 @@ int hvf_vcpu_exec(CPUState *cpu)
cpu->vcpu_dirty = false;
}
- env->hvf_emul->interruptable =
- !(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
- (VMCS_INTERRUPTIBILITY_STI_BLOCKING |
- VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
-
hvf_inject_interrupts(cpu);
vmx_update_tpr(cpu);
@@ -792,7 +836,10 @@ int hvf_vcpu_exec(CPUState *cpu)
uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);
uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd,
VMCS_EXIT_INSTRUCTION_LENGTH);
+
uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
+
+ hvf_store_events(cpu, ins_len, idtvec_info);
rip = rreg(cpu->hvf_fd, HV_X86_RIP);
RFLAGS(env) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
env->eflags = RFLAGS(env);
diff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf-utils/vmcs.h
index c410dcfaaa..0fae73dce5 100644
--- a/target/i386/hvf-utils/vmcs.h
+++ b/target/i386/hvf-utils/vmcs.h
@@ -299,6 +299,7 @@
/*
* VMCS IDT-Vectoring information fields
*/
+#define VMCS_IDT_VEC_VECNUM 0xFF
#define VMCS_IDT_VEC_VALID (1U << 31)
#define VMCS_IDT_VEC_TYPE 0x700
#define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11)
@@ -306,6 +307,8 @@
#define VMCS_IDT_VEC_NMI (2 << 8)
#define VMCS_IDT_VEC_HWEXCEPTION (3 << 8)
#define VMCS_IDT_VEC_SWINTR (4 << 8)
+#define VMCS_IDT_VEC_PRIV_SWEXCEPTION (5 << 8)
+#define VMCS_IDT_VEC_SWEXCEPTION (6 << 8)
/*
* VMCS Guest interruptibility field
diff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf-utils/vmx.h
index d086c8d253..6d557045a5 100644
--- a/target/i386/hvf-utils/vmx.h
+++ b/target/i386/hvf-utils/vmx.h
@@ -181,6 +181,10 @@ static inline void macvm_set_rip(CPUState *cpu, uint64_t rip)
static inline void vmx_clear_nmi_blocking(CPUState *cpu)
{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
+ env->hflags2 &= ~HF2_NMI_MASK;
uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
@@ -188,6 +192,10 @@ static inline void vmx_clear_nmi_blocking(CPUState *cpu)
static inline void vmx_set_nmi_blocking(CPUState *cpu)
{
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env = &x86_cpu->env;
+
+ env->hflags2 |= HF2_NMI_MASK;
uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c
index 8986b4e5e5..3a50548817 100644
--- a/target/i386/hvf-utils/x86hvf.c
+++ b/target/i386/hvf-utils/x86hvf.c
@@ -356,50 +356,47 @@ void vmx_clear_int_window_exiting(CPUState *cpu)
void hvf_inject_interrupts(CPUState *cpu_state)
{
- int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
- VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
X86CPU *x86cpu = X86_CPU(cpu_state);
CPUX86State *env = &x86cpu->env;
- uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);
- uint64_t info = 0;
-
- if (idt_info & VMCS_IDT_VEC_VALID) {
- uint8_t vector = idt_info & 0xff;
- uint64_t intr_type = idt_info & VMCS_INTR_T_MASK;
- info = idt_info;
+ uint8_t vector;
+ uint64_t intr_type;
+ bool have_event = true;
+ if (env->interrupt_injected != -1) {
+ vector = env->interrupt_injected;
+ intr_type = VMCS_INTR_T_SWINTR;
+ } else if (env->exception_injected != -1) {
+ vector = env->exception_injected;
+ if (vector == EXCP03_INT3 || vector == EXCP04_INTO) {
+ intr_type = VMCS_INTR_T_SWEXCEPTION;
+ } else {
+ intr_type = VMCS_INTR_T_HWEXCEPTION;
+ }
+ } else if (env->nmi_injected) {
+ vector = NMI_VEC;
+ intr_type = VMCS_INTR_T_NMI;
+ } else {
+ have_event = false;
+ }
+ uint64_t info = 0;
+ if (have_event) {
+ info = vector | intr_type | VMCS_INTR_VALID;
uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON);
- if (intr_type == VMCS_INTR_T_NMI && reason != EXIT_REASON_TASK_SWITCH) {
- allow_nmi = 1;
+ if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) {
vmx_clear_nmi_blocking(cpu_state);
}
- if ((allow_nmi || intr_type != VMCS_INTR_T_NMI)) {
+ if (!(env->hflags2 & HF2_NMI_MASK) || intr_type != VMCS_INTR_T_NMI) {
info &= ~(1 << 12); /* clear undefined bit */
if (intr_type == VMCS_INTR_T_SWINTR ||
- intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||
intr_type == VMCS_INTR_T_SWEXCEPTION) {
- uint64_t ins_len = rvmcs(cpu_state->hvf_fd,
- VMCS_EXIT_INSTRUCTION_LENGTH);
- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
- }
- if (vector == EXCEPTION_BP || vector == EXCEPTION_OF) {
- /*
- * VT-x requires #BP and #OF to be injected as software
- * exceptions.
- */
- info &= ~VMCS_INTR_T_MASK;
- info |= VMCS_INTR_T_SWEXCEPTION;
- uint64_t ins_len = rvmcs(cpu_state->hvf_fd,
- VMCS_EXIT_INSTRUCTION_LENGTH);
- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);
}
- uint64_t err = 0;
- if (idt_info & VMCS_INTR_DEL_ERRCODE) {
- err = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR);
- wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err);
+ if (env->has_error_code) {
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR,
+ env->error_code);
}
/*printf("reinject %lx err %d\n", info, err);*/
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
@@ -407,7 +404,7 @@ void hvf_inject_interrupts(CPUState *cpu_state)
}
if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {
- if (allow_nmi && !(info & VMCS_INTR_VALID)) {
+ if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) {
cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | NMI_VEC;
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
@@ -416,7 +413,7 @@ void hvf_inject_interrupts(CPUState *cpu_state)
}
}
- if (env->hvf_emul->interruptable &&
+ if (!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
(cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
(EFLAGS(env) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
int line = cpu_get_pic_interrupt(&x86cpu->env);
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 6db7783edc..a695b8cd4e 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1030,8 +1030,6 @@ void kvm_arch_reset_vcpu(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
- env->exception_injected = -1;
- env->interrupt_injected = -1;
env->xcr0 = 1;
if (kvm_irqchip_in_kernel()) {
env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Qemu-devel] [PATCH 14/14] hvf: inject General Protection Fault when vmexit through vmcall
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (12 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 13/14] hvf: refactor event injection code for hvf Sergio Andres Gomez Del Real
@ 2017-08-28 1:56 ` Sergio Andres Gomez Del Real
2017-08-28 7:24 ` [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU no-reply
` (2 subsequent siblings)
16 siblings, 0 replies; 27+ messages in thread
From: Sergio Andres Gomez Del Real @ 2017-08-28 1:56 UTC (permalink / raw)
To: qemu-devel; +Cc: Sergio Andres Gomez Del Real
This commit injects a GP fault when the guest vmexit's by executing a
vmcall instruction.
Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
---
target/i386/hvf-all.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
index 25e4fd4eb2..fdb2b12c8a 100644
--- a/target/i386/hvf-all.c
+++ b/target/i386/hvf-all.c
@@ -1064,7 +1064,9 @@ int hvf_vcpu_exec(CPUState *cpu)
macvm_set_rip(cpu, rip + ins_len);
break;
case VMX_REASON_VMCALL:
- /* TODO: inject #GP fault */
+ env->exception_injected = EXCP0D_GPF;
+ env->has_error_code = true;
+ env->error_code = 0;
break;
default:
fprintf(stderr, "%llx: unhandled exit %llx\n", rip, exit_reason);
--
2.14.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (13 preceding siblings ...)
2017-08-28 1:56 ` [Qemu-devel] [PATCH 14/14] hvf: inject General Protection Fault when vmexit through vmcall Sergio Andres Gomez Del Real
@ 2017-08-28 7:24 ` no-reply
2017-08-29 9:51 ` Stefan Hajnoczi
2017-08-29 9:53 ` Stefan Hajnoczi
16 siblings, 0 replies; 27+ messages in thread
From: no-reply @ 2017-08-28 7:24 UTC (permalink / raw)
To: sergio.g.delreal; +Cc: famz, qemu-devel, Sergio.G.DelReal
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Subject: [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU
Message-id: 20170828015654.2530-1-Sergio.G.DelReal@gmail.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20170828015654.2530-1-Sergio.G.DelReal@gmail.com -> patchew/20170828015654.2530-1-Sergio.G.DelReal@gmail.com
Switched to a new branch 'test'
b279706053 hvf: inject General Protection Fault when vmexit through vmcall
3f4eacf577 hvf: refactor event injection code for hvf
6aa5077cc9 hvf: move fields from CPUState to CPUX86State
a6d5a70cee hvf: implement vga dirty page tracking
8c4e7701f9 hvf: refactor cpuid code
b6fd2efc4a hvf: implement hvf_get_supported_cpuid
c0e093a40a apic: add function to apic that will be used by hvf
eb479acf42 hvf: run hvf code through checkpatch.pl and fix style issues
19a4b813a6 hvf: add compilation rules to Makefile.objs
977ccbfd5a hvf: use new helper functions for put/get xsave
1f90c0f943 hvf: add fields to CPUState and CPUX86State; add definitions
f5c67bec92 hvf: add conditional macros around hvf code in cpus.c
33276f37df hvf: add code base from Google's QEMU repository
18621fd06c hvf: add support for Hypervisor.framework in the configure script
=== OUTPUT BEGIN ===
Checking PATCH 1/14: hvf: add support for Hypervisor.framework in the configure script...
Checking PATCH 2/14: hvf: add code base from Google's QEMU repository...
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
ERROR: line over 90 characters
#129: FILE: include/sysemu/hvf.h:59:
+/* Disable HVF if |disable| is 1, otherwise, enable it iff it is supported by the host CPU.
WARNING: line over 80 characters
#133: FILE: include/sysemu/hvf.h:63:
+/* Returns non-0 if the host CPU supports the VMX "unrestricted guest" feature which
WARNING: line over 80 characters
#134: FILE: include/sysemu/hvf.h:64:
+ * allows the virtual CPU to directly run in "real mode". If true, this allows QEMU to run
WARNING: line over 80 characters
#135: FILE: include/sysemu/hvf.h:65:
+ * several vCPU threads in parallel (see cpus.c). Otherwise, only a a single TCG thread
WARNING: line over 80 characters
#136: FILE: include/sysemu/hvf.h:66:
+ * can run, and it will call HVF to run the current instructions, except in case of
WARNING: line over 80 characters
#138: FILE: include/sysemu/hvf.h:68:
+// int hvf_ug_platform(void); does not apply to HVF; assume we must be in UG mode
ERROR: do not use C99 // comments
#138: FILE: include/sysemu/hvf.h:68:
+// int hvf_ug_platform(void); does not apply to HVF; assume we must be in UG mode
ERROR: do not use C99 // comments
#152: FILE: include/sysemu/hvf.h:82:
+// void hvf_reset_vcpu_state(void *opaque);
ERROR: braces {} are necessary for all arms of this statement
#209: FILE: target/i386/hvf-all.c:37:
+ if (ret == HV_SUCCESS)
[...]
ERROR: switch and case should be at the same indent
#212: FILE: target/i386/hvf-all.c:40:
+ switch (ret) {
+ case HV_ERROR:
[...]
+ case HV_BUSY:
[...]
+ case HV_BAD_ARGUMENT:
[...]
+ case HV_NO_RESOURCES:
[...]
+ case HV_NO_DEVICE:
[...]
+ case HV_UNSUPPORTED:
[...]
+ default:
ERROR: do not use C99 // comments
#238: FILE: target/i386/hvf-all.c:66:
+// Memory slots/////////////////////////////////////////////////////////////////
ERROR: open brace '{' following function declarations go on the next line
#240: FILE: target/i386/hvf-all.c:68:
+hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t end) {
WARNING: line over 80 characters
#245: FILE: target/i386/hvf-all.c:73:
+ if (slot->size && start < (slot->start + slot->size) && end > slot->start)
ERROR: braces {} are necessary for all arms of this statement
#245: FILE: target/i386/hvf-all.c:73:
+ if (slot->size && start < (slot->start + slot->size) && end > slot->start)
[...]
ERROR: spaces required around that '+' (ctx:VxV)
#259: FILE: target/i386/hvf-all.c:87:
+#define ALIGN(x, y) (((x)+(y)-1) & ~((y)-1))
^
ERROR: spaces required around that '-' (ctx:VxV)
#259: FILE: target/i386/hvf-all.c:87:
+#define ALIGN(x, y) (((x)+(y)-1) & ~((y)-1))
^
ERROR: spaces required around that '-' (ctx:VxV)
#259: FILE: target/i386/hvf-all.c:87:
+#define ALIGN(x, y) (((x)+(y)-1) & ~((y)-1))
^
ERROR: "foo* bar" should be "foo *bar"
#294: FILE: target/i386/hvf-all.c:122:
+void hvf_set_phys_mem(MemoryRegionSection* section, bool add)
ERROR: trailing statements should be on next line
#299: FILE: target/i386/hvf-all.c:127:
+ if (!memory_region_is_ram(area)) return;
ERROR: braces {} are necessary for all arms of this statement
#299: FILE: target/i386/hvf-all.c:127:
+ if (!memory_region_is_ram(area)) return;
[...]
ERROR: braces {} are necessary for all arms of this statement
#306: FILE: target/i386/hvf-all.c:134:
+ if (mem->size == int128_get64(section->size) &&
[...]
ERROR: line over 90 characters
#308: FILE: target/i386/hvf-all.c:136:
+ mem->mem == (memory_region_get_ram_ptr(area) + section->offset_within_region))
ERROR: do not use C99 // comments
#309: FILE: target/i386/hvf-all.c:137:
+ return; // Same region was attempted to register, go away.
ERROR: do not use C99 // comments
#312: FILE: target/i386/hvf-all.c:140:
+ // Region needs to be reset. set the size to 0 and remap it.
ERROR: trailing statements should be on next line
#321: FILE: target/i386/hvf-all.c:149:
+ if (!add) return;
ERROR: braces {} are necessary for all arms of this statement
#321: FILE: target/i386/hvf-all.c:149:
+ if (!add) return;
[...]
ERROR: do not use C99 // comments
#323: FILE: target/i386/hvf-all.c:151:
+ // Now make a new slot.
ERROR: braces {} are necessary for all arms of this statement
#328: FILE: target/i386/hvf-all.c:156:
+ if (!mem->size)
[...]
ERROR: do not use C99 // comments
#361: FILE: target/i386/hvf-all.c:189:
+ // TODO: need integrate APIC handling
ERROR: braces {} are necessary for all arms of this statement
#367: FILE: target/i386/hvf-all.c:195:
+ if (irr == -1)
[...]
+ else
[...]
WARNING: line over 80 characters
#370: FILE: target/i386/hvf-all.c:198:
+ wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4);
ERROR: do not use C99 // comments
#382: FILE: target/i386/hvf-all.c:210:
+// TODO: taskswitch handling
WARNING: line over 80 characters
#422: FILE: target/i386/hvf-all.c:250:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR);
ERROR: space required before the open brace '{'
#422: FILE: target/i386/hvf-all.c:250:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR);
ERROR: space required after that close brace '}'
#422: FILE: target/i386/hvf-all.c:250:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR);
WARNING: line over 80 characters
#423: FILE: target/i386/hvf-all.c:251:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES);
ERROR: space required before the open brace '{'
#423: FILE: target/i386/hvf-all.c:251:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES);
ERROR: space required after that close brace '}'
#423: FILE: target/i386/hvf-all.c:251:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES);
WARNING: line over 80 characters
#424: FILE: target/i386/hvf-all.c:252:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS);
ERROR: space required before the open brace '{'
#424: FILE: target/i386/hvf-all.c:252:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS);
ERROR: space required after that close brace '}'
#424: FILE: target/i386/hvf-all.c:252:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS);
WARNING: line over 80 characters
#425: FILE: target/i386/hvf-all.c:253:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS);
ERROR: space required before the open brace '{'
#425: FILE: target/i386/hvf-all.c:253:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS);
ERROR: space required after that close brace '}'
#425: FILE: target/i386/hvf-all.c:253:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS);
WARNING: line over 80 characters
#426: FILE: target/i386/hvf-all.c:254:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS);
ERROR: space required before the open brace '{'
#426: FILE: target/i386/hvf-all.c:254:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS);
ERROR: space required after that close brace '}'
#426: FILE: target/i386/hvf-all.c:254:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS);
WARNING: line over 80 characters
#427: FILE: target/i386/hvf-all.c:255:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS);
ERROR: space required before the open brace '{'
#427: FILE: target/i386/hvf-all.c:255:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS);
ERROR: space required after that close brace '}'
#427: FILE: target/i386/hvf-all.c:255:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS);
WARNING: line over 80 characters
#428: FILE: target/i386/hvf-all.c:256:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS);
ERROR: space required before the open brace '{'
#428: FILE: target/i386/hvf-all.c:256:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS);
ERROR: space required after that close brace '}'
#428: FILE: target/i386/hvf-all.c:256:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS);
ERROR: if this code is redundant consider removing it
#430: FILE: target/i386/hvf-all.c:258:
+#if 0
ERROR: line over 90 characters
#441: FILE: target/i386/hvf-all.c:269:
+static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
WARNING: line over 80 characters
#442: FILE: target/i386/hvf-all.c:270:
+ uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
ERROR: line over 90 characters
#452: FILE: target/i386/hvf-all.c:280:
+ vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset);
WARNING: line over 80 characters
#458: FILE: target/i386/hvf-all.c:286:
+ vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss));
ERROR: line over 90 characters
#464: FILE: target/i386/hvf-all.c:292:
+static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
WARNING: line over 80 characters
#479: FILE: target/i386/hvf-all.c:307:
+ x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, REG_SEG_TR);
ERROR: braces {} are necessary for all arms of this statement
#495: FILE: target/i386/hvf-all.c:323:
+ if (tss_sel.rpl > dpl || cs.rpl > dpl)
[...]
ERROR: do not use C99 // comments
#496: FILE: target/i386/hvf-all.c:324:
+ ;//DPRINTF("emulate_gp");
ERROR: line over 90 characters
#500: FILE: target/i386/hvf-all.c:328:
+ if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) {
ERROR: braces {} are necessary for all arms of this statement
#509: FILE: target/i386/hvf-all.c:337:
+ if (reason == TSR_IRET)
[...]
ERROR: braces {} are necessary for all arms of this statement
#512: FILE: target/i386/hvf-all.c:340:
+ if (reason != TSR_CALL && reason != TSR_IDT_GATE)
[...]
ERROR: braces {} are necessary for all arms of this statement
#520: FILE: target/i386/hvf-all.c:348:
+ if (next_tss_desc.type & 8)
[...]
+ else
[...]
WARNING: line over 80 characters
#521: FILE: target/i386/hvf-all.c:349:
+ ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
WARNING: line over 80 characters
#523: FILE: target/i386/hvf-all.c:351:
+ //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
ERROR: do not use C99 // comments
#523: FILE: target/i386/hvf-all.c:351:
+ //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
ERROR: "foo * bar" should be "foo *bar"
#536: FILE: target/i386/hvf-all.c:364:
+static void hvf_handle_interrupt(CPUState * cpu, int mask)
ERROR: "foo * bar" should be "foo *bar"
#544: FILE: target/i386/hvf-all.c:372:
+void hvf_handle_io(CPUArchState * env, uint16_t port, void* buffer,
ERROR: do not use C99 // comments
#557: FILE: target/i386/hvf-all.c:385:
+//
ERROR: do not use C99 // comments
#558: FILE: target/i386/hvf-all.c:386:
+// TODO: synchronize vcpu state
ERROR: do not use C99 // comments
#561: FILE: target/i386/hvf-all.c:389:
+ CPUState *cpu_state = cpu;//(CPUState *)data;
ERROR: braces {} are necessary for all arms of this statement
#562: FILE: target/i386/hvf-all.c:390:
+ if (cpu_state->hvf_vcpu_dirty == 0)
[...]
ERROR: braces {} are necessary for all arms of this statement
#570: FILE: target/i386/hvf-all.c:398:
+ if (cpu_state->hvf_vcpu_dirty == 0)
[...]
ERROR: trailing whitespace
#597: FILE: target/i386/hvf-all.c:425:
+ $
ERROR: do not use C99 // comments
#598: FILE: target/i386/hvf-all.c:426:
+// TODO: ept fault handlig
ERROR: externs should be avoided in .c files
#599: FILE: target/i386/hvf-all.c:427:
+void vmx_clear_int_window_exiting(CPUState *cpu);
ERROR: code indent should never use tabs
#602: FILE: target/i386/hvf-all.c:430:
+^Iint read, write;$
ERROR: code indent should never use tabs
#604: FILE: target/i386/hvf-all.c:432:
+^I/* EPT fault on an instruction fetch doesn't make sense here */$
ERROR: code indent should never use tabs
#605: FILE: target/i386/hvf-all.c:433:
+^Iif (ept_qual & EPT_VIOLATION_INST_FETCH)$
ERROR: braces {} are necessary for all arms of this statement
#605: FILE: target/i386/hvf-all.c:433:
+ if (ept_qual & EPT_VIOLATION_INST_FETCH)
[...]
ERROR: code indent should never use tabs
#606: FILE: target/i386/hvf-all.c:434:
+^I^Ireturn false;$
ERROR: code indent should never use tabs
#608: FILE: target/i386/hvf-all.c:436:
+^I/* EPT fault must be a read fault or a write fault */$
ERROR: code indent should never use tabs
#609: FILE: target/i386/hvf-all.c:437:
+^Iread = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;$
ERROR: code indent should never use tabs
#610: FILE: target/i386/hvf-all.c:438:
+^Iwrite = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;$
ERROR: code indent should never use tabs
#611: FILE: target/i386/hvf-all.c:439:
+^Iif ((read | write) == 0)$
ERROR: braces {} are necessary for all arms of this statement
#611: FILE: target/i386/hvf-all.c:439:
+ if ((read | write) == 0)
[...]
ERROR: code indent should never use tabs
#612: FILE: target/i386/hvf-all.c:440:
+^I^Ireturn false;$
ERROR: code indent should never use tabs
#614: FILE: target/i386/hvf-all.c:442:
+^I/*$
ERROR: code indent should never use tabs
#615: FILE: target/i386/hvf-all.c:443:
+^I * The EPT violation must have been caused by accessing a$
ERROR: code indent should never use tabs
#616: FILE: target/i386/hvf-all.c:444:
+^I * guest-physical address that is a translation of a guest-linear$
ERROR: code indent should never use tabs
#617: FILE: target/i386/hvf-all.c:445:
+^I * address.$
ERROR: code indent should never use tabs
#618: FILE: target/i386/hvf-all.c:446:
+^I */$
ERROR: code indent should never use tabs
#619: FILE: target/i386/hvf-all.c:447:
+^Iif ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||$
ERROR: code indent should never use tabs
#620: FILE: target/i386/hvf-all.c:448:
+^I (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {$
ERROR: code indent should never use tabs
#621: FILE: target/i386/hvf-all.c:449:
+^I^Ireturn false;$
ERROR: code indent should never use tabs
#622: FILE: target/i386/hvf-all.c:450:
+^I}$
ERROR: code indent should never use tabs
#624: FILE: target/i386/hvf-all.c:452:
+^Ireturn true;$
ERROR: "foo * bar" should be "foo *bar"
#627: FILE: target/i386/hvf-all.c:455:
+static void hvf_region_add(MemoryListener * listener,
ERROR: "foo * bar" should be "foo *bar"
#628: FILE: target/i386/hvf-all.c:456:
+ MemoryRegionSection * section)
ERROR: "foo * bar" should be "foo *bar"
#633: FILE: target/i386/hvf-all.c:461:
+static void hvf_region_del(MemoryListener * listener,
ERROR: "foo * bar" should be "foo *bar"
#634: FILE: target/i386/hvf-all.c:462:
+ MemoryRegionSection * section)
ERROR: open brace '{' following function declarations go on the next line
#649: FILE: target/i386/hvf-all.c:477:
+void vmx_reset_vcpu(CPUState *cpu) {
ERROR: do not use C99 // comments
#659: FILE: target/i386/hvf-all.c:487:
+ // set VMCS guest state fields
ERROR: do not use C99 // comments
#706: FILE: target/i386/hvf-all.c:534:
+ //wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);
ERROR: suspect code indent for conditional statements (4, 9)
#720: FILE: target/i386/hvf-all.c:548:
+ for (int i = 0; i < 8; i++)
+ wreg(cpu->hvf_fd, HV_X86_R8+i, 0x0);
ERROR: braces {} are necessary even for single statement blocks
#720: FILE: target/i386/hvf-all.c:548:
+ for (int i = 0; i < 8; i++)
+ wreg(cpu->hvf_fd, HV_X86_R8+i, 0x0);
ERROR: spaces required around that '+' (ctx:VxV)
#721: FILE: target/i386/hvf-all.c:549:
+ wreg(cpu->hvf_fd, HV_X86_R8+i, 0x0);
^
ERROR: trailing whitespace
#729: FILE: target/i386/hvf-all.c:557:
+void hvf_vcpu_destroy(CPUState* cpu) $
ERROR: "foo* bar" should be "foo *bar"
#729: FILE: target/i386/hvf-all.c:557:
+void hvf_vcpu_destroy(CPUState* cpu)
ERROR: "foo * bar" should be "foo *bar"
#739: FILE: target/i386/hvf-all.c:567:
+int hvf_init_vcpu(CPUState * cpu) {
ERROR: open brace '{' following function declarations go on the next line
#739: FILE: target/i386/hvf-all.c:567:
+int hvf_init_vcpu(CPUState * cpu) {
ERROR: trailing whitespace
#742: FILE: target/i386/hvf-all.c:570:
+ $
ERROR: do not use C99 // comments
#743: FILE: target/i386/hvf-all.c:571:
+ // init cpu signals
WARNING: line over 80 characters
#759: FILE: target/i386/hvf-all.c:587:
+ cpu->hvf_caps = (struct hvf_vcpu_caps*)g_malloc0(sizeof(struct hvf_vcpu_caps));
ERROR: "(foo*)" should be "(foo *)"
#759: FILE: target/i386/hvf-all.c:587:
+ cpu->hvf_caps = (struct hvf_vcpu_caps*)g_malloc0(sizeof(struct hvf_vcpu_caps));
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#759: FILE: target/i386/hvf-all.c:587:
+ cpu->hvf_caps = (struct hvf_vcpu_caps*)g_malloc0(sizeof(struct hvf_vcpu_caps));
WARNING: line over 80 characters
#760: FILE: target/i386/hvf-all.c:588:
+ cpu->hvf_x86 = (struct hvf_x86_state*)g_malloc0(sizeof(struct hvf_x86_state));
ERROR: "(foo*)" should be "(foo *)"
#760: FILE: target/i386/hvf-all.c:588:
+ cpu->hvf_x86 = (struct hvf_x86_state*)g_malloc0(sizeof(struct hvf_x86_state));
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#760: FILE: target/i386/hvf-all.c:588:
+ cpu->hvf_x86 = (struct hvf_x86_state*)g_malloc0(sizeof(struct hvf_x86_state));
WARNING: line over 80 characters
#766: FILE: target/i386/hvf-all.c:594:
+ if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &cpu->hvf_caps->vmx_cap_pinbased))
ERROR: code indent should never use tabs
#766: FILE: target/i386/hvf-all.c:594:
+^Iif (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &cpu->hvf_caps->vmx_cap_pinbased))$
ERROR: braces {} are necessary for all arms of this statement
#766: FILE: target/i386/hvf-all.c:594:
+ if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &cpu->hvf_caps->vmx_cap_pinbased))
[...]
ERROR: code indent should never use tabs
#767: FILE: target/i386/hvf-all.c:595:
+^I^Iabort();$
ERROR: line over 90 characters
#768: FILE: target/i386/hvf-all.c:596:
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cpu->hvf_caps->vmx_cap_procbased))
ERROR: code indent should never use tabs
#768: FILE: target/i386/hvf-all.c:596:
+^Iif (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cpu->hvf_caps->vmx_cap_procbased))$
ERROR: braces {} are necessary for all arms of this statement
#768: FILE: target/i386/hvf-all.c:596:
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cpu->hvf_caps->vmx_cap_procbased))
[...]
ERROR: code indent should never use tabs
#769: FILE: target/i386/hvf-all.c:597:
+^I^Iabort();$
ERROR: line over 90 characters
#770: FILE: target/i386/hvf-all.c:598:
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cpu->hvf_caps->vmx_cap_procbased2))
ERROR: code indent should never use tabs
#770: FILE: target/i386/hvf-all.c:598:
+^Iif (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cpu->hvf_caps->vmx_cap_procbased2))$
ERROR: braces {} are necessary for all arms of this statement
#770: FILE: target/i386/hvf-all.c:598:
+ if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cpu->hvf_caps->vmx_cap_procbased2))
[...]
ERROR: code indent should never use tabs
#771: FILE: target/i386/hvf-all.c:599:
+^I^Iabort();$
WARNING: line over 80 characters
#772: FILE: target/i386/hvf-all.c:600:
+ if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cpu->hvf_caps->vmx_cap_entry))
ERROR: code indent should never use tabs
#772: FILE: target/i386/hvf-all.c:600:
+^Iif (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cpu->hvf_caps->vmx_cap_entry))$
ERROR: braces {} are necessary for all arms of this statement
#772: FILE: target/i386/hvf-all.c:600:
+ if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cpu->hvf_caps->vmx_cap_entry))
[...]
ERROR: code indent should never use tabs
#773: FILE: target/i386/hvf-all.c:601:
+^I^Iabort();$
ERROR: code indent should never use tabs
#775: FILE: target/i386/hvf-all.c:603:
+^I/* set VMCS control fields */$
WARNING: line over 80 characters
#776: FILE: target/i386/hvf-all.c:604:
+ wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));
ERROR: line over 90 characters
#777: FILE: target/i386/hvf-all.c:605:
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,
WARNING: line over 80 characters
#778: FILE: target/i386/hvf-all.c:606:
+ VMCS_PRI_PROC_BASED_CTLS_HLT |
WARNING: line over 80 characters
#779: FILE: target/i386/hvf-all.c:607:
+ VMCS_PRI_PROC_BASED_CTLS_MWAIT |
WARNING: line over 80 characters
#780: FILE: target/i386/hvf-all.c:608:
+ VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
WARNING: line over 80 characters
#781: FILE: target/i386/hvf-all.c:609:
+ VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
WARNING: line over 80 characters
#782: FILE: target/i386/hvf-all.c:610:
+ VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
ERROR: code indent should never use tabs
#783: FILE: target/i386/hvf-all.c:611:
+^Iwvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,$
ERROR: line over 90 characters
#784: FILE: target/i386/hvf-all.c:612:
+ cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
ERROR: space required after that ',' (ctx:VxV)
#784: FILE: target/i386/hvf-all.c:612:
+ cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
^
WARNING: line over 80 characters
#786: FILE: target/i386/hvf-all.c:614:
+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry, 0));
ERROR: code indent should never use tabs
#786: FILE: target/i386/hvf-all.c:614:
+^Iwvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry, 0));$
ERROR: code indent should never use tabs
#787: FILE: target/i386/hvf-all.c:615:
+^Iwvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */$
WARNING: line over 80 characters
#794: FILE: target/i386/hvf-all.c:622:
+ x86cpu->env.kvm_xsave_buf = qemu_memalign(4096, sizeof(struct hvf_xsave_buf));
ERROR: do not use C99 // comments
#804: FILE: target/i386/hvf-all.c:632:
+ //hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);
ERROR: open brace '{' following function declarations go on the next line
#813: FILE: target/i386/hvf-all.c:641:
+void hvf_disable(int shouldDisable) {
ERROR: "foo* bar" should be "foo *bar"
#817: FILE: target/i386/hvf-all.c:645:
+int hvf_vcpu_exec(CPUState* cpu) {
ERROR: open brace '{' following function declarations go on the next line
#817: FILE: target/i386/hvf-all.c:645:
+int hvf_vcpu_exec(CPUState* cpu) {
WARNING: line over 80 characters
#837: FILE: target/i386/hvf-all.c:665:
+ (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
WARNING: line over 80 characters
#855: FILE: target/i386/hvf-all.c:683:
+ uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
ERROR: switch and case should be at the same indent
#869: FILE: target/i386/hvf-all.c:697:
+ switch (exit_reason) {
[...]
+ case EXIT_REASON_EPT_FAULT:
[...]
+ case EXIT_REASON_INOUT:
[...]
+ case EXIT_REASON_INTR_WINDOW:
[...]
+ case EXIT_REASON_NMI_WINDOW:
[...]
+ case EXIT_REASON_EXT_INTR:
[...]
+ case EXIT_REASON_RDMSR:
+ case EXIT_REASON_WRMSR:
[...]
+ case EXIT_REASON_RDPMC:
[...]
+ case VMX_REASON_VMCALL:
[...]
+ default:
ERROR: line over 90 characters
#872: FILE: target/i386/hvf-all.c:700:
+ if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu) & IF_MASK))
ERROR: line over 90 characters
#892: FILE: target/i386/hvf-all.c:720:
+ if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && (exit_qual & EXIT_QUAL_NMIUDTI) != 0)
ERROR: braces {} are necessary for all arms of this statement
#892: FILE: target/i386/hvf-all.c:720:
+ if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && (exit_qual & EXIT_QUAL_NMIUDTI) != 0)
[...]
ERROR: do not use C99 // comments
#896: FILE: target/i386/hvf-all.c:724:
+ // mmio
ERROR: braces {} are necessary for all arms of this statement
#912: FILE: target/i386/hvf-all.c:740:
+ if (!read && !write)
[...]
ERROR: trailing statements should be on next line
#915: FILE: target/i386/hvf-all.c:743:
+ if (write) flags |= HV_MEMORY_WRITE;
ERROR: braces {} are necessary for all arms of this statement
#915: FILE: target/i386/hvf-all.c:743:
+ if (write) flags |= HV_MEMORY_WRITE;
[...]
ERROR: braces {} are necessary for all arms of this statement
#918: FILE: target/i386/hvf-all.c:746:
+ if (write)
[...]
ERROR: do not use C99 // comments
#932: FILE: target/i386/hvf-all.c:760:
+ //uint32_t rep = (exit_qual & 0x20) != 0;
ERROR: trailing statements should be on next line
#939: FILE: target/i386/hvf-all.c:767:
+ if (size == 1) AL(cpu) = val;
ERROR: braces {} are necessary for all arms of this statement
#939: FILE: target/i386/hvf-all.c:767:
+ if (size == 1) AL(cpu) = val;
[...]
+ else if (size == 2) AX(cpu) = val;
[...]
+ else if (size == 4) RAX(cpu) = (uint32_t)val;
[...]
+ else VM_PANIC("size");
[...]
ERROR: trailing statements should be on next line
#940: FILE: target/i386/hvf-all.c:768:
+ else if (size == 2) AX(cpu) = val;
ERROR: braces {} are necessary for all arms of this statement
#940: FILE: target/i386/hvf-all.c:768:
+ else if (size == 2) AX(cpu) = val;
[...]
+ else if (size == 4) RAX(cpu) = (uint32_t)val;
[...]
+ else VM_PANIC("size");
[...]
ERROR: trailing statements should be on next line
#941: FILE: target/i386/hvf-all.c:769:
+ else if (size == 4) RAX(cpu) = (uint32_t)val;
ERROR: braces {} are necessary for all arms of this statement
#941: FILE: target/i386/hvf-all.c:769:
+ else if (size == 4) RAX(cpu) = (uint32_t)val;
[...]
+ else VM_PANIC("size");
[...]
ERROR: trailing statements should be on next line
#942: FILE: target/i386/hvf-all.c:770:
+ else VM_PANIC("size");
ERROR: braces {} are necessary for all arms of this statement
#1013: FILE: target/i386/hvf-all.c:841:
+ if (exit_reason == EXIT_REASON_RDMSR)
[...]
+ else
[...]
ERROR: switch and case should be at the same indent
#1029: FILE: target/i386/hvf-all.c:857:
+ switch (cr) {
[...]
+ default:
WARNING: line over 80 characters
#1041: FILE: target/i386/hvf-all.c:869:
+ RRX(cpu, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
ERROR: else should follow close brace '}'
#1043: FILE: target/i386/hvf-all.c:871:
+ }
+ else {
ERROR: do not use C99 // comments
#1058: FILE: target/i386/hvf-all.c:886:
+ case EXIT_REASON_APIC_ACCESS: { // TODO
ERROR: line over 90 characters
#1077: FILE: target/i386/hvf-all.c:905:
+ vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo & VMCS_INTR_T_MASK);
ERROR: do not use C99 // comments
#1081: FILE: target/i386/hvf-all.c:909:
+ //addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
ERROR: do not use C99 // comments
#1093: FILE: target/i386/hvf-all.c:921:
+ // TODO: maybe just take this out?
ERROR: do not use C99 // comments
#1094: FILE: target/i386/hvf-all.c:922:
+ // if (g_hypervisor_iface) {
ERROR: do not use C99 // comments
#1095: FILE: target/i386/hvf-all.c:923:
+ // load_regs(cpu);
ERROR: do not use C99 // comments
#1096: FILE: target/i386/hvf-all.c:924:
+ // g_hypervisor_iface->hypercall_handler(cpu);
WARNING: line over 80 characters
#1097: FILE: target/i386/hvf-all.c:925:
+ // RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
ERROR: do not use C99 // comments
#1097: FILE: target/i386/hvf-all.c:925:
+ // RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
ERROR: do not use C99 // comments
#1098: FILE: target/i386/hvf-all.c:926:
+ // store_regs(cpu);
ERROR: do not use C99 // comments
#1099: FILE: target/i386/hvf-all.c:927:
+ // }
WARNING: line over 80 characters
#1102: FILE: target/i386/hvf-all.c:930:
+ fprintf(stderr, "%llx: unhandled exit %llx\n", rip, exit_reason);
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#1120: FILE: target/i386/hvf-all.c:948:
+ s = (HVFState *)g_malloc0(sizeof(HVFState));
ERROR: trailing whitespace
#1121: FILE: target/i386/hvf-all.c:949:
+ $
ERROR: trailing whitespace
#1127: FILE: target/i386/hvf-all.c:955:
+ $
ERROR: "foo * bar" should be "foo *bar"
#1204: FILE: target/i386/hvf-i386.h:44:
+int hvf_inject_interrupt(CPUArchState * env, int vector);
ERROR: code indent should never use tabs
#1264: FILE: target/i386/hvf-utils/vmcs.h:30:
+#define^I_VMCS_H_$
ERROR: code indent should never use tabs
#1269: FILE: target/i386/hvf-utils/vmcs.h:35:
+#define^IVMCS_INITIAL^I^I^I0xffffffffffffffff$
ERROR: code indent should never use tabs
#1271: FILE: target/i386/hvf-utils/vmcs.h:37:
+#define^IVMCS_IDENT(encoding)^I^I((encoding) | 0x80000000)$
ERROR: code indent should never use tabs
#1275: FILE: target/i386/hvf-utils/vmcs.h:41:
+#define^IVMCS_INVALID_ENCODING^I^I0xffffffff$
ERROR: code indent should never use tabs
#1278: FILE: target/i386/hvf-utils/vmcs.h:44:
+#define^IVMCS_VPID^I^I^I0x00000000$
ERROR: code indent should never use tabs
#1279: FILE: target/i386/hvf-utils/vmcs.h:45:
+#define^IVMCS_PIR_VECTOR^I^I^I0x00000002$
ERROR: code indent should never use tabs
#1282: FILE: target/i386/hvf-utils/vmcs.h:48:
+#define^IVMCS_GUEST_ES_SELECTOR^I^I0x00000800$
ERROR: code indent should never use tabs
#1283: FILE: target/i386/hvf-utils/vmcs.h:49:
+#define^IVMCS_GUEST_CS_SELECTOR^I^I0x00000802$
ERROR: code indent should never use tabs
#1284: FILE: target/i386/hvf-utils/vmcs.h:50:
+#define^IVMCS_GUEST_SS_SELECTOR^I^I0x00000804$
ERROR: code indent should never use tabs
#1285: FILE: target/i386/hvf-utils/vmcs.h:51:
+#define^IVMCS_GUEST_DS_SELECTOR^I^I0x00000806$
ERROR: code indent should never use tabs
#1286: FILE: target/i386/hvf-utils/vmcs.h:52:
+#define^IVMCS_GUEST_FS_SELECTOR^I^I0x00000808$
ERROR: code indent should never use tabs
#1287: FILE: target/i386/hvf-utils/vmcs.h:53:
+#define^IVMCS_GUEST_GS_SELECTOR^I^I0x0000080A$
ERROR: code indent should never use tabs
#1288: FILE: target/i386/hvf-utils/vmcs.h:54:
+#define^IVMCS_GUEST_LDTR_SELECTOR^I0x0000080C$
ERROR: code indent should never use tabs
#1289: FILE: target/i386/hvf-utils/vmcs.h:55:
+#define^IVMCS_GUEST_TR_SELECTOR^I^I0x0000080E$
ERROR: code indent should never use tabs
#1290: FILE: target/i386/hvf-utils/vmcs.h:56:
+#define^IVMCS_GUEST_INTR_STATUS^I^I0x00000810$
ERROR: code indent should never use tabs
#1293: FILE: target/i386/hvf-utils/vmcs.h:59:
+#define^IVMCS_HOST_ES_SELECTOR^I^I0x00000C00$
ERROR: code indent should never use tabs
#1294: FILE: target/i386/hvf-utils/vmcs.h:60:
+#define^IVMCS_HOST_CS_SELECTOR^I^I0x00000C02$
ERROR: code indent should never use tabs
#1295: FILE: target/i386/hvf-utils/vmcs.h:61:
+#define^IVMCS_HOST_SS_SELECTOR^I^I0x00000C04$
ERROR: code indent should never use tabs
#1296: FILE: target/i386/hvf-utils/vmcs.h:62:
+#define^IVMCS_HOST_DS_SELECTOR^I^I0x00000C06$
ERROR: code indent should never use tabs
#1297: FILE: target/i386/hvf-utils/vmcs.h:63:
+#define^IVMCS_HOST_FS_SELECTOR^I^I0x00000C08$
ERROR: code indent should never use tabs
#1298: FILE: target/i386/hvf-utils/vmcs.h:64:
+#define^IVMCS_HOST_GS_SELECTOR^I^I0x00000C0A$
ERROR: code indent should never use tabs
#1299: FILE: target/i386/hvf-utils/vmcs.h:65:
+#define^IVMCS_HOST_TR_SELECTOR^I^I0x00000C0C$
ERROR: code indent should never use tabs
#1302: FILE: target/i386/hvf-utils/vmcs.h:68:
+#define^IVMCS_IO_BITMAP_A^I^I0x00002000$
ERROR: code indent should never use tabs
#1303: FILE: target/i386/hvf-utils/vmcs.h:69:
+#define^IVMCS_IO_BITMAP_B^I^I0x00002002$
ERROR: code indent should never use tabs
#1304: FILE: target/i386/hvf-utils/vmcs.h:70:
+#define^IVMCS_MSR_BITMAP^I^I^I0x00002004$
ERROR: code indent should never use tabs
#1305: FILE: target/i386/hvf-utils/vmcs.h:71:
+#define^IVMCS_EXIT_MSR_STORE^I^I0x00002006$
ERROR: code indent should never use tabs
#1306: FILE: target/i386/hvf-utils/vmcs.h:72:
+#define^IVMCS_EXIT_MSR_LOAD^I^I0x00002008$
ERROR: code indent should never use tabs
#1307: FILE: target/i386/hvf-utils/vmcs.h:73:
+#define^IVMCS_ENTRY_MSR_LOAD^I^I0x0000200A$
ERROR: code indent should never use tabs
#1308: FILE: target/i386/hvf-utils/vmcs.h:74:
+#define^IVMCS_EXECUTIVE_VMCS^I^I0x0000200C$
ERROR: code indent should never use tabs
#1309: FILE: target/i386/hvf-utils/vmcs.h:75:
+#define^IVMCS_TSC_OFFSET^I^I^I0x00002010$
ERROR: code indent should never use tabs
#1310: FILE: target/i386/hvf-utils/vmcs.h:76:
+#define^IVMCS_VIRTUAL_APIC^I^I0x00002012$
ERROR: code indent should never use tabs
#1311: FILE: target/i386/hvf-utils/vmcs.h:77:
+#define^IVMCS_APIC_ACCESS^I^I0x00002014$
ERROR: code indent should never use tabs
#1312: FILE: target/i386/hvf-utils/vmcs.h:78:
+#define^IVMCS_PIR_DESC^I^I^I0x00002016$
ERROR: code indent should never use tabs
#1313: FILE: target/i386/hvf-utils/vmcs.h:79:
+#define^IVMCS_EPTP^I^I^I0x0000201A$
ERROR: code indent should never use tabs
#1314: FILE: target/i386/hvf-utils/vmcs.h:80:
+#define^IVMCS_EOI_EXIT0^I^I^I0x0000201C$
ERROR: code indent should never use tabs
#1315: FILE: target/i386/hvf-utils/vmcs.h:81:
+#define^IVMCS_EOI_EXIT1^I^I^I0x0000201E$
ERROR: code indent should never use tabs
#1316: FILE: target/i386/hvf-utils/vmcs.h:82:
+#define^IVMCS_EOI_EXIT2^I^I^I0x00002020$
ERROR: code indent should never use tabs
#1317: FILE: target/i386/hvf-utils/vmcs.h:83:
+#define^IVMCS_EOI_EXIT3^I^I^I0x00002022$
ERROR: code indent should never use tabs
#1318: FILE: target/i386/hvf-utils/vmcs.h:84:
+#define^IVMCS_EOI_EXIT(vector)^I^I(VMCS_EOI_EXIT0 + ((vector) / 64) * 2)$
ERROR: code indent should never use tabs
#1321: FILE: target/i386/hvf-utils/vmcs.h:87:
+#define^IVMCS_GUEST_PHYSICAL_ADDRESS^I0x00002400$
ERROR: code indent should never use tabs
#1324: FILE: target/i386/hvf-utils/vmcs.h:90:
+#define^IVMCS_LINK_POINTER^I^I0x00002800$
ERROR: code indent should never use tabs
#1325: FILE: target/i386/hvf-utils/vmcs.h:91:
+#define^IVMCS_GUEST_IA32_DEBUGCTL^I0x00002802$
ERROR: code indent should never use tabs
#1326: FILE: target/i386/hvf-utils/vmcs.h:92:
+#define^IVMCS_GUEST_IA32_PAT^I^I0x00002804$
ERROR: code indent should never use tabs
#1327: FILE: target/i386/hvf-utils/vmcs.h:93:
+#define^IVMCS_GUEST_IA32_EFER^I^I0x00002806$
ERROR: code indent should never use tabs
#1328: FILE: target/i386/hvf-utils/vmcs.h:94:
+#define^IVMCS_GUEST_IA32_PERF_GLOBAL_CTRL 0x00002808$
ERROR: code indent should never use tabs
#1329: FILE: target/i386/hvf-utils/vmcs.h:95:
+#define^IVMCS_GUEST_PDPTE0^I^I0x0000280A$
ERROR: code indent should never use tabs
#1330: FILE: target/i386/hvf-utils/vmcs.h:96:
+#define^IVMCS_GUEST_PDPTE1^I^I0x0000280C$
ERROR: code indent should never use tabs
#1331: FILE: target/i386/hvf-utils/vmcs.h:97:
+#define^IVMCS_GUEST_PDPTE2^I^I0x0000280E$
ERROR: code indent should never use tabs
#1332: FILE: target/i386/hvf-utils/vmcs.h:98:
+#define^IVMCS_GUEST_PDPTE3^I^I0x00002810$
ERROR: code indent should never use tabs
#1335: FILE: target/i386/hvf-utils/vmcs.h:101:
+#define^IVMCS_HOST_IA32_PAT^I^I0x00002C00$
ERROR: code indent should never use tabs
#1336: FILE: target/i386/hvf-utils/vmcs.h:102:
+#define^IVMCS_HOST_IA32_EFER^I^I0x00002C02$
ERROR: code indent should never use tabs
#1337: FILE: target/i386/hvf-utils/vmcs.h:103:
+#define^IVMCS_HOST_IA32_PERF_GLOBAL_CTRL^I0x00002C04$
ERROR: code indent should never use tabs
#1340: FILE: target/i386/hvf-utils/vmcs.h:106:
+#define^IVMCS_PIN_BASED_CTLS^I^I0x00004000$
ERROR: code indent should never use tabs
#1341: FILE: target/i386/hvf-utils/vmcs.h:107:
+#define^IVMCS_PRI_PROC_BASED_CTLS^I0x00004002$
ERROR: code indent should never use tabs
#1342: FILE: target/i386/hvf-utils/vmcs.h:108:
+#define^IVMCS_EXCEPTION_BITMAP^I^I0x00004004$
ERROR: code indent should never use tabs
#1343: FILE: target/i386/hvf-utils/vmcs.h:109:
+#define^IVMCS_PF_ERROR_MASK^I^I0x00004006$
ERROR: code indent should never use tabs
#1344: FILE: target/i386/hvf-utils/vmcs.h:110:
+#define^IVMCS_PF_ERROR_MATCH^I^I0x00004008$
ERROR: code indent should never use tabs
#1345: FILE: target/i386/hvf-utils/vmcs.h:111:
+#define^IVMCS_CR3_TARGET_COUNT^I^I0x0000400A$
ERROR: code indent should never use tabs
#1346: FILE: target/i386/hvf-utils/vmcs.h:112:
+#define^IVMCS_EXIT_CTLS^I^I^I0x0000400C$
ERROR: code indent should never use tabs
#1347: FILE: target/i386/hvf-utils/vmcs.h:113:
+#define^IVMCS_EXIT_MSR_STORE_COUNT^I0x0000400E$
ERROR: code indent should never use tabs
#1348: FILE: target/i386/hvf-utils/vmcs.h:114:
+#define^IVMCS_EXIT_MSR_LOAD_COUNT^I0x00004010$
ERROR: code indent should never use tabs
#1349: FILE: target/i386/hvf-utils/vmcs.h:115:
+#define^IVMCS_ENTRY_CTLS^I^I^I0x00004012$
ERROR: code indent should never use tabs
#1350: FILE: target/i386/hvf-utils/vmcs.h:116:
+#define^IVMCS_ENTRY_MSR_LOAD_COUNT^I0x00004014$
ERROR: code indent should never use tabs
#1351: FILE: target/i386/hvf-utils/vmcs.h:117:
+#define^IVMCS_ENTRY_INTR_INFO^I^I0x00004016$
ERROR: code indent should never use tabs
#1352: FILE: target/i386/hvf-utils/vmcs.h:118:
+#define^IVMCS_ENTRY_EXCEPTION_ERROR^I0x00004018$
ERROR: code indent should never use tabs
#1353: FILE: target/i386/hvf-utils/vmcs.h:119:
+#define^IVMCS_ENTRY_INST_LENGTH^I^I0x0000401A$
ERROR: code indent should never use tabs
#1354: FILE: target/i386/hvf-utils/vmcs.h:120:
+#define^IVMCS_TPR_THRESHOLD^I^I0x0000401C$
ERROR: code indent should never use tabs
#1355: FILE: target/i386/hvf-utils/vmcs.h:121:
+#define^IVMCS_SEC_PROC_BASED_CTLS^I0x0000401E$
ERROR: code indent should never use tabs
#1356: FILE: target/i386/hvf-utils/vmcs.h:122:
+#define^IVMCS_PLE_GAP^I^I^I0x00004020$
ERROR: code indent should never use tabs
#1357: FILE: target/i386/hvf-utils/vmcs.h:123:
+#define^IVMCS_PLE_WINDOW^I^I^I0x00004022$
ERROR: code indent should never use tabs
#1360: FILE: target/i386/hvf-utils/vmcs.h:126:
+#define^IVMCS_INSTRUCTION_ERROR^I^I0x00004400$
ERROR: code indent should never use tabs
#1361: FILE: target/i386/hvf-utils/vmcs.h:127:
+#define^IVMCS_EXIT_REASON^I^I0x00004402$
ERROR: code indent should never use tabs
#1362: FILE: target/i386/hvf-utils/vmcs.h:128:
+#define^IVMCS_EXIT_INTR_INFO^I^I0x00004404$
ERROR: code indent should never use tabs
#1363: FILE: target/i386/hvf-utils/vmcs.h:129:
+#define^IVMCS_EXIT_INTR_ERRCODE^I^I0x00004406$
ERROR: code indent should never use tabs
#1364: FILE: target/i386/hvf-utils/vmcs.h:130:
+#define^IVMCS_IDT_VECTORING_INFO^I^I0x00004408$
ERROR: code indent should never use tabs
#1365: FILE: target/i386/hvf-utils/vmcs.h:131:
+#define^IVMCS_IDT_VECTORING_ERROR^I0x0000440A$
ERROR: code indent should never use tabs
#1366: FILE: target/i386/hvf-utils/vmcs.h:132:
+#define^IVMCS_EXIT_INSTRUCTION_LENGTH^I0x0000440C$
ERROR: code indent should never use tabs
#1367: FILE: target/i386/hvf-utils/vmcs.h:133:
+#define^IVMCS_EXIT_INSTRUCTION_INFO^I0x0000440E$
ERROR: code indent should never use tabs
#1370: FILE: target/i386/hvf-utils/vmcs.h:136:
+#define^IVMCS_GUEST_ES_LIMIT^I^I0x00004800$
ERROR: code indent should never use tabs
#1371: FILE: target/i386/hvf-utils/vmcs.h:137:
+#define^IVMCS_GUEST_CS_LIMIT^I^I0x00004802$
ERROR: code indent should never use tabs
#1372: FILE: target/i386/hvf-utils/vmcs.h:138:
+#define^IVMCS_GUEST_SS_LIMIT^I^I0x00004804$
ERROR: code indent should never use tabs
#1373: FILE: target/i386/hvf-utils/vmcs.h:139:
+#define^IVMCS_GUEST_DS_LIMIT^I^I0x00004806$
ERROR: code indent should never use tabs
#1374: FILE: target/i386/hvf-utils/vmcs.h:140:
+#define^IVMCS_GUEST_FS_LIMIT^I^I0x00004808$
ERROR: code indent should never use tabs
#1375: FILE: target/i386/hvf-utils/vmcs.h:141:
+#define^IVMCS_GUEST_GS_LIMIT^I^I0x0000480A$
ERROR: code indent should never use tabs
#1376: FILE: target/i386/hvf-utils/vmcs.h:142:
+#define^IVMCS_GUEST_LDTR_LIMIT^I^I0x0000480C$
ERROR: code indent should never use tabs
#1377: FILE: target/i386/hvf-utils/vmcs.h:143:
+#define^IVMCS_GUEST_TR_LIMIT^I^I0x0000480E$
ERROR: code indent should never use tabs
#1378: FILE: target/i386/hvf-utils/vmcs.h:144:
+#define^IVMCS_GUEST_GDTR_LIMIT^I^I0x00004810$
ERROR: code indent should never use tabs
#1379: FILE: target/i386/hvf-utils/vmcs.h:145:
+#define^IVMCS_GUEST_IDTR_LIMIT^I^I0x00004812$
ERROR: code indent should never use tabs
#1380: FILE: target/i386/hvf-utils/vmcs.h:146:
+#define^IVMCS_GUEST_ES_ACCESS_RIGHTS^I0x00004814$
ERROR: code indent should never use tabs
#1381: FILE: target/i386/hvf-utils/vmcs.h:147:
+#define^IVMCS_GUEST_CS_ACCESS_RIGHTS^I0x00004816$
ERROR: code indent should never use tabs
#1382: FILE: target/i386/hvf-utils/vmcs.h:148:
+#define^IVMCS_GUEST_SS_ACCESS_RIGHTS^I0x00004818$
ERROR: code indent should never use tabs
#1383: FILE: target/i386/hvf-utils/vmcs.h:149:
+#define^IVMCS_GUEST_DS_ACCESS_RIGHTS^I0x0000481A$
ERROR: code indent should never use tabs
#1384: FILE: target/i386/hvf-utils/vmcs.h:150:
+#define^IVMCS_GUEST_FS_ACCESS_RIGHTS^I0x0000481C$
ERROR: code indent should never use tabs
#1385: FILE: target/i386/hvf-utils/vmcs.h:151:
+#define^IVMCS_GUEST_GS_ACCESS_RIGHTS^I0x0000481E$
ERROR: code indent should never use tabs
#1386: FILE: target/i386/hvf-utils/vmcs.h:152:
+#define^IVMCS_GUEST_LDTR_ACCESS_RIGHTS^I0x00004820$
ERROR: code indent should never use tabs
#1387: FILE: target/i386/hvf-utils/vmcs.h:153:
+#define^IVMCS_GUEST_TR_ACCESS_RIGHTS^I0x00004822$
ERROR: code indent should never use tabs
#1388: FILE: target/i386/hvf-utils/vmcs.h:154:
+#define^IVMCS_GUEST_INTERRUPTIBILITY^I0x00004824$
ERROR: code indent should never use tabs
#1389: FILE: target/i386/hvf-utils/vmcs.h:155:
+#define^IVMCS_GUEST_ACTIVITY^I^I0x00004826$
ERROR: code indent should never use tabs
#1390: FILE: target/i386/hvf-utils/vmcs.h:156:
+#define VMCS_GUEST_SMBASE^I^I0x00004828$
ERROR: code indent should never use tabs
#1391: FILE: target/i386/hvf-utils/vmcs.h:157:
+#define^IVMCS_GUEST_IA32_SYSENTER_CS^I0x0000482A$
ERROR: code indent should never use tabs
#1392: FILE: target/i386/hvf-utils/vmcs.h:158:
+#define^IVMCS_PREEMPTION_TIMER_VALUE^I0x0000482E$
ERROR: code indent should never use tabs
#1395: FILE: target/i386/hvf-utils/vmcs.h:161:
+#define^IVMCS_HOST_IA32_SYSENTER_CS^I0x00004C00$
ERROR: code indent should never use tabs
#1398: FILE: target/i386/hvf-utils/vmcs.h:164:
+#define^IVMCS_CR0_MASK^I^I^I0x00006000$
ERROR: code indent should never use tabs
#1399: FILE: target/i386/hvf-utils/vmcs.h:165:
+#define^IVMCS_CR4_MASK^I^I^I0x00006002$
ERROR: code indent should never use tabs
#1400: FILE: target/i386/hvf-utils/vmcs.h:166:
+#define^IVMCS_CR0_SHADOW^I^I^I0x00006004$
ERROR: code indent should never use tabs
#1401: FILE: target/i386/hvf-utils/vmcs.h:167:
+#define^IVMCS_CR4_SHADOW^I^I^I0x00006006$
ERROR: code indent should never use tabs
#1402: FILE: target/i386/hvf-utils/vmcs.h:168:
+#define^IVMCS_CR3_TARGET0^I^I0x00006008$
ERROR: code indent should never use tabs
#1403: FILE: target/i386/hvf-utils/vmcs.h:169:
+#define^IVMCS_CR3_TARGET1^I^I0x0000600A$
ERROR: code indent should never use tabs
#1404: FILE: target/i386/hvf-utils/vmcs.h:170:
+#define^IVMCS_CR3_TARGET2^I^I0x0000600C$
ERROR: code indent should never use tabs
#1405: FILE: target/i386/hvf-utils/vmcs.h:171:
+#define^IVMCS_CR3_TARGET3^I^I0x0000600E$
ERROR: code indent should never use tabs
#1408: FILE: target/i386/hvf-utils/vmcs.h:174:
+#define^IVMCS_EXIT_QUALIFICATION^I^I0x00006400$
ERROR: code indent should never use tabs
#1409: FILE: target/i386/hvf-utils/vmcs.h:175:
+#define^IVMCS_IO_RCX^I^I^I0x00006402$
ERROR: code indent should never use tabs
#1410: FILE: target/i386/hvf-utils/vmcs.h:176:
+#define^IVMCS_IO_RSI^I^I^I0x00006404$
ERROR: code indent should never use tabs
#1411: FILE: target/i386/hvf-utils/vmcs.h:177:
+#define^IVMCS_IO_RDI^I^I^I0x00006406$
ERROR: code indent should never use tabs
#1412: FILE: target/i386/hvf-utils/vmcs.h:178:
+#define^IVMCS_IO_RIP^I^I^I0x00006408$
ERROR: code indent should never use tabs
#1413: FILE: target/i386/hvf-utils/vmcs.h:179:
+#define^IVMCS_GUEST_LINEAR_ADDRESS^I0x0000640A$
ERROR: code indent should never use tabs
#1416: FILE: target/i386/hvf-utils/vmcs.h:182:
+#define^IVMCS_GUEST_CR0^I^I^I0x00006800$
ERROR: code indent should never use tabs
#1417: FILE: target/i386/hvf-utils/vmcs.h:183:
+#define^IVMCS_GUEST_CR3^I^I^I0x00006802$
ERROR: code indent should never use tabs
#1418: FILE: target/i386/hvf-utils/vmcs.h:184:
+#define^IVMCS_GUEST_CR4^I^I^I0x00006804$
ERROR: code indent should never use tabs
#1419: FILE: target/i386/hvf-utils/vmcs.h:185:
+#define^IVMCS_GUEST_ES_BASE^I^I0x00006806$
ERROR: code indent should never use tabs
#1420: FILE: target/i386/hvf-utils/vmcs.h:186:
+#define^IVMCS_GUEST_CS_BASE^I^I0x00006808$
ERROR: code indent should never use tabs
#1421: FILE: target/i386/hvf-utils/vmcs.h:187:
+#define^IVMCS_GUEST_SS_BASE^I^I0x0000680A$
ERROR: code indent should never use tabs
#1422: FILE: target/i386/hvf-utils/vmcs.h:188:
+#define^IVMCS_GUEST_DS_BASE^I^I0x0000680C$
ERROR: code indent should never use tabs
#1423: FILE: target/i386/hvf-utils/vmcs.h:189:
+#define^IVMCS_GUEST_FS_BASE^I^I0x0000680E$
ERROR: code indent should never use tabs
#1424: FILE: target/i386/hvf-utils/vmcs.h:190:
+#define^IVMCS_GUEST_GS_BASE^I^I0x00006810$
ERROR: code indent should never use tabs
#1425: FILE: target/i386/hvf-utils/vmcs.h:191:
+#define^IVMCS_GUEST_LDTR_BASE^I^I0x00006812$
ERROR: code indent should never use tabs
#1426: FILE: target/i386/hvf-utils/vmcs.h:192:
+#define^IVMCS_GUEST_TR_BASE^I^I0x00006814$
ERROR: code indent should never use tabs
#1427: FILE: target/i386/hvf-utils/vmcs.h:193:
+#define^IVMCS_GUEST_GDTR_BASE^I^I0x00006816$
ERROR: code indent should never use tabs
#1428: FILE: target/i386/hvf-utils/vmcs.h:194:
+#define^IVMCS_GUEST_IDTR_BASE^I^I0x00006818$
ERROR: code indent should never use tabs
#1429: FILE: target/i386/hvf-utils/vmcs.h:195:
+#define^IVMCS_GUEST_DR7^I^I^I0x0000681A$
ERROR: code indent should never use tabs
#1430: FILE: target/i386/hvf-utils/vmcs.h:196:
+#define^IVMCS_GUEST_RSP^I^I^I0x0000681C$
ERROR: code indent should never use tabs
#1431: FILE: target/i386/hvf-utils/vmcs.h:197:
+#define^IVMCS_GUEST_RIP^I^I^I0x0000681E$
ERROR: code indent should never use tabs
#1432: FILE: target/i386/hvf-utils/vmcs.h:198:
+#define^IVMCS_GUEST_RFLAGS^I^I0x00006820$
ERROR: code indent should never use tabs
#1433: FILE: target/i386/hvf-utils/vmcs.h:199:
+#define^IVMCS_GUEST_PENDING_DBG_EXCEPTIONS 0x00006822$
ERROR: code indent should never use tabs
#1434: FILE: target/i386/hvf-utils/vmcs.h:200:
+#define^IVMCS_GUEST_IA32_SYSENTER_ESP^I0x00006824$
ERROR: code indent should never use tabs
#1435: FILE: target/i386/hvf-utils/vmcs.h:201:
+#define^IVMCS_GUEST_IA32_SYSENTER_EIP^I0x00006826$
ERROR: code indent should never use tabs
#1438: FILE: target/i386/hvf-utils/vmcs.h:204:
+#define^IVMCS_HOST_CR0^I^I^I0x00006C00$
ERROR: code indent should never use tabs
#1439: FILE: target/i386/hvf-utils/vmcs.h:205:
+#define^IVMCS_HOST_CR3^I^I^I0x00006C02$
ERROR: code indent should never use tabs
#1440: FILE: target/i386/hvf-utils/vmcs.h:206:
+#define^IVMCS_HOST_CR4^I^I^I0x00006C04$
ERROR: code indent should never use tabs
#1441: FILE: target/i386/hvf-utils/vmcs.h:207:
+#define^IVMCS_HOST_FS_BASE^I^I0x00006C06$
ERROR: code indent should never use tabs
#1442: FILE: target/i386/hvf-utils/vmcs.h:208:
+#define^IVMCS_HOST_GS_BASE^I^I0x00006C08$
ERROR: code indent should never use tabs
#1443: FILE: target/i386/hvf-utils/vmcs.h:209:
+#define^IVMCS_HOST_TR_BASE^I^I0x00006C0A$
ERROR: code indent should never use tabs
#1444: FILE: target/i386/hvf-utils/vmcs.h:210:
+#define^IVMCS_HOST_GDTR_BASE^I^I0x00006C0C$
ERROR: code indent should never use tabs
#1445: FILE: target/i386/hvf-utils/vmcs.h:211:
+#define^IVMCS_HOST_IDTR_BASE^I^I0x00006C0E$
ERROR: code indent should never use tabs
#1446: FILE: target/i386/hvf-utils/vmcs.h:212:
+#define^IVMCS_HOST_IA32_SYSENTER_ESP^I0x00006C10$
ERROR: code indent should never use tabs
#1447: FILE: target/i386/hvf-utils/vmcs.h:213:
+#define^IVMCS_HOST_IA32_SYSENTER_EIP^I0x00006C12$
ERROR: code indent should never use tabs
#1448: FILE: target/i386/hvf-utils/vmcs.h:214:
+#define^IVMCS_HOST_RSP^I^I^I0x00006C14$
ERROR: code indent should never use tabs
#1449: FILE: target/i386/hvf-utils/vmcs.h:215:
+#define^IVMCS_HOST_RIP^I^I^I0x00006c16$
ERROR: code indent should never use tabs
#1454: FILE: target/i386/hvf-utils/vmcs.h:220:
+#define^IVMRESUME_WITH_NON_LAUNCHED_VMCS^I5$
ERROR: code indent should never use tabs
#1459: FILE: target/i386/hvf-utils/vmcs.h:225:
+#define EXIT_REASON_EXCEPTION^I^I0$
ERROR: code indent should never use tabs
#1460: FILE: target/i386/hvf-utils/vmcs.h:226:
+#define EXIT_REASON_EXT_INTR^I^I1$
ERROR: code indent should never use tabs
#1461: FILE: target/i386/hvf-utils/vmcs.h:227:
+#define EXIT_REASON_TRIPLE_FAULT^I2$
ERROR: code indent should never use tabs
#1462: FILE: target/i386/hvf-utils/vmcs.h:228:
+#define EXIT_REASON_INIT^I^I3$
ERROR: code indent should never use tabs
#1463: FILE: target/i386/hvf-utils/vmcs.h:229:
+#define EXIT_REASON_SIPI^I^I4$
ERROR: code indent should never use tabs
#1464: FILE: target/i386/hvf-utils/vmcs.h:230:
+#define EXIT_REASON_IO_SMI^I^I5$
ERROR: code indent should never use tabs
#1465: FILE: target/i386/hvf-utils/vmcs.h:231:
+#define EXIT_REASON_SMI^I^I^I6$
ERROR: code indent should never use tabs
#1466: FILE: target/i386/hvf-utils/vmcs.h:232:
+#define EXIT_REASON_INTR_WINDOW^I^I7$
ERROR: code indent should never use tabs
#1467: FILE: target/i386/hvf-utils/vmcs.h:233:
+#define EXIT_REASON_NMI_WINDOW^I^I8$
ERROR: code indent should never use tabs
#1468: FILE: target/i386/hvf-utils/vmcs.h:234:
+#define EXIT_REASON_TASK_SWITCH^I^I9$
ERROR: code indent should never use tabs
#1469: FILE: target/i386/hvf-utils/vmcs.h:235:
+#define EXIT_REASON_CPUID^I^I10$
ERROR: code indent should never use tabs
#1470: FILE: target/i386/hvf-utils/vmcs.h:236:
+#define EXIT_REASON_GETSEC^I^I11$
ERROR: code indent should never use tabs
#1471: FILE: target/i386/hvf-utils/vmcs.h:237:
+#define EXIT_REASON_HLT^I^I^I12$
ERROR: code indent should never use tabs
#1472: FILE: target/i386/hvf-utils/vmcs.h:238:
+#define EXIT_REASON_INVD^I^I13$
ERROR: code indent should never use tabs
#1473: FILE: target/i386/hvf-utils/vmcs.h:239:
+#define EXIT_REASON_INVLPG^I^I14$
ERROR: code indent should never use tabs
#1474: FILE: target/i386/hvf-utils/vmcs.h:240:
+#define EXIT_REASON_RDPMC^I^I15$
ERROR: code indent should never use tabs
#1475: FILE: target/i386/hvf-utils/vmcs.h:241:
+#define EXIT_REASON_RDTSC^I^I16$
ERROR: code indent should never use tabs
#1476: FILE: target/i386/hvf-utils/vmcs.h:242:
+#define EXIT_REASON_RSM^I^I^I17$
ERROR: code indent should never use tabs
#1477: FILE: target/i386/hvf-utils/vmcs.h:243:
+#define EXIT_REASON_VMCALL^I^I18$
ERROR: code indent should never use tabs
#1478: FILE: target/i386/hvf-utils/vmcs.h:244:
+#define EXIT_REASON_VMCLEAR^I^I19$
ERROR: code indent should never use tabs
#1479: FILE: target/i386/hvf-utils/vmcs.h:245:
+#define EXIT_REASON_VMLAUNCH^I^I20$
ERROR: code indent should never use tabs
#1480: FILE: target/i386/hvf-utils/vmcs.h:246:
+#define EXIT_REASON_VMPTRLD^I^I21$
ERROR: code indent should never use tabs
#1481: FILE: target/i386/hvf-utils/vmcs.h:247:
+#define EXIT_REASON_VMPTRST^I^I22$
ERROR: code indent should never use tabs
#1482: FILE: target/i386/hvf-utils/vmcs.h:248:
+#define EXIT_REASON_VMREAD^I^I23$
ERROR: code indent should never use tabs
#1483: FILE: target/i386/hvf-utils/vmcs.h:249:
+#define EXIT_REASON_VMRESUME^I^I24$
ERROR: code indent should never use tabs
#1484: FILE: target/i386/hvf-utils/vmcs.h:250:
+#define EXIT_REASON_VMWRITE^I^I25$
ERROR: code indent should never use tabs
#1485: FILE: target/i386/hvf-utils/vmcs.h:251:
+#define EXIT_REASON_VMXOFF^I^I26$
ERROR: code indent should never use tabs
#1486: FILE: target/i386/hvf-utils/vmcs.h:252:
+#define EXIT_REASON_VMXON^I^I27$
ERROR: code indent should never use tabs
#1487: FILE: target/i386/hvf-utils/vmcs.h:253:
+#define EXIT_REASON_CR_ACCESS^I^I28$
ERROR: code indent should never use tabs
#1488: FILE: target/i386/hvf-utils/vmcs.h:254:
+#define EXIT_REASON_DR_ACCESS^I^I29$
ERROR: code indent should never use tabs
#1489: FILE: target/i386/hvf-utils/vmcs.h:255:
+#define EXIT_REASON_INOUT^I^I30$
ERROR: code indent should never use tabs
#1490: FILE: target/i386/hvf-utils/vmcs.h:256:
+#define EXIT_REASON_RDMSR^I^I31$
ERROR: code indent should never use tabs
#1491: FILE: target/i386/hvf-utils/vmcs.h:257:
+#define EXIT_REASON_WRMSR^I^I32$
ERROR: code indent should never use tabs
#1492: FILE: target/i386/hvf-utils/vmcs.h:258:
+#define EXIT_REASON_INVAL_VMCS^I^I33$
ERROR: code indent should never use tabs
#1493: FILE: target/i386/hvf-utils/vmcs.h:259:
+#define EXIT_REASON_INVAL_MSR^I^I34$
ERROR: code indent should never use tabs
#1494: FILE: target/i386/hvf-utils/vmcs.h:260:
+#define EXIT_REASON_MWAIT^I^I36$
ERROR: code indent should never use tabs
#1495: FILE: target/i386/hvf-utils/vmcs.h:261:
+#define EXIT_REASON_MTF^I^I^I37$
ERROR: code indent should never use tabs
#1496: FILE: target/i386/hvf-utils/vmcs.h:262:
+#define EXIT_REASON_MONITOR^I^I39$
ERROR: code indent should never use tabs
#1497: FILE: target/i386/hvf-utils/vmcs.h:263:
+#define EXIT_REASON_PAUSE^I^I40$
ERROR: code indent should never use tabs
#1498: FILE: target/i386/hvf-utils/vmcs.h:264:
+#define EXIT_REASON_MCE_DURING_ENTRY^I41$
ERROR: code indent should never use tabs
#1499: FILE: target/i386/hvf-utils/vmcs.h:265:
+#define EXIT_REASON_TPR^I^I^I43$
ERROR: code indent should never use tabs
#1500: FILE: target/i386/hvf-utils/vmcs.h:266:
+#define EXIT_REASON_APIC_ACCESS^I^I44$
ERROR: code indent should never use tabs
#1501: FILE: target/i386/hvf-utils/vmcs.h:267:
+#define^IEXIT_REASON_VIRTUALIZED_EOI^I45$
ERROR: code indent should never use tabs
#1502: FILE: target/i386/hvf-utils/vmcs.h:268:
+#define EXIT_REASON_GDTR_IDTR^I^I46$
ERROR: code indent should never use tabs
#1503: FILE: target/i386/hvf-utils/vmcs.h:269:
+#define EXIT_REASON_LDTR_TR^I^I47$
ERROR: code indent should never use tabs
#1504: FILE: target/i386/hvf-utils/vmcs.h:270:
+#define EXIT_REASON_EPT_FAULT^I^I48$
ERROR: code indent should never use tabs
#1505: FILE: target/i386/hvf-utils/vmcs.h:271:
+#define EXIT_REASON_EPT_MISCONFIG^I49$
ERROR: code indent should never use tabs
#1506: FILE: target/i386/hvf-utils/vmcs.h:272:
+#define EXIT_REASON_INVEPT^I^I50$
ERROR: code indent should never use tabs
#1507: FILE: target/i386/hvf-utils/vmcs.h:273:
+#define EXIT_REASON_RDTSCP^I^I51$
ERROR: code indent should never use tabs
#1508: FILE: target/i386/hvf-utils/vmcs.h:274:
+#define EXIT_REASON_VMX_PREEMPT^I^I52$
ERROR: code indent should never use tabs
#1509: FILE: target/i386/hvf-utils/vmcs.h:275:
+#define EXIT_REASON_INVVPID^I^I53$
ERROR: code indent should never use tabs
#1510: FILE: target/i386/hvf-utils/vmcs.h:276:
+#define EXIT_REASON_WBINVD^I^I54$
ERROR: code indent should never use tabs
#1511: FILE: target/i386/hvf-utils/vmcs.h:277:
+#define EXIT_REASON_XSETBV^I^I55$
ERROR: code indent should never use tabs
#1512: FILE: target/i386/hvf-utils/vmcs.h:278:
+#define^IEXIT_REASON_APIC_WRITE^I^I56$
ERROR: code indent should never use tabs
#1519: FILE: target/i386/hvf-utils/vmcs.h:285:
+#define^IEXIT_QUAL_NMIUDTI^I(1 << 12)$
ERROR: code indent should never use tabs
#1523: FILE: target/i386/hvf-utils/vmcs.h:289:
+#define^IVMCS_INTR_VALID^I^I(1U << 31)$
ERROR: code indent should never use tabs
#1524: FILE: target/i386/hvf-utils/vmcs.h:290:
+#define^IVMCS_INTR_T_MASK^I0x700^I^I/* Interruption-info type */$
ERROR: code indent should never use tabs
#1525: FILE: target/i386/hvf-utils/vmcs.h:291:
+#define^IVMCS_INTR_T_HWINTR^I(0 << 8)$
ERROR: code indent should never use tabs
#1526: FILE: target/i386/hvf-utils/vmcs.h:292:
+#define^IVMCS_INTR_T_NMI^I^I(2 << 8)$
ERROR: code indent should never use tabs
#1527: FILE: target/i386/hvf-utils/vmcs.h:293:
+#define^IVMCS_INTR_T_HWEXCEPTION^I(3 << 8)$
ERROR: code indent should never use tabs
#1528: FILE: target/i386/hvf-utils/vmcs.h:294:
+#define^IVMCS_INTR_T_SWINTR^I(4 << 8)$
ERROR: code indent should never use tabs
#1529: FILE: target/i386/hvf-utils/vmcs.h:295:
+#define^IVMCS_INTR_T_PRIV_SWEXCEPTION (5 << 8)$
ERROR: code indent should never use tabs
#1530: FILE: target/i386/hvf-utils/vmcs.h:296:
+#define^IVMCS_INTR_T_SWEXCEPTION^I(6 << 8)$
ERROR: code indent should never use tabs
#1531: FILE: target/i386/hvf-utils/vmcs.h:297:
+#define^IVMCS_INTR_DEL_ERRCODE^I(1 << 11)$
ERROR: code indent should never use tabs
#1536: FILE: target/i386/hvf-utils/vmcs.h:302:
+#define^IVMCS_IDT_VEC_VALID (1U << 31)$
ERROR: code indent should never use tabs
#1537: FILE: target/i386/hvf-utils/vmcs.h:303:
+#define^IVMCS_IDT_VEC_TYPE 0x700$
ERROR: code indent should never use tabs
#1538: FILE: target/i386/hvf-utils/vmcs.h:304:
+#define^IVMCS_IDT_VEC_ERRCODE_VALID^I(1U << 11)$
ERROR: code indent should never use tabs
#1539: FILE: target/i386/hvf-utils/vmcs.h:305:
+#define^IVMCS_IDT_VEC_HWINTR (0 << 8)$
ERROR: code indent should never use tabs
#1540: FILE: target/i386/hvf-utils/vmcs.h:306:
+#define^IVMCS_IDT_VEC_NMI (2 << 8)$
ERROR: code indent should never use tabs
#1541: FILE: target/i386/hvf-utils/vmcs.h:307:
+#define^IVMCS_IDT_VEC_HWEXCEPTION^I(3 << 8)$
ERROR: code indent should never use tabs
#1542: FILE: target/i386/hvf-utils/vmcs.h:308:
+#define^IVMCS_IDT_VEC_SWINTR (4 << 8)$
ERROR: code indent should never use tabs
#1547: FILE: target/i386/hvf-utils/vmcs.h:313:
+#define^IVMCS_INTERRUPTIBILITY_STI_BLOCKING^I(1 << 0)$
ERROR: code indent should never use tabs
#1548: FILE: target/i386/hvf-utils/vmcs.h:314:
+#define^IVMCS_INTERRUPTIBILITY_MOVSS_BLOCKING^I(1 << 1)$
ERROR: code indent should never use tabs
#1549: FILE: target/i386/hvf-utils/vmcs.h:315:
+#define^IVMCS_INTERRUPTIBILITY_SMI_BLOCKING^I(1 << 2)$
ERROR: code indent should never use tabs
#1550: FILE: target/i386/hvf-utils/vmcs.h:316:
+#define^IVMCS_INTERRUPTIBILITY_NMI_BLOCKING^I(1 << 3)$
ERROR: code indent should never use tabs
#1555: FILE: target/i386/hvf-utils/vmcs.h:321:
+#define^IEXIT_QUAL_NMI_WHILE_STI_BLOCKING^I3$
ERROR: code indent should never use tabs
#1560: FILE: target/i386/hvf-utils/vmcs.h:326:
+#define^IEPT_VIOLATION_DATA_READ^I^I(1UL << 0)$
ERROR: code indent should never use tabs
#1561: FILE: target/i386/hvf-utils/vmcs.h:327:
+#define^IEPT_VIOLATION_DATA_WRITE^I(1UL << 1)$
ERROR: code indent should never use tabs
#1562: FILE: target/i386/hvf-utils/vmcs.h:328:
+#define^IEPT_VIOLATION_INST_FETCH^I(1UL << 2)$
ERROR: code indent should never use tabs
#1563: FILE: target/i386/hvf-utils/vmcs.h:329:
+#define^IEPT_VIOLATION_GPA_READABLE^I(1UL << 3)$
ERROR: code indent should never use tabs
#1564: FILE: target/i386/hvf-utils/vmcs.h:330:
+#define^IEPT_VIOLATION_GPA_WRITEABLE^I(1UL << 4)$
ERROR: code indent should never use tabs
#1565: FILE: target/i386/hvf-utils/vmcs.h:331:
+#define^IEPT_VIOLATION_GPA_EXECUTABLE^I(1UL << 5)$
ERROR: code indent should never use tabs
#1566: FILE: target/i386/hvf-utils/vmcs.h:332:
+#define^IEPT_VIOLATION_GLA_VALID^I^I(1UL << 7)$
ERROR: code indent should never use tabs
#1567: FILE: target/i386/hvf-utils/vmcs.h:333:
+#define^IEPT_VIOLATION_XLAT_VALID^I(1UL << 8)$
ERROR: code indent should never use tabs
#1572: FILE: target/i386/hvf-utils/vmcs.h:338:
+#define^IAPIC_ACCESS_OFFSET(qual)^I((qual) & 0xFFF)$
ERROR: code indent should never use tabs
#1573: FILE: target/i386/hvf-utils/vmcs.h:339:
+#define^IAPIC_ACCESS_TYPE(qual)^I^I(((qual) >> 12) & 0xF)$
ERROR: code indent should never use tabs
#1578: FILE: target/i386/hvf-utils/vmcs.h:344:
+#define^IAPIC_WRITE_OFFSET(qual)^I^I((qual) & 0xFFF)$
ERROR: code indent should never use tabs
#1596: FILE: target/i386/hvf-utils/vmcs.h:362:
+^ITSR_CALL,$
ERROR: code indent should never use tabs
#1597: FILE: target/i386/hvf-utils/vmcs.h:363:
+^ITSR_IRET,$
ERROR: code indent should never use tabs
#1599: FILE: target/i386/hvf-utils/vmcs.h:365:
+^ITSR_IDT_GATE,^I/* task gate in IDT */$
ERROR: inline keyword should sit between storage class and type
#1642: FILE: target/i386/hvf-utils/vmx.h:34:
+static uint64_t inline rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg)
ERROR: code indent should never use tabs
#1644: FILE: target/i386/hvf-utils/vmx.h:36:
+^Iuint64_t v;$
ERROR: code indent should never use tabs
#1646: FILE: target/i386/hvf-utils/vmx.h:38:
+^Iif (hv_vcpu_read_register(vcpu, reg, &v)) {$
ERROR: code indent should never use tabs
#1647: FILE: target/i386/hvf-utils/vmx.h:39:
+^I^Iabort();$
ERROR: code indent should never use tabs
#1648: FILE: target/i386/hvf-utils/vmx.h:40:
+^I}$
ERROR: code indent should never use tabs
#1650: FILE: target/i386/hvf-utils/vmx.h:42:
+^Ireturn v;$
ERROR: inline keyword should sit between storage class and type
#1654: FILE: target/i386/hvf-utils/vmx.h:46:
+static void inline wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v)
ERROR: code indent should never use tabs
#1656: FILE: target/i386/hvf-utils/vmx.h:48:
+^Iif (hv_vcpu_write_register(vcpu, reg, v)) {$
ERROR: code indent should never use tabs
#1657: FILE: target/i386/hvf-utils/vmx.h:49:
+^I^Iabort();$
ERROR: code indent should never use tabs
#1658: FILE: target/i386/hvf-utils/vmx.h:50:
+^I}$
ERROR: inline keyword should sit between storage class and type
#1662: FILE: target/i386/hvf-utils/vmx.h:54:
+static uint64_t inline rvmcs(hv_vcpuid_t vcpu, uint32_t field)
ERROR: code indent should never use tabs
#1664: FILE: target/i386/hvf-utils/vmx.h:56:
+^Iuint64_t v;$
ERROR: code indent should never use tabs
#1666: FILE: target/i386/hvf-utils/vmx.h:58:
+^Ihv_vmx_vcpu_read_vmcs(vcpu, field, &v);$
ERROR: code indent should never use tabs
#1668: FILE: target/i386/hvf-utils/vmx.h:60:
+^Ireturn v;$
ERROR: inline keyword should sit between storage class and type
#1672: FILE: target/i386/hvf-utils/vmx.h:64:
+static void inline wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v)
ERROR: code indent should never use tabs
#1674: FILE: target/i386/hvf-utils/vmx.h:66:
+^Ihv_vmx_vcpu_write_vmcs(vcpu, field, v);$
ERROR: inline keyword should sit between storage class and type
#1678: FILE: target/i386/hvf-utils/vmx.h:70:
+static uint64_t inline cap2ctrl(uint64_t cap, uint64_t ctrl)
ERROR: code indent should never use tabs
#1680: FILE: target/i386/hvf-utils/vmx.h:72:
+^Ireturn (ctrl | (cap & 0xffffffff)) & (cap >> 32);$
WARNING: line over 80 characters
#1702: FILE: target/i386/hvf-utils/vmx.h:94:
+ wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | VM_ENTRY_GUEST_LMA);
WARNING: line over 80 characters
#1705: FILE: target/i386/hvf-utils/vmx.h:97:
+ if ((efer & EFER_LME) && (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
ERROR: line over 90 characters
#1706: FILE: target/i386/hvf-utils/vmx.h:98:
+ wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS);
ERROR: inline keyword should sit between storage class and type
#1721: FILE: target/i386/hvf-utils/vmx.h:113:
+static void inline macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
WARNING: line over 80 characters
#1728: FILE: target/i386/hvf-utils/vmx.h:120:
+ if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & EFER_LME))
ERROR: braces {} are necessary for all arms of this statement
#1728: FILE: target/i386/hvf-utils/vmx.h:120:
+ if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & EFER_LME))
[...]
WARNING: line over 80 characters
#1729: FILE: target/i386/hvf-utils/vmx.h:121:
+ address_space_rw(&address_space_memory, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
ERROR: braces {} are necessary even for single statement blocks
#1733: FILE: target/i386/hvf-utils/vmx.h:125:
+ for (i = 0; i < 4; i++)
+ wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
ERROR: spaces required around that '|' (ctx:VxW)
#1740: FILE: target/i386/hvf-utils/vmx.h:132:
+ wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE| CR0_ET);
^
ERROR: suspect code indent for conditional statements (8, 13)
#1743: FILE: target/i386/hvf-utils/vmx.h:135:
+ if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG))
+ enter_long_mode(vcpu, cr0, efer);
ERROR: braces {} are necessary for all arms of this statement
#1743: FILE: target/i386/hvf-utils/vmx.h:135:
+ if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG))
[...]
ERROR: braces {} are necessary for all arms of this statement
#1745: FILE: target/i386/hvf-utils/vmx.h:137:
+ if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG))
[...]
ERROR: inline keyword should sit between storage class and type
#1753: FILE: target/i386/hvf-utils/vmx.h:145:
+static void inline macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
ERROR: inline keyword should sit between storage class and type
#1764: FILE: target/i386/hvf-utils/vmx.h:156:
+static void inline macvm_set_rip(CPUState *cpu, uint64_t rip)
WARNING: line over 80 characters
#1773: FILE: target/i386/hvf-utils/vmx.h:165:
+ if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING))
ERROR: braces {} are necessary for all arms of this statement
#1773: FILE: target/i386/hvf-utils/vmx.h:165:
+ if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING))
[...]
ERROR: line over 90 characters
#1775: FILE: target/i386/hvf-utils/vmx.h:167:
+ val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
ERROR: inline keyword should sit between storage class and type
#1778: FILE: target/i386/hvf-utils/vmx.h:170:
+static void inline vmx_clear_nmi_blocking(CPUState *cpu)
ERROR: inline keyword should sit between storage class and type
#1785: FILE: target/i386/hvf-utils/vmx.h:177:
+static void inline vmx_set_nmi_blocking(CPUState *cpu)
ERROR: inline keyword should sit between storage class and type
#1792: FILE: target/i386/hvf-utils/vmx.h:184:
+static void inline vmx_set_nmi_window_exiting(CPUState *cpu)
ERROR: line over 90 characters
#1796: FILE: target/i386/hvf-utils/vmx.h:188:
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
ERROR: inline keyword should sit between storage class and type
#1800: FILE: target/i386/hvf-utils/vmx.h:192:
+static void inline vmx_clear_nmi_window_exiting(CPUState *cpu)
ERROR: line over 90 characters
#1805: FILE: target/i386/hvf-utils/vmx.h:197:
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
ERROR: line over 90 characters
#1863: FILE: target/i386/hvf-utils/x86.c:49:
+bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
ERROR: do not use C99 // comments
#1869: FILE: target/i386/hvf-utils/x86.c:55:
+ // valid gdt descriptors start from index 1
ERROR: braces {} are necessary for all arms of this statement
#1870: FILE: target/i386/hvf-utils/x86.c:56:
+ if (!sel.index && GDT_SEL == sel.ti)
[...]
ERROR: braces {} are necessary for all arms of this statement
#1881: FILE: target/i386/hvf-utils/x86.c:67:
+ if (sel.index * 8 >= limit)
[...]
ERROR: line over 90 characters
#1888: FILE: target/i386/hvf-utils/x86.c:74:
+bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
ERROR: trailing whitespace
#1892: FILE: target/i386/hvf-utils/x86.c:78:
+ $
ERROR: trailing whitespace
#1900: FILE: target/i386/hvf-utils/x86.c:86:
+ $
ERROR: __func__ should be used instead of gcc specific __FUNCTION__
#1902: FILE: target/i386/hvf-utils/x86.c:88:
+ printf("%s: gdt limit\n", __FUNCTION__);
WARNING: line over 80 characters
#1909: FILE: target/i386/hvf-utils/x86.c:95:
+bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate)
ERROR: __func__ should be used instead of gcc specific __FUNCTION__
#1916: FILE: target/i386/hvf-utils/x86.c:102:
+ printf("%s: idt limit\n", __FUNCTION__);
ERROR: return is not a function, parentheses are not required
#1937: FILE: target/i386/hvf-utils/x86.c:123:
+ return (x86_is_protected(cpu) && (RFLAGS(cpu) & RFLAGS_VM));
WARNING: line over 80 characters
#1970: FILE: target/i386/hvf-utils/x86.c:156:
+addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg)
ERROR: switch and case should be at the same indent
#1972: FILE: target/i386/hvf-utils/x86.c:158:
+ switch (size) {
+ case 2:
[...]
+ case 4:
[...]
+ default:
ERROR: do not use C99 // comments
#2022: FILE: target/i386/hvf-utils/x86.h:28:
+// exceptions
ERROR: do not use C99 // comments
#2024: FILE: target/i386/hvf-utils/x86.h:30:
+ EXCEPTION_DE, // divide error
ERROR: do not use C99 // comments
#2025: FILE: target/i386/hvf-utils/x86.h:31:
+ EXCEPTION_DB, // debug fault
ERROR: do not use C99 // comments
#2026: FILE: target/i386/hvf-utils/x86.h:32:
+ EXCEPTION_NMI, // non-maskable interrupt
ERROR: code indent should never use tabs
#2027: FILE: target/i386/hvf-utils/x86.h:33:
+ EXCEPTION_BP, // breakpoint^Itrap$
ERROR: do not use C99 // comments
#2027: FILE: target/i386/hvf-utils/x86.h:33:
+ EXCEPTION_BP, // breakpoint trap
ERROR: code indent should never use tabs
#2028: FILE: target/i386/hvf-utils/x86.h:34:
+ EXCEPTION_OF, // overflow^Itrap$
ERROR: do not use C99 // comments
#2028: FILE: target/i386/hvf-utils/x86.h:34:
+ EXCEPTION_OF, // overflow trap
ERROR: code indent should never use tabs
#2029: FILE: target/i386/hvf-utils/x86.h:35:
+ EXCEPTION_BR, // boundary range exceeded^Ifault$
ERROR: do not use C99 // comments
#2029: FILE: target/i386/hvf-utils/x86.h:35:
+ EXCEPTION_BR, // boundary range exceeded fault
ERROR: do not use C99 // comments
#2030: FILE: target/i386/hvf-utils/x86.h:36:
+ EXCEPTION_UD, // undefined opcode
ERROR: do not use C99 // comments
#2031: FILE: target/i386/hvf-utils/x86.h:37:
+ EXCEPTION_NM, // device not available
ERROR: do not use C99 // comments
#2032: FILE: target/i386/hvf-utils/x86.h:38:
+ EXCEPTION_DF, // double fault
ERROR: do not use C99 // comments
#2033: FILE: target/i386/hvf-utils/x86.h:39:
+ EXCEPTION_RSVD, // not defined
ERROR: code indent should never use tabs
#2034: FILE: target/i386/hvf-utils/x86.h:40:
+ EXCEPTION_TS, // invalid TSS^Ifault$
ERROR: do not use C99 // comments
#2034: FILE: target/i386/hvf-utils/x86.h:40:
+ EXCEPTION_TS, // invalid TSS fault
ERROR: code indent should never use tabs
#2035: FILE: target/i386/hvf-utils/x86.h:41:
+ EXCEPTION_NP, // not present^Ifault$
ERROR: do not use C99 // comments
#2035: FILE: target/i386/hvf-utils/x86.h:41:
+ EXCEPTION_NP, // not present fault
ERROR: code indent should never use tabs
#2036: FILE: target/i386/hvf-utils/x86.h:42:
+ EXCEPTION_GP, // general protection^Ifault$
ERROR: do not use C99 // comments
#2036: FILE: target/i386/hvf-utils/x86.h:42:
+ EXCEPTION_GP, // general protection fault
ERROR: do not use C99 // comments
#2037: FILE: target/i386/hvf-utils/x86.h:43:
+ EXCEPTION_PF, // page fault
ERROR: do not use C99 // comments
#2038: FILE: target/i386/hvf-utils/x86.h:44:
+ EXCEPTION_RSVD2, // not defined
ERROR: do not use C99 // comments
#2041: FILE: target/i386/hvf-utils/x86.h:47:
+// general purpose regs
ERROR: do not use C99 // comments
#2061: FILE: target/i386/hvf-utils/x86.h:67:
+// segment regs
ERROR: open brace '{' following struct go on the same line
#2074: FILE: target/i386/hvf-utils/x86.h:80:
+typedef struct x86_register
+{
ERROR: do not use C99 // comments
#2077: FILE: target/i386/hvf-utils/x86.h:83:
+ uint64_t rrx; // full 64 bit
ERROR: do not use C99 // comments
#2080: FILE: target/i386/hvf-utils/x86.h:86:
+ uint32_t erx; // low 32 bit part
ERROR: do not use C99 // comments
#2084: FILE: target/i386/hvf-utils/x86.h:90:
+ uint16_t rx; // low 16 bit part
ERROR: do not use C99 // comments
#2089: FILE: target/i386/hvf-utils/x86.h:95:
+ uint8_t lx; // low 8 bit part
ERROR: do not use C99 // comments
#2090: FILE: target/i386/hvf-utils/x86.h:96:
+ uint8_t hx; // high 8 bit
ERROR: do not use C99 // comments
#2117: FILE: target/i386/hvf-utils/x86.h:123:
+// rflags register
ERROR: do not use C99 // comments
#2202: FILE: target/i386/hvf-utils/x86.h:208:
+// 16 bit Task State Segment
ERROR: do not use C99 // comments
#2228: FILE: target/i386/hvf-utils/x86.h:234:
+// 32 bit Task State Segment
ERROR: open brace '{' following struct go on the same line
#2230: FILE: target/i386/hvf-utils/x86.h:236:
+typedef struct x86_tss_segment32
+{
ERROR: do not use C99 // comments
#2260: FILE: target/i386/hvf-utils/x86.h:266:
+// 64 bit Task State Segment
ERROR: open brace '{' following struct go on the same line
#2262: FILE: target/i386/hvf-utils/x86.h:268:
+typedef struct x86_tss_segment64
+{
ERROR: do not use C99 // comments
#2280: FILE: target/i386/hvf-utils/x86.h:286:
+// segment descriptors
WARNING: line over 80 characters
#2302: FILE: target/i386/hvf-utils/x86.h:308:
+static inline void x86_set_segment_base(x86_segment_descriptor *desc, uint32_t base)
ERROR: braces {} are necessary for all arms of this statement
#2312: FILE: target/i386/hvf-utils/x86.h:318:
+ if (desc->g)
[...]
WARNING: line over 80 characters
#2317: FILE: target/i386/hvf-utils/x86.h:323:
+static inline void x86_set_segment_limit(x86_segment_descriptor *desc, uint32_t limit)
ERROR: do not use C99 // comments
#2353: FILE: target/i386/hvf-utils/x86.h:359:
+// Definition of hvf_x86_state is here
ERROR: trailing whitespace
#2357: FILE: target/i386/hvf-utils/x86.h:363:
+ $
ERROR: "foo* bar" should be "foo *bar"
#2367: FILE: target/i386/hvf-utils/x86.h:373:
+ uint8_t* apic_page;
ERROR: do not use C99 // comments
#2377: FILE: target/i386/hvf-utils/x86.h:383:
+// useful register access macros
ERROR: do not use C99 // comments
#2433: FILE: target/i386/hvf-utils/x86.h:439:
+// deal with GDT/LDT descriptors in memory
ERROR: line over 90 characters
#2434: FILE: target/i386/hvf-utils/x86.h:440:
+bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
ERROR: line over 90 characters
#2435: FILE: target/i386/hvf-utils/x86.h:441:
+bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
WARNING: line over 80 characters
#2437: FILE: target/i386/hvf-utils/x86.h:443:
+bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate);
ERROR: do not use C99 // comments
#2439: FILE: target/i386/hvf-utils/x86.h:445:
+// helpers
WARNING: line over 80 characters
#2449: FILE: target/i386/hvf-utils/x86.h:455:
+addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg);
ERROR: do not use C99 // comments
#2455: FILE: target/i386/hvf-utils/x86.h:461:
+ __asm__ __volatile__("rdtscp; " // serializing read of tsc
WARNING: line over 80 characters
#2456: FILE: target/i386/hvf-utils/x86.h:462:
+ "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up
ERROR: do not use C99 // comments
#2456: FILE: target/i386/hvf-utils/x86.h:462:
+ "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up
ERROR: do not use C99 // comments
#2457: FILE: target/i386/hvf-utils/x86.h:463:
+ "or %%rdx,%%rax" // and or onto rax
ERROR: do not use C99 // comments
#2458: FILE: target/i386/hvf-utils/x86.h:464:
+ : "=a"(tsc) // output to tsc variable
ERROR: do not use C99 // comments
#2460: FILE: target/i386/hvf-utils/x86.h:466:
+ : "%rcx", "%rdx"); // rcx and rdx are clobbered
ERROR: trailing whitespace
#2461: FILE: target/i386/hvf-utils/x86.h:467:
+ $
WARNING: line over 80 characters
#2514: FILE: target/i386/hvf-utils/x86_cpuid.c:44:
+ .ext_features = /*CPUID_EXT_SSE3 |*/ CPUID_EXT_POPCNT, CPUID_MTRR | CPUID_CLFLUSH,
ERROR: do not use C99 // comments
#2517: FILE: target/i386/hvf-utils/x86_cpuid.c:47:
+ .ext3_features = 0,//CPUID_EXT3_LAHF_LM,
ERROR: trailing whitespace
#2534: FILE: target/i386/hvf-utils/x86_cpuid.c:64:
+ .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_SSSE3 | $
ERROR: do not initialise statics to 0 or NULL
#2565: FILE: target/i386/hvf-utils/x86_cpuid.c:95:
+static struct x86_cpuid *_cpuid = NULL;
ERROR: "foo* bar" should be "foo *bar"
#2567: FILE: target/i386/hvf-utils/x86_cpuid.c:97:
+void init_cpuid(struct CPUState* cpu)
ERROR: do not use C99 // comments
#2569: FILE: target/i386/hvf-utils/x86_cpuid.c:99:
+ _cpuid = &builtin_cpus[2]; // core2duo
ERROR: line over 90 characters
#2572: FILE: target/i386/hvf-utils/x86_cpuid.c:102:
+void get_cpuid_func(struct CPUState* cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
ERROR: "foo* bar" should be "foo *bar"
#2572: FILE: target/i386/hvf-utils/x86_cpuid.c:102:
+void get_cpuid_func(struct CPUState* cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
ERROR: switch and case should be at the same indent
#2580: FILE: target/i386/hvf-utils/x86_cpuid.c:110:
+ switch(func) {
+ case 0:
[...]
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 5:
[...]
+ case 6:
[...]
+ case 7:
[...]
+ case 9:
[...]
+ case 0xA:
[...]
+ case 0xB:
[...]
+ case 0xD:
[...]
+ case 0x80000000:
[...]
+ case 0x80000001:
[...]
+ case 0x80000002:
+ case 0x80000003:
+ case 0x80000004:
[...]
+ case 0x80000005:
[...]
+ case 0x80000006:
[...]
+ case 0x80000007:
[...]
+ case 0x80000008:
[...]
+ case 0x8000000A:
[...]
+ case 0x80000019:
[...]
+ case 0xC0000000:
[...]
+ default:
ERROR: space required before the open parenthesis '('
#2580: FILE: target/i386/hvf-utils/x86_cpuid.c:110:
+ switch(func) {
ERROR: line over 90 characters
#2588: FILE: target/i386/hvf-utils/x86_cpuid.c:118:
+ *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
ERROR: do not use C99 // comments
#2588: FILE: target/i386/hvf-utils/x86_cpuid.c:118:
+ *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
WARNING: line over 80 characters
#2598: FILE: target/i386/hvf-utils/x86_cpuid.c:128:
+ *ecx = *ecx & ~(CPUID_EXT_OSXSAVE | CPUID_EXT_MONITOR | CPUID_EXT_X2APIC |
ERROR: line over 90 characters
#2599: FILE: target/i386/hvf-utils/x86_cpuid.c:129:
+ CPUID_EXT_VMX | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_TM2 | CPUID_EXT_PCID |
ERROR: line over 90 characters
#2633: FILE: target/i386/hvf-utils/x86_cpuid.c:163:
+ *ebx = h_rbx & ~(CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF | CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
ERROR: line over 90 characters
#2634: FILE: target/i386/hvf-utils/x86_cpuid.c:164:
+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INVPCID);
ERROR: braces {} are necessary for all arms of this statement
#2661: FILE: target/i386/hvf-utils/x86_cpuid.c:191:
+ if (!cnt)
[...]
ERROR: braces {} are necessary for all arms of this statement
#2663: FILE: target/i386/hvf-utils/x86_cpuid.c:193:
+ if (1 == cnt)
[...]
ERROR: line over 90 characters
#2676: FILE: target/i386/hvf-utils/x86_cpuid.c:206:
+ *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
ERROR: do not use C99 // comments
#2676: FILE: target/i386/hvf-utils/x86_cpuid.c:206:
+ *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
WARNING: architecture specific defines should be avoided
#2763: FILE: target/i386/hvf-utils/x86_cpuid.h:17:
+#ifndef __CPUID_H__
ERROR: "foo* bar" should be "foo *bar"
#2793: FILE: target/i386/hvf-utils/x86_cpuid.h:47:
+void init_cpuid(struct CPUState* cpu);
ERROR: line over 90 characters
#2794: FILE: target/i386/hvf-utils/x86_cpuid.h:48:
+void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
WARNING: line over 80 characters
#2835: FILE: target/i386/hvf-utils/x86_decode.c:32:
+ printf("%llx: failed to decode instruction ", cpu->hvf_x86->fetch_rip - decode->len);
ERROR: braces {} are necessary even for single statement blocks
#2836: FILE: target/i386/hvf-utils/x86_decode.c:33:
+ for (int i = 0; i < decode->opcode_len; i++)
+ printf("%x ", decode->opcode[i]);
ERROR: switch and case should be at the same indent
#2844: FILE: target/i386/hvf-utils/x86_decode.c:41:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: __func__ should be used instead of gcc specific __FUNCTION__
#2858: FILE: target/i386/hvf-utils/x86_decode.c:55:
+ VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
WARNING: line over 80 characters
#2864: FILE: target/i386/hvf-utils/x86_decode.c:61:
+static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode, int size)
ERROR: trailing whitespace
#2867: FILE: target/i386/hvf-utils/x86_decode.c:64:
+ $
ERROR: switch and case should be at the same indent
#2868: FILE: target/i386/hvf-utils/x86_decode.c:65:
+ switch (size) {
+ case 1:
+ case 2:
+ case 4:
+ case 8:
[...]
+ default:
ERROR: __func__ should be used instead of gcc specific __FUNCTION__
#2875: FILE: target/i386/hvf-utils/x86_decode.c:72:
+ VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
ERROR: trailing whitespace
#2881: FILE: target/i386/hvf-utils/x86_decode.c:78:
+ $
ERROR: line over 90 characters
#2905: FILE: target/i386/hvf-utils/x86_decode.c:102:
+static void decode_modrm_rm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2910: FILE: target/i386/hvf-utils/x86_decode.c:107:
+static void decode_modrm_reg(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
WARNING: line over 80 characters
#2917: FILE: target/i386/hvf-utils/x86_decode.c:114:
+static void decode_rax(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2924: FILE: target/i386/hvf-utils/x86_decode.c:121:
+static inline void decode_immediate(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *var, int size)
ERROR: switch and case should be at the same indent
#2928: FILE: target/i386/hvf-utils/x86_decode.c:125:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: line over 90 characters
#2946: FILE: target/i386/hvf-utils/x86_decode.c:143:
+static void decode_imm8(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2952: FILE: target/i386/hvf-utils/x86_decode.c:149:
+static void decode_imm8_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2959: FILE: target/i386/hvf-utils/x86_decode.c:156:
+static void decode_imm16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
WARNING: line over 80 characters
#2966: FILE: target/i386/hvf-utils/x86_decode.c:163:
+static void decode_imm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2977: FILE: target/i386/hvf-utils/x86_decode.c:174:
+static void decode_imm_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2984: FILE: target/i386/hvf-utils/x86_decode.c:181:
+static void decode_imm_1(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#2990: FILE: target/i386/hvf-utils/x86_decode.c:187:
+static void decode_imm_0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
WARNING: line over 80 characters
#2999: FILE: target/i386/hvf-utils/x86_decode.c:196:
+ uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
ERROR: trailing whitespace
#3000: FILE: target/i386/hvf-utils/x86_decode.c:197:
+ $
ERROR: switch and case should be at the same indent
#3002: FILE: target/i386/hvf-utils/x86_decode.c:199:
+ switch (op) {
+ case 0xe:
[...]
+ case 0x16:
[...]
+ case 0x1e:
[...]
+ case 0x06:
[...]
+ case 0xa0:
[...]
+ case 0xa8:
WARNING: line over 80 characters
#3026: FILE: target/i386/hvf-utils/x86_decode.c:223:
+ uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
ERROR: trailing whitespace
#3027: FILE: target/i386/hvf-utils/x86_decode.c:224:
+ $
ERROR: switch and case should be at the same indent
#3029: FILE: target/i386/hvf-utils/x86_decode.c:226:
+ switch (op) {
+ case 0xf:
[...]
+ case 0x17:
[...]
+ case 0x1f:
[...]
+ case 0x07:
[...]
+ case 0xa1:
[...]
+ case 0xa9:
ERROR: line over 90 characters
#3055: FILE: target/i386/hvf-utils/x86_decode.c:252:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: line over 90 characters
#3062: FILE: target/i386/hvf-utils/x86_decode.c:259:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: braces {} are necessary for all arms of this statement
#3067: FILE: target/i386/hvf-utils/x86_decode.c:264:
+ if (!decode->modrm.reg)
[...]
+ else if (1 == decode->modrm.reg)
[...]
ERROR: braces {} are necessary for all arms of this statement
#3069: FILE: target/i386/hvf-utils/x86_decode.c:266:
+ else if (1 == decode->modrm.reg)
[...]
ERROR: line over 90 characters
#3077: FILE: target/i386/hvf-utils/x86_decode.c:274:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: line over 90 characters
#3084: FILE: target/i386/hvf-utils/x86_decode.c:281:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: switch and case should be at the same indent
#3145: FILE: target/i386/hvf-utils/x86_decode.c:342:
+ switch (decode->modrm.reg) {
+ case 0:
+ case 1:
[...]
+ case 2:
[...]
+ case 3:
[...]
+ default:
ERROR: line over 90 characters
#3165: FILE: target/i386/hvf-utils/x86_decode.c:362:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: line over 90 characters
#3172: FILE: target/i386/hvf-utils/x86_decode.c:369:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: line over 90 characters
#3176: FILE: target/i386/hvf-utils/x86_decode.c:373:
+static void fetch_moffs(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#3186: FILE: target/i386/hvf-utils/x86_decode.c:383:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
WARNING: line over 80 characters
#3190: FILE: target/i386/hvf-utils/x86_decode.c:387:
+static void decode_rcx(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#3202: FILE: target/i386/hvf-utils/x86_decode.c:399:
+ void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
ERROR: line over 90 characters
#3203: FILE: target/i386/hvf-utils/x86_decode.c:400:
+ void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
ERROR: line over 90 characters
#3204: FILE: target/i386/hvf-utils/x86_decode.c:401:
+ void (*decode_op3)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op3);
ERROR: line over 90 characters
#3205: FILE: target/i386/hvf-utils/x86_decode.c:402:
+ void (*decode_op4)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op4);
ERROR: line over 90 characters
#3218: FILE: target/i386/hvf-utils/x86_decode.c:415:
+ void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
ERROR: line over 90 characters
#3219: FILE: target/i386/hvf-utils/x86_decode.c:416:
+ void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
WARNING: line over 80 characters
#3224: FILE: target/i386/hvf-utils/x86_decode.c:421:
+struct decode_tbl invl_inst = {0x0, 0, 0, false, NULL, NULL, NULL, NULL, decode_invalid};
ERROR: trailing whitespace
#3233: FILE: target/i386/hvf-utils/x86_decode.c:430:
+ $
WARNING: line over 80 characters
#3236: FILE: target/i386/hvf-utils/x86_decode.c:433:
+ int index = ((decode->opcode[0] & 0xf) << 4) | (mode << 3) | decode->modrm.reg;
ERROR: trailing whitespace
#3237: FILE: target/i386/hvf-utils/x86_decode.c:434:
+ $
ERROR: trailing whitespace
#3239: FILE: target/i386/hvf-utils/x86_decode.c:436:
+ $
ERROR: braces {} are necessary for all arms of this statement
#3241: FILE: target/i386/hvf-utils/x86_decode.c:438:
+ if (decoder->operand_size)
[...]
ERROR: trailing whitespace
#3246: FILE: target/i386/hvf-utils/x86_decode.c:443:
+ $
ERROR: braces {} are necessary for all arms of this statement
#3247: FILE: target/i386/hvf-utils/x86_decode.c:444:
+ if (decoder->decode_op1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#3249: FILE: target/i386/hvf-utils/x86_decode.c:446:
+ if (decoder->decode_op2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#3251: FILE: target/i386/hvf-utils/x86_decode.c:448:
+ if (decoder->decode_postfix)
[...]
ERROR: trailing whitespace
#3253: FILE: target/i386/hvf-utils/x86_decode.c:450:
+ $
ERROR: line over 90 characters
#3254: FILE: target/i386/hvf-utils/x86_decode.c:451:
+ VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n", decode->opcode[0], decode->modrm.modrm, decoder->modrm_reg, decoder->modrm_mod);
ERROR: braces {} are necessary for all arms of this statement
#3271: FILE: target/i386/hvf-utils/x86_decode.c:468:
+ if (decode->modrm.reg > 2)
[...]
WARNING: line over 80 characters
#3288: FILE: target/i386/hvf-utils/x86_decode.c:485:
+ printf("%llx: decode_sldtgroup: %d\n", cpu->hvf_x86->fetch_rip, decode->modrm.reg);
ERROR: line over 90 characters
#3330: FILE: target/i386/hvf-utils/x86_decode.c:527:
+static void decode_x87_modrm_floatp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#3335: FILE: target/i386/hvf-utils/x86_decode.c:532:
+static void decode_x87_modrm_intp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#3340: FILE: target/i386/hvf-utils/x86_decode.c:537:
+static void decode_x87_modrm_bytep(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#3345: FILE: target/i386/hvf-utils/x86_decode.c:542:
+static void decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: line over 90 characters
#3351: FILE: target/i386/hvf-utils/x86_decode.c:548:
+static void decode_decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: switch and case should be at the same indent
#3361: FILE: target/i386/hvf-utils/x86_decode.c:558:
+ switch (decode->modrm.reg) {
+ case 0:
[...]
+ case 1:
[...]
+ case 5:
[...]
+ case 6:
[...]
+ case 7:
[...]
+ default:
ERROR: line over 90 characters
#3398: FILE: target/i386/hvf-utils/x86_decode.c:595:
+ decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
ERROR: switch and case should be at the same indent
#3403: FILE: target/i386/hvf-utils/x86_decode.c:600:
+ switch(decode->modrm.modrm) {
+ case 0xe0:
[...]
+ case 0xe1:
[...]
+ case 0xe4:
[...]
+ case 0xe5:
[...]
+ default:
ERROR: space required before the open parenthesis '('
#3403: FILE: target/i386/hvf-utils/x86_decode.c:600:
+ switch(decode->modrm.modrm) {
ERROR: do not use C99 // comments
#3405: FILE: target/i386/hvf-utils/x86_decode.c:602:
+ // FCHS
ERROR: do not use C99 // comments
#3415: FILE: target/i386/hvf-utils/x86_decode.c:612:
+ // FXAM
ERROR: switch and case should be at the same indent
#3426: FILE: target/i386/hvf-utils/x86_decode.c:623:
+ switch (decode->modrm.modrm) {
+ case 0xe0:
[...]
+ case 0xe1:
[...]
+ case 0xe2:
[...]
+ case 0xe3:
[...]
+ case 0xe4:
[...]
+ default:
ERROR: line over 90 characters
#3428: FILE: target/i386/hvf-utils/x86_decode.c:625:
+ VM_PANIC_ON_EX(1, "unhandled FNENI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
ERROR: line over 90 characters
#3431: FILE: target/i386/hvf-utils/x86_decode.c:628:
+ VM_PANIC_ON_EX(1, "unhandled FNDISI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
ERROR: line over 90 characters
#3434: FILE: target/i386/hvf-utils/x86_decode.c:631:
+ VM_PANIC_ON_EX(1, "unhandled FCLEX: %x %x\n", decode->opcode[0], decode->modrm.modrm);
ERROR: line over 90 characters
#3443: FILE: target/i386/hvf-utils/x86_decode.c:640:
+ VM_PANIC_ON_EX(1, "unhandled fpu opcode: %x %x\n", decode->opcode[0], decode->modrm.modrm);
ERROR: line over 90 characters
#3450: FILE: target/i386/hvf-utils/x86_decode.c:647:
+#define RFLAGS_MASK_OSZAPC (RFLAGS_OF | RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
WARNING: line over 80 characters
#3451: FILE: target/i386/hvf-utils/x86_decode.c:648:
+#define RFLAGS_MASK_LAHF (RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
ERROR: that open brace { should be on the previous line
#3459: FILE: target/i386/hvf-utils/x86_decode.c:656:
+struct decode_tbl _1op_inst[] =
+{
ERROR: line over 90 characters
#3460: FILE: target/i386/hvf-utils/x86_decode.c:657:
+ {0x0, X86_DECODE_CMD_ADD, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3461: FILE: target/i386/hvf-utils/x86_decode.c:658:
+ {0x1, X86_DECODE_CMD_ADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3462: FILE: target/i386/hvf-utils/x86_decode.c:659:
+ {0x2, X86_DECODE_CMD_ADD, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3463: FILE: target/i386/hvf-utils/x86_decode.c:660:
+ {0x3, X86_DECODE_CMD_ADD, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3464: FILE: target/i386/hvf-utils/x86_decode.c:661:
+ {0x4, X86_DECODE_CMD_ADD, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3465: FILE: target/i386/hvf-utils/x86_decode.c:662:
+ {0x5, X86_DECODE_CMD_ADD, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3466: FILE: target/i386/hvf-utils/x86_decode.c:663:
+ {0x6, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3467: FILE: target/i386/hvf-utils/x86_decode.c:664:
+ {0x7, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3468: FILE: target/i386/hvf-utils/x86_decode.c:665:
+ {0x8, X86_DECODE_CMD_OR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3469: FILE: target/i386/hvf-utils/x86_decode.c:666:
+ {0x9, X86_DECODE_CMD_OR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3470: FILE: target/i386/hvf-utils/x86_decode.c:667:
+ {0xa, X86_DECODE_CMD_OR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3471: FILE: target/i386/hvf-utils/x86_decode.c:668:
+ {0xb, X86_DECODE_CMD_OR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3472: FILE: target/i386/hvf-utils/x86_decode.c:669:
+ {0xc, X86_DECODE_CMD_OR, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3473: FILE: target/i386/hvf-utils/x86_decode.c:670:
+ {0xd, X86_DECODE_CMD_OR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3474: FILE: target/i386/hvf-utils/x86_decode.c:671:
+ $
ERROR: line over 90 characters
#3475: FILE: target/i386/hvf-utils/x86_decode.c:672:
+ {0xe, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3476: FILE: target/i386/hvf-utils/x86_decode.c:673:
+ {0xf, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3477: FILE: target/i386/hvf-utils/x86_decode.c:674:
+ $
ERROR: line over 90 characters
#3478: FILE: target/i386/hvf-utils/x86_decode.c:675:
+ {0x10, X86_DECODE_CMD_ADC, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3479: FILE: target/i386/hvf-utils/x86_decode.c:676:
+ {0x11, X86_DECODE_CMD_ADC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3480: FILE: target/i386/hvf-utils/x86_decode.c:677:
+ {0x12, X86_DECODE_CMD_ADC, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3481: FILE: target/i386/hvf-utils/x86_decode.c:678:
+ {0x13, X86_DECODE_CMD_ADC, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3482: FILE: target/i386/hvf-utils/x86_decode.c:679:
+ {0x14, X86_DECODE_CMD_ADC, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3483: FILE: target/i386/hvf-utils/x86_decode.c:680:
+ {0x15, X86_DECODE_CMD_ADC, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3484: FILE: target/i386/hvf-utils/x86_decode.c:681:
+ $
ERROR: line over 90 characters
#3485: FILE: target/i386/hvf-utils/x86_decode.c:682:
+ {0x16, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3486: FILE: target/i386/hvf-utils/x86_decode.c:683:
+ {0x17, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3487: FILE: target/i386/hvf-utils/x86_decode.c:684:
+ $
ERROR: line over 90 characters
#3488: FILE: target/i386/hvf-utils/x86_decode.c:685:
+ {0x18, X86_DECODE_CMD_SBB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3489: FILE: target/i386/hvf-utils/x86_decode.c:686:
+ {0x19, X86_DECODE_CMD_SBB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3490: FILE: target/i386/hvf-utils/x86_decode.c:687:
+ {0x1a, X86_DECODE_CMD_SBB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3491: FILE: target/i386/hvf-utils/x86_decode.c:688:
+ {0x1b, X86_DECODE_CMD_SBB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3492: FILE: target/i386/hvf-utils/x86_decode.c:689:
+ {0x1c, X86_DECODE_CMD_SBB, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3493: FILE: target/i386/hvf-utils/x86_decode.c:690:
+ {0x1d, X86_DECODE_CMD_SBB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3494: FILE: target/i386/hvf-utils/x86_decode.c:691:
+ $
ERROR: line over 90 characters
#3495: FILE: target/i386/hvf-utils/x86_decode.c:692:
+ {0x1e, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3496: FILE: target/i386/hvf-utils/x86_decode.c:693:
+ {0x1f, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3497: FILE: target/i386/hvf-utils/x86_decode.c:694:
+ $
ERROR: line over 90 characters
#3498: FILE: target/i386/hvf-utils/x86_decode.c:695:
+ {0x20, X86_DECODE_CMD_AND, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3499: FILE: target/i386/hvf-utils/x86_decode.c:696:
+ {0x21, X86_DECODE_CMD_AND, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3500: FILE: target/i386/hvf-utils/x86_decode.c:697:
+ {0x22, X86_DECODE_CMD_AND, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3501: FILE: target/i386/hvf-utils/x86_decode.c:698:
+ {0x23, X86_DECODE_CMD_AND, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3502: FILE: target/i386/hvf-utils/x86_decode.c:699:
+ {0x24, X86_DECODE_CMD_AND, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3503: FILE: target/i386/hvf-utils/x86_decode.c:700:
+ {0x25, X86_DECODE_CMD_AND, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3504: FILE: target/i386/hvf-utils/x86_decode.c:701:
+ {0x28, X86_DECODE_CMD_SUB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3505: FILE: target/i386/hvf-utils/x86_decode.c:702:
+ {0x29, X86_DECODE_CMD_SUB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3506: FILE: target/i386/hvf-utils/x86_decode.c:703:
+ {0x2a, X86_DECODE_CMD_SUB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3507: FILE: target/i386/hvf-utils/x86_decode.c:704:
+ {0x2b, X86_DECODE_CMD_SUB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3508: FILE: target/i386/hvf-utils/x86_decode.c:705:
+ {0x2c, X86_DECODE_CMD_SUB, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3509: FILE: target/i386/hvf-utils/x86_decode.c:706:
+ {0x2d, X86_DECODE_CMD_SUB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3510: FILE: target/i386/hvf-utils/x86_decode.c:707:
+ {0x2f, X86_DECODE_CMD_DAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3511: FILE: target/i386/hvf-utils/x86_decode.c:708:
+ {0x30, X86_DECODE_CMD_XOR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3512: FILE: target/i386/hvf-utils/x86_decode.c:709:
+ {0x31, X86_DECODE_CMD_XOR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3513: FILE: target/i386/hvf-utils/x86_decode.c:710:
+ {0x32, X86_DECODE_CMD_XOR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3514: FILE: target/i386/hvf-utils/x86_decode.c:711:
+ {0x33, X86_DECODE_CMD_XOR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3515: FILE: target/i386/hvf-utils/x86_decode.c:712:
+ {0x34, X86_DECODE_CMD_XOR, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3516: FILE: target/i386/hvf-utils/x86_decode.c:713:
+ {0x35, X86_DECODE_CMD_XOR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3517: FILE: target/i386/hvf-utils/x86_decode.c:714:
+ $
ERROR: line over 90 characters
#3518: FILE: target/i386/hvf-utils/x86_decode.c:715:
+ {0x38, X86_DECODE_CMD_CMP, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3519: FILE: target/i386/hvf-utils/x86_decode.c:716:
+ {0x39, X86_DECODE_CMD_CMP, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3520: FILE: target/i386/hvf-utils/x86_decode.c:717:
+ {0x3a, X86_DECODE_CMD_CMP, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3521: FILE: target/i386/hvf-utils/x86_decode.c:718:
+ {0x3b, X86_DECODE_CMD_CMP, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3522: FILE: target/i386/hvf-utils/x86_decode.c:719:
+ {0x3c, X86_DECODE_CMD_CMP, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3523: FILE: target/i386/hvf-utils/x86_decode.c:720:
+ {0x3d, X86_DECODE_CMD_CMP, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3524: FILE: target/i386/hvf-utils/x86_decode.c:721:
+ $
ERROR: line over 90 characters
#3525: FILE: target/i386/hvf-utils/x86_decode.c:722:
+ {0x3f, X86_DECODE_CMD_AAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3526: FILE: target/i386/hvf-utils/x86_decode.c:723:
+ $
ERROR: line over 90 characters
#3527: FILE: target/i386/hvf-utils/x86_decode.c:724:
+ {0x40, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3528: FILE: target/i386/hvf-utils/x86_decode.c:725:
+ {0x41, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3529: FILE: target/i386/hvf-utils/x86_decode.c:726:
+ {0x42, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3530: FILE: target/i386/hvf-utils/x86_decode.c:727:
+ {0x43, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3531: FILE: target/i386/hvf-utils/x86_decode.c:728:
+ {0x44, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3532: FILE: target/i386/hvf-utils/x86_decode.c:729:
+ {0x45, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3533: FILE: target/i386/hvf-utils/x86_decode.c:730:
+ {0x46, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3534: FILE: target/i386/hvf-utils/x86_decode.c:731:
+ {0x47, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3535: FILE: target/i386/hvf-utils/x86_decode.c:732:
+ $
ERROR: line over 90 characters
#3536: FILE: target/i386/hvf-utils/x86_decode.c:733:
+ {0x48, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3537: FILE: target/i386/hvf-utils/x86_decode.c:734:
+ {0x49, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3538: FILE: target/i386/hvf-utils/x86_decode.c:735:
+ {0x4a, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3539: FILE: target/i386/hvf-utils/x86_decode.c:736:
+ {0x4b, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3540: FILE: target/i386/hvf-utils/x86_decode.c:737:
+ {0x4c, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3541: FILE: target/i386/hvf-utils/x86_decode.c:738:
+ {0x4d, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3542: FILE: target/i386/hvf-utils/x86_decode.c:739:
+ {0x4e, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3543: FILE: target/i386/hvf-utils/x86_decode.c:740:
+ {0x4f, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3544: FILE: target/i386/hvf-utils/x86_decode.c:741:
+ $
ERROR: line over 90 characters
#3545: FILE: target/i386/hvf-utils/x86_decode.c:742:
+ {0x50, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3546: FILE: target/i386/hvf-utils/x86_decode.c:743:
+ {0x51, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3547: FILE: target/i386/hvf-utils/x86_decode.c:744:
+ {0x52, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3548: FILE: target/i386/hvf-utils/x86_decode.c:745:
+ {0x53, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3549: FILE: target/i386/hvf-utils/x86_decode.c:746:
+ {0x54, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3550: FILE: target/i386/hvf-utils/x86_decode.c:747:
+ {0x55, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3551: FILE: target/i386/hvf-utils/x86_decode.c:748:
+ {0x56, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3552: FILE: target/i386/hvf-utils/x86_decode.c:749:
+ {0x57, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3553: FILE: target/i386/hvf-utils/x86_decode.c:750:
+ $
ERROR: line over 90 characters
#3554: FILE: target/i386/hvf-utils/x86_decode.c:751:
+ {0x58, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3555: FILE: target/i386/hvf-utils/x86_decode.c:752:
+ {0x59, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3556: FILE: target/i386/hvf-utils/x86_decode.c:753:
+ {0x5a, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3557: FILE: target/i386/hvf-utils/x86_decode.c:754:
+ {0x5b, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3558: FILE: target/i386/hvf-utils/x86_decode.c:755:
+ {0x5c, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3559: FILE: target/i386/hvf-utils/x86_decode.c:756:
+ {0x5d, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3560: FILE: target/i386/hvf-utils/x86_decode.c:757:
+ {0x5e, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3561: FILE: target/i386/hvf-utils/x86_decode.c:758:
+ {0x5f, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3562: FILE: target/i386/hvf-utils/x86_decode.c:759:
+ $
ERROR: line over 90 characters
#3563: FILE: target/i386/hvf-utils/x86_decode.c:760:
+ {0x60, X86_DECODE_CMD_PUSHA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3564: FILE: target/i386/hvf-utils/x86_decode.c:761:
+ {0x61, X86_DECODE_CMD_POPA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3565: FILE: target/i386/hvf-utils/x86_decode.c:762:
+ $
ERROR: line over 90 characters
#3566: FILE: target/i386/hvf-utils/x86_decode.c:763:
+ {0x68, X86_DECODE_CMD_PUSH, 0, false, decode_imm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3567: FILE: target/i386/hvf-utils/x86_decode.c:764:
+ {0x6a, X86_DECODE_CMD_PUSH, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3568: FILE: target/i386/hvf-utils/x86_decode.c:765:
+ {0x69, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3569: FILE: target/i386/hvf-utils/x86_decode.c:766:
+ {0x6b, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm8_signed, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3570: FILE: target/i386/hvf-utils/x86_decode.c:767:
+ $
WARNING: line over 80 characters
#3571: FILE: target/i386/hvf-utils/x86_decode.c:768:
+ {0x6c, X86_DECODE_CMD_INS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3572: FILE: target/i386/hvf-utils/x86_decode.c:769:
+ {0x6d, X86_DECODE_CMD_INS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3573: FILE: target/i386/hvf-utils/x86_decode.c:770:
+ {0x6e, X86_DECODE_CMD_OUTS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3574: FILE: target/i386/hvf-utils/x86_decode.c:771:
+ {0x6f, X86_DECODE_CMD_OUTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3575: FILE: target/i386/hvf-utils/x86_decode.c:772:
+ $
ERROR: line over 90 characters
#3576: FILE: target/i386/hvf-utils/x86_decode.c:773:
+ {0x70, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3577: FILE: target/i386/hvf-utils/x86_decode.c:774:
+ {0x71, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3578: FILE: target/i386/hvf-utils/x86_decode.c:775:
+ {0x72, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3579: FILE: target/i386/hvf-utils/x86_decode.c:776:
+ {0x73, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3580: FILE: target/i386/hvf-utils/x86_decode.c:777:
+ {0x74, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3581: FILE: target/i386/hvf-utils/x86_decode.c:778:
+ {0x75, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3582: FILE: target/i386/hvf-utils/x86_decode.c:779:
+ {0x76, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3583: FILE: target/i386/hvf-utils/x86_decode.c:780:
+ {0x77, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3584: FILE: target/i386/hvf-utils/x86_decode.c:781:
+ {0x78, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3585: FILE: target/i386/hvf-utils/x86_decode.c:782:
+ {0x79, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3586: FILE: target/i386/hvf-utils/x86_decode.c:783:
+ {0x7a, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3587: FILE: target/i386/hvf-utils/x86_decode.c:784:
+ {0x7b, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3588: FILE: target/i386/hvf-utils/x86_decode.c:785:
+ {0x7c, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3589: FILE: target/i386/hvf-utils/x86_decode.c:786:
+ {0x7d, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3590: FILE: target/i386/hvf-utils/x86_decode.c:787:
+ {0x7e, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3591: FILE: target/i386/hvf-utils/x86_decode.c:788:
+ {0x7f, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3592: FILE: target/i386/hvf-utils/x86_decode.c:789:
+ $
ERROR: line over 90 characters
#3593: FILE: target/i386/hvf-utils/x86_decode.c:790:
+ {0x80, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3594: FILE: target/i386/hvf-utils/x86_decode.c:791:
+ {0x81, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3595: FILE: target/i386/hvf-utils/x86_decode.c:792:
+ {0x82, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3596: FILE: target/i386/hvf-utils/x86_decode.c:793:
+ {0x83, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8_signed, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3597: FILE: target/i386/hvf-utils/x86_decode.c:794:
+ {0x84, X86_DECODE_CMD_TST, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3598: FILE: target/i386/hvf-utils/x86_decode.c:795:
+ {0x85, X86_DECODE_CMD_TST, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3599: FILE: target/i386/hvf-utils/x86_decode.c:796:
+ {0x86, X86_DECODE_CMD_XCHG, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3600: FILE: target/i386/hvf-utils/x86_decode.c:797:
+ {0x87, X86_DECODE_CMD_XCHG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3601: FILE: target/i386/hvf-utils/x86_decode.c:798:
+ {0x88, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3602: FILE: target/i386/hvf-utils/x86_decode.c:799:
+ {0x89, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3603: FILE: target/i386/hvf-utils/x86_decode.c:800:
+ {0x8a, X86_DECODE_CMD_MOV, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3604: FILE: target/i386/hvf-utils/x86_decode.c:801:
+ {0x8b, X86_DECODE_CMD_MOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3605: FILE: target/i386/hvf-utils/x86_decode.c:802:
+ {0x8c, X86_DECODE_CMD_MOV_FROM_SEG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3606: FILE: target/i386/hvf-utils/x86_decode.c:803:
+ {0x8d, X86_DECODE_CMD_LEA, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3607: FILE: target/i386/hvf-utils/x86_decode.c:804:
+ {0x8e, X86_DECODE_CMD_MOV_TO_SEG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3608: FILE: target/i386/hvf-utils/x86_decode.c:805:
+ {0x8f, X86_DECODE_CMD_POP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3609: FILE: target/i386/hvf-utils/x86_decode.c:806:
+ $
WARNING: line over 80 characters
#3610: FILE: target/i386/hvf-utils/x86_decode.c:807:
+ {0x90, X86_DECODE_CMD_NOP, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3611: FILE: target/i386/hvf-utils/x86_decode.c:808:
+ {0x91, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3612: FILE: target/i386/hvf-utils/x86_decode.c:809:
+ {0x92, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3613: FILE: target/i386/hvf-utils/x86_decode.c:810:
+ {0x93, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3614: FILE: target/i386/hvf-utils/x86_decode.c:811:
+ {0x94, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3615: FILE: target/i386/hvf-utils/x86_decode.c:812:
+ {0x95, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3616: FILE: target/i386/hvf-utils/x86_decode.c:813:
+ {0x96, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3617: FILE: target/i386/hvf-utils/x86_decode.c:814:
+ {0x97, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3618: FILE: target/i386/hvf-utils/x86_decode.c:815:
+ $
WARNING: line over 80 characters
#3619: FILE: target/i386/hvf-utils/x86_decode.c:816:
+ {0x98, X86_DECODE_CMD_CBW, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3620: FILE: target/i386/hvf-utils/x86_decode.c:817:
+ {0x99, X86_DECODE_CMD_CWD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3621: FILE: target/i386/hvf-utils/x86_decode.c:818:
+ $
ERROR: line over 90 characters
#3622: FILE: target/i386/hvf-utils/x86_decode.c:819:
+ {0x9a, X86_DECODE_CMD_CALL_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3623: FILE: target/i386/hvf-utils/x86_decode.c:820:
+ $
ERROR: line over 90 characters
#3624: FILE: target/i386/hvf-utils/x86_decode.c:821:
+ {0x9c, X86_DECODE_CMD_PUSHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3625: FILE: target/i386/hvf-utils/x86_decode.c:822:
+ //{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_POPF},
ERROR: do not use C99 // comments
#3625: FILE: target/i386/hvf-utils/x86_decode.c:822:
+ //{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_POPF},
WARNING: line over 80 characters
#3626: FILE: target/i386/hvf-utils/x86_decode.c:823:
+ {0x9e, X86_DECODE_CMD_SAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3627: FILE: target/i386/hvf-utils/x86_decode.c:824:
+ {0x9f, X86_DECODE_CMD_LAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_LAHF},
ERROR: trailing whitespace
#3628: FILE: target/i386/hvf-utils/x86_decode.c:825:
+ $
ERROR: line over 90 characters
#3629: FILE: target/i386/hvf-utils/x86_decode.c:826:
+ {0xa0, X86_DECODE_CMD_MOV, 1, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3630: FILE: target/i386/hvf-utils/x86_decode.c:827:
+ {0xa1, X86_DECODE_CMD_MOV, 0, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3631: FILE: target/i386/hvf-utils/x86_decode.c:828:
+ {0xa2, X86_DECODE_CMD_MOV, 1, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3632: FILE: target/i386/hvf-utils/x86_decode.c:829:
+ {0xa3, X86_DECODE_CMD_MOV, 0, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3633: FILE: target/i386/hvf-utils/x86_decode.c:830:
+ $
WARNING: line over 80 characters
#3634: FILE: target/i386/hvf-utils/x86_decode.c:831:
+ {0xa4, X86_DECODE_CMD_MOVS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3635: FILE: target/i386/hvf-utils/x86_decode.c:832:
+ {0xa5, X86_DECODE_CMD_MOVS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3636: FILE: target/i386/hvf-utils/x86_decode.c:833:
+ {0xa6, X86_DECODE_CMD_CMPS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3637: FILE: target/i386/hvf-utils/x86_decode.c:834:
+ {0xa7, X86_DECODE_CMD_CMPS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
WARNING: line over 80 characters
#3638: FILE: target/i386/hvf-utils/x86_decode.c:835:
+ {0xaa, X86_DECODE_CMD_STOS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3639: FILE: target/i386/hvf-utils/x86_decode.c:836:
+ {0xab, X86_DECODE_CMD_STOS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3640: FILE: target/i386/hvf-utils/x86_decode.c:837:
+ {0xac, X86_DECODE_CMD_LODS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3641: FILE: target/i386/hvf-utils/x86_decode.c:838:
+ {0xad, X86_DECODE_CMD_LODS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3642: FILE: target/i386/hvf-utils/x86_decode.c:839:
+ {0xae, X86_DECODE_CMD_SCAS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3643: FILE: target/i386/hvf-utils/x86_decode.c:840:
+ {0xaf, X86_DECODE_CMD_SCAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3644: FILE: target/i386/hvf-utils/x86_decode.c:841:
+ $
ERROR: line over 90 characters
#3645: FILE: target/i386/hvf-utils/x86_decode.c:842:
+ {0xa8, X86_DECODE_CMD_TST, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3646: FILE: target/i386/hvf-utils/x86_decode.c:843:
+ {0xa9, X86_DECODE_CMD_TST, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3647: FILE: target/i386/hvf-utils/x86_decode.c:844:
+ $
ERROR: line over 90 characters
#3648: FILE: target/i386/hvf-utils/x86_decode.c:845:
+ {0xb0, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3649: FILE: target/i386/hvf-utils/x86_decode.c:846:
+ {0xb1, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3650: FILE: target/i386/hvf-utils/x86_decode.c:847:
+ {0xb2, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3651: FILE: target/i386/hvf-utils/x86_decode.c:848:
+ {0xb3, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3652: FILE: target/i386/hvf-utils/x86_decode.c:849:
+ {0xb4, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3653: FILE: target/i386/hvf-utils/x86_decode.c:850:
+ {0xb5, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3654: FILE: target/i386/hvf-utils/x86_decode.c:851:
+ {0xb6, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3655: FILE: target/i386/hvf-utils/x86_decode.c:852:
+ {0xb7, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3656: FILE: target/i386/hvf-utils/x86_decode.c:853:
+ $
ERROR: line over 90 characters
#3657: FILE: target/i386/hvf-utils/x86_decode.c:854:
+ {0xb8, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3658: FILE: target/i386/hvf-utils/x86_decode.c:855:
+ {0xb9, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3659: FILE: target/i386/hvf-utils/x86_decode.c:856:
+ {0xba, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3660: FILE: target/i386/hvf-utils/x86_decode.c:857:
+ {0xbb, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3661: FILE: target/i386/hvf-utils/x86_decode.c:858:
+ {0xbc, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3662: FILE: target/i386/hvf-utils/x86_decode.c:859:
+ {0xbd, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3663: FILE: target/i386/hvf-utils/x86_decode.c:860:
+ {0xbe, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3664: FILE: target/i386/hvf-utils/x86_decode.c:861:
+ {0xbf, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3665: FILE: target/i386/hvf-utils/x86_decode.c:862:
+ $
ERROR: line over 90 characters
#3666: FILE: target/i386/hvf-utils/x86_decode.c:863:
+ {0xc0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3667: FILE: target/i386/hvf-utils/x86_decode.c:864:
+ {0xc1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3668: FILE: target/i386/hvf-utils/x86_decode.c:865:
+ $
ERROR: line over 90 characters
#3669: FILE: target/i386/hvf-utils/x86_decode.c:866:
+ {0xc2, X86_DECODE_RET_NEAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3670: FILE: target/i386/hvf-utils/x86_decode.c:867:
+ {0xc3, X86_DECODE_RET_NEAR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3671: FILE: target/i386/hvf-utils/x86_decode.c:868:
+ $
ERROR: line over 90 characters
#3672: FILE: target/i386/hvf-utils/x86_decode.c:869:
+ {0xc4, X86_DECODE_CMD_LES, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3673: FILE: target/i386/hvf-utils/x86_decode.c:870:
+ {0xc5, X86_DECODE_CMD_LDS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3674: FILE: target/i386/hvf-utils/x86_decode.c:871:
+ $
ERROR: line over 90 characters
#3675: FILE: target/i386/hvf-utils/x86_decode.c:872:
+ {0xc6, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3676: FILE: target/i386/hvf-utils/x86_decode.c:873:
+ {0xc7, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3677: FILE: target/i386/hvf-utils/x86_decode.c:874:
+ $
ERROR: line over 90 characters
#3678: FILE: target/i386/hvf-utils/x86_decode.c:875:
+ {0xc8, X86_DECODE_CMD_ENTER, 0, false, decode_imm16, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3679: FILE: target/i386/hvf-utils/x86_decode.c:876:
+ {0xc9, X86_DECODE_CMD_LEAVE, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3680: FILE: target/i386/hvf-utils/x86_decode.c:877:
+ {0xca, X86_DECODE_RET_FAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3681: FILE: target/i386/hvf-utils/x86_decode.c:878:
+ {0xcb, X86_DECODE_RET_FAR, 0, false, decode_imm_0, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3682: FILE: target/i386/hvf-utils/x86_decode.c:879:
+ {0xcd, X86_DECODE_CMD_INT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3683: FILE: target/i386/hvf-utils/x86_decode.c:880:
+ //{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IRET},
ERROR: do not use C99 // comments
#3683: FILE: target/i386/hvf-utils/x86_decode.c:880:
+ //{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IRET},
ERROR: trailing whitespace
#3684: FILE: target/i386/hvf-utils/x86_decode.c:881:
+ $
ERROR: line over 90 characters
#3685: FILE: target/i386/hvf-utils/x86_decode.c:882:
+ {0xd0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3686: FILE: target/i386/hvf-utils/x86_decode.c:883:
+ {0xd1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3687: FILE: target/i386/hvf-utils/x86_decode.c:884:
+ {0xd2, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3688: FILE: target/i386/hvf-utils/x86_decode.c:885:
+ {0xd3, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3689: FILE: target/i386/hvf-utils/x86_decode.c:886:
+ $
ERROR: line over 90 characters
#3690: FILE: target/i386/hvf-utils/x86_decode.c:887:
+ {0xd4, X86_DECODE_CMD_AAM, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3691: FILE: target/i386/hvf-utils/x86_decode.c:888:
+ {0xd5, X86_DECODE_CMD_AAD, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3692: FILE: target/i386/hvf-utils/x86_decode.c:889:
+ $
WARNING: line over 80 characters
#3693: FILE: target/i386/hvf-utils/x86_decode.c:890:
+ {0xd7, X86_DECODE_CMD_XLAT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3694: FILE: target/i386/hvf-utils/x86_decode.c:891:
+ $
ERROR: line over 90 characters
#3695: FILE: target/i386/hvf-utils/x86_decode.c:892:
+ {0xd8, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3696: FILE: target/i386/hvf-utils/x86_decode.c:893:
+ {0xd9, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3697: FILE: target/i386/hvf-utils/x86_decode.c:894:
+ {0xda, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3698: FILE: target/i386/hvf-utils/x86_decode.c:895:
+ {0xdb, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3699: FILE: target/i386/hvf-utils/x86_decode.c:896:
+ {0xdc, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3700: FILE: target/i386/hvf-utils/x86_decode.c:897:
+ {0xdd, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3701: FILE: target/i386/hvf-utils/x86_decode.c:898:
+ {0xde, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3702: FILE: target/i386/hvf-utils/x86_decode.c:899:
+ {0xdf, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3703: FILE: target/i386/hvf-utils/x86_decode.c:900:
+ $
ERROR: line over 90 characters
#3704: FILE: target/i386/hvf-utils/x86_decode.c:901:
+ {0xe0, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3705: FILE: target/i386/hvf-utils/x86_decode.c:902:
+ {0xe1, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3706: FILE: target/i386/hvf-utils/x86_decode.c:903:
+ {0xe2, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3707: FILE: target/i386/hvf-utils/x86_decode.c:904:
+ $
ERROR: line over 90 characters
#3708: FILE: target/i386/hvf-utils/x86_decode.c:905:
+ {0xe3, X86_DECODE_CMD_JCXZ, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3709: FILE: target/i386/hvf-utils/x86_decode.c:906:
+ $
ERROR: line over 90 characters
#3710: FILE: target/i386/hvf-utils/x86_decode.c:907:
+ {0xe4, X86_DECODE_CMD_IN, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3711: FILE: target/i386/hvf-utils/x86_decode.c:908:
+ {0xe5, X86_DECODE_CMD_IN, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3712: FILE: target/i386/hvf-utils/x86_decode.c:909:
+ {0xe6, X86_DECODE_CMD_OUT, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3713: FILE: target/i386/hvf-utils/x86_decode.c:910:
+ {0xe7, X86_DECODE_CMD_OUT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3714: FILE: target/i386/hvf-utils/x86_decode.c:911:
+ {0xe8, X86_DECODE_CMD_CALL_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3715: FILE: target/i386/hvf-utils/x86_decode.c:912:
+ {0xe9, X86_DECODE_CMD_JMP_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3716: FILE: target/i386/hvf-utils/x86_decode.c:913:
+ {0xea, X86_DECODE_CMD_JMP_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3717: FILE: target/i386/hvf-utils/x86_decode.c:914:
+ {0xeb, X86_DECODE_CMD_JMP_NEAR, 1, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3718: FILE: target/i386/hvf-utils/x86_decode.c:915:
+ {0xec, X86_DECODE_CMD_IN, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3719: FILE: target/i386/hvf-utils/x86_decode.c:916:
+ {0xed, X86_DECODE_CMD_IN, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3720: FILE: target/i386/hvf-utils/x86_decode.c:917:
+ {0xee, X86_DECODE_CMD_OUT, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3721: FILE: target/i386/hvf-utils/x86_decode.c:918:
+ {0xef, X86_DECODE_CMD_OUT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3722: FILE: target/i386/hvf-utils/x86_decode.c:919:
+ $
WARNING: line over 80 characters
#3723: FILE: target/i386/hvf-utils/x86_decode.c:920:
+ {0xf4, X86_DECODE_CMD_HLT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3724: FILE: target/i386/hvf-utils/x86_decode.c:921:
+ $
WARNING: line over 80 characters
#3725: FILE: target/i386/hvf-utils/x86_decode.c:922:
+ {0xf5, X86_DECODE_CMD_CMC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
ERROR: trailing whitespace
#3726: FILE: target/i386/hvf-utils/x86_decode.c:923:
+ $
ERROR: line over 90 characters
#3727: FILE: target/i386/hvf-utils/x86_decode.c:924:
+ {0xf6, X86_DECODE_CMD_INVL, 1, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3728: FILE: target/i386/hvf-utils/x86_decode.c:925:
+ {0xf7, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3729: FILE: target/i386/hvf-utils/x86_decode.c:926:
+ $
WARNING: line over 80 characters
#3730: FILE: target/i386/hvf-utils/x86_decode.c:927:
+ {0xf8, X86_DECODE_CMD_CLC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
WARNING: line over 80 characters
#3731: FILE: target/i386/hvf-utils/x86_decode.c:928:
+ {0xf9, X86_DECODE_CMD_STC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
ERROR: trailing whitespace
#3732: FILE: target/i386/hvf-utils/x86_decode.c:929:
+ $
WARNING: line over 80 characters
#3733: FILE: target/i386/hvf-utils/x86_decode.c:930:
+ {0xfa, X86_DECODE_CMD_CLI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
WARNING: line over 80 characters
#3734: FILE: target/i386/hvf-utils/x86_decode.c:931:
+ {0xfb, X86_DECODE_CMD_STI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
WARNING: line over 80 characters
#3735: FILE: target/i386/hvf-utils/x86_decode.c:932:
+ {0xfc, X86_DECODE_CMD_CLD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
WARNING: line over 80 characters
#3736: FILE: target/i386/hvf-utils/x86_decode.c:933:
+ {0xfd, X86_DECODE_CMD_STD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
ERROR: line over 90 characters
#3737: FILE: target/i386/hvf-utils/x86_decode.c:934:
+ {0xfe, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, NULL, NULL, NULL, decode_incgroup2, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3738: FILE: target/i386/hvf-utils/x86_decode.c:935:
+ {0xff, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_ffgroup, RFLAGS_MASK_OSZAPC},
ERROR: that open brace { should be on the previous line
#3742: FILE: target/i386/hvf-utils/x86_decode.c:939:
+struct decode_tbl _2op_inst[] =
+{
ERROR: line over 90 characters
#3743: FILE: target/i386/hvf-utils/x86_decode.c:940:
+ {0x0, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_sldtgroup, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3744: FILE: target/i386/hvf-utils/x86_decode.c:941:
+ {0x1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_lidtgroup, RFLAGS_MASK_NONE},
WARNING: line over 80 characters
#3745: FILE: target/i386/hvf-utils/x86_decode.c:942:
+ {0x6, X86_DECODE_CMD_CLTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_TF},
ERROR: line over 90 characters
#3746: FILE: target/i386/hvf-utils/x86_decode.c:943:
+ {0x9, X86_DECODE_CMD_WBINVD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3747: FILE: target/i386/hvf-utils/x86_decode.c:944:
+ {0x18, X86_DECODE_CMD_PREFETCH, 0, true, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3748: FILE: target/i386/hvf-utils/x86_decode.c:945:
+ {0x1f, X86_DECODE_CMD_NOP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3749: FILE: target/i386/hvf-utils/x86_decode.c:946:
+ {0x20, X86_DECODE_CMD_MOV_FROM_CR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3750: FILE: target/i386/hvf-utils/x86_decode.c:947:
+ {0x21, X86_DECODE_CMD_MOV_FROM_DR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3751: FILE: target/i386/hvf-utils/x86_decode.c:948:
+ {0x22, X86_DECODE_CMD_MOV_TO_CR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3752: FILE: target/i386/hvf-utils/x86_decode.c:949:
+ {0x23, X86_DECODE_CMD_MOV_TO_DR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3753: FILE: target/i386/hvf-utils/x86_decode.c:950:
+ {0x30, X86_DECODE_CMD_WRMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3754: FILE: target/i386/hvf-utils/x86_decode.c:951:
+ {0x31, X86_DECODE_CMD_RDTSC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3755: FILE: target/i386/hvf-utils/x86_decode.c:952:
+ {0x32, X86_DECODE_CMD_RDMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3756: FILE: target/i386/hvf-utils/x86_decode.c:953:
+ {0x40, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3757: FILE: target/i386/hvf-utils/x86_decode.c:954:
+ {0x41, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3758: FILE: target/i386/hvf-utils/x86_decode.c:955:
+ {0x42, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3759: FILE: target/i386/hvf-utils/x86_decode.c:956:
+ {0x43, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3760: FILE: target/i386/hvf-utils/x86_decode.c:957:
+ {0x44, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3761: FILE: target/i386/hvf-utils/x86_decode.c:958:
+ {0x45, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3762: FILE: target/i386/hvf-utils/x86_decode.c:959:
+ {0x46, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3763: FILE: target/i386/hvf-utils/x86_decode.c:960:
+ {0x47, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3764: FILE: target/i386/hvf-utils/x86_decode.c:961:
+ {0x48, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3765: FILE: target/i386/hvf-utils/x86_decode.c:962:
+ {0x49, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3766: FILE: target/i386/hvf-utils/x86_decode.c:963:
+ {0x4a, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3767: FILE: target/i386/hvf-utils/x86_decode.c:964:
+ {0x4b, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3768: FILE: target/i386/hvf-utils/x86_decode.c:965:
+ {0x4c, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3769: FILE: target/i386/hvf-utils/x86_decode.c:966:
+ {0x4d, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3770: FILE: target/i386/hvf-utils/x86_decode.c:967:
+ {0x4e, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3771: FILE: target/i386/hvf-utils/x86_decode.c:968:
+ {0x4f, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3772: FILE: target/i386/hvf-utils/x86_decode.c:969:
+ {0x77, X86_DECODE_CMD_EMMS, 0, false, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3773: FILE: target/i386/hvf-utils/x86_decode.c:970:
+ {0x82, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3774: FILE: target/i386/hvf-utils/x86_decode.c:971:
+ {0x83, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3775: FILE: target/i386/hvf-utils/x86_decode.c:972:
+ {0x84, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3776: FILE: target/i386/hvf-utils/x86_decode.c:973:
+ {0x85, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3777: FILE: target/i386/hvf-utils/x86_decode.c:974:
+ {0x86, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3778: FILE: target/i386/hvf-utils/x86_decode.c:975:
+ {0x87, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3779: FILE: target/i386/hvf-utils/x86_decode.c:976:
+ {0x88, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3780: FILE: target/i386/hvf-utils/x86_decode.c:977:
+ {0x89, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3781: FILE: target/i386/hvf-utils/x86_decode.c:978:
+ {0x8a, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3782: FILE: target/i386/hvf-utils/x86_decode.c:979:
+ {0x8b, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3783: FILE: target/i386/hvf-utils/x86_decode.c:980:
+ {0x8c, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3784: FILE: target/i386/hvf-utils/x86_decode.c:981:
+ {0x8d, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3785: FILE: target/i386/hvf-utils/x86_decode.c:982:
+ {0x8e, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3786: FILE: target/i386/hvf-utils/x86_decode.c:983:
+ {0x8f, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3787: FILE: target/i386/hvf-utils/x86_decode.c:984:
+ {0x90, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3788: FILE: target/i386/hvf-utils/x86_decode.c:985:
+ {0x91, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3789: FILE: target/i386/hvf-utils/x86_decode.c:986:
+ {0x92, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3790: FILE: target/i386/hvf-utils/x86_decode.c:987:
+ {0x93, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3791: FILE: target/i386/hvf-utils/x86_decode.c:988:
+ {0x94, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3792: FILE: target/i386/hvf-utils/x86_decode.c:989:
+ {0x95, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3793: FILE: target/i386/hvf-utils/x86_decode.c:990:
+ {0x96, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3794: FILE: target/i386/hvf-utils/x86_decode.c:991:
+ {0x97, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3795: FILE: target/i386/hvf-utils/x86_decode.c:992:
+ {0x98, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3796: FILE: target/i386/hvf-utils/x86_decode.c:993:
+ {0x99, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3797: FILE: target/i386/hvf-utils/x86_decode.c:994:
+ {0x9a, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3798: FILE: target/i386/hvf-utils/x86_decode.c:995:
+ {0x9b, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3799: FILE: target/i386/hvf-utils/x86_decode.c:996:
+ {0x9c, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3800: FILE: target/i386/hvf-utils/x86_decode.c:997:
+ {0x9d, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3801: FILE: target/i386/hvf-utils/x86_decode.c:998:
+ {0x9e, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3802: FILE: target/i386/hvf-utils/x86_decode.c:999:
+ {0x9f, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3803: FILE: target/i386/hvf-utils/x86_decode.c:1000:
+ $
ERROR: line over 90 characters
#3804: FILE: target/i386/hvf-utils/x86_decode.c:1001:
+ {0xb0, X86_DECODE_CMD_CMPXCHG, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3805: FILE: target/i386/hvf-utils/x86_decode.c:1002:
+ {0xb1, X86_DECODE_CMD_CMPXCHG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3806: FILE: target/i386/hvf-utils/x86_decode.c:1003:
+ $
ERROR: line over 90 characters
#3807: FILE: target/i386/hvf-utils/x86_decode.c:1004:
+ {0xb6, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3808: FILE: target/i386/hvf-utils/x86_decode.c:1005:
+ {0xb7, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3809: FILE: target/i386/hvf-utils/x86_decode.c:1006:
+ {0xb8, X86_DECODE_CMD_POPCNT, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3810: FILE: target/i386/hvf-utils/x86_decode.c:1007:
+ {0xbe, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3811: FILE: target/i386/hvf-utils/x86_decode.c:1008:
+ {0xbf, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3812: FILE: target/i386/hvf-utils/x86_decode.c:1009:
+ {0xa0, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3813: FILE: target/i386/hvf-utils/x86_decode.c:1010:
+ {0xa1, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3814: FILE: target/i386/hvf-utils/x86_decode.c:1011:
+ {0xa2, X86_DECODE_CMD_CPUID, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3815: FILE: target/i386/hvf-utils/x86_decode.c:1012:
+ {0xa3, X86_DECODE_CMD_BT, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
ERROR: line over 90 characters
#3816: FILE: target/i386/hvf-utils/x86_decode.c:1013:
+ {0xa4, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3817: FILE: target/i386/hvf-utils/x86_decode.c:1014:
+ {0xa5, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3818: FILE: target/i386/hvf-utils/x86_decode.c:1015:
+ {0xa8, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3819: FILE: target/i386/hvf-utils/x86_decode.c:1016:
+ {0xa9, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3820: FILE: target/i386/hvf-utils/x86_decode.c:1017:
+ {0xab, X86_DECODE_CMD_BTS, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
ERROR: line over 90 characters
#3821: FILE: target/i386/hvf-utils/x86_decode.c:1018:
+ {0xac, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3822: FILE: target/i386/hvf-utils/x86_decode.c:1019:
+ {0xad, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3823: FILE: target/i386/hvf-utils/x86_decode.c:1020:
+ $
ERROR: line over 90 characters
#3824: FILE: target/i386/hvf-utils/x86_decode.c:1021:
+ {0xae, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_aegroup, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3825: FILE: target/i386/hvf-utils/x86_decode.c:1022:
+ $
ERROR: line over 90 characters
#3826: FILE: target/i386/hvf-utils/x86_decode.c:1023:
+ {0xaf, X86_DECODE_CMD_IMUL_2, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3827: FILE: target/i386/hvf-utils/x86_decode.c:1024:
+ {0xb2, X86_DECODE_CMD_LSS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3828: FILE: target/i386/hvf-utils/x86_decode.c:1025:
+ {0xb3, X86_DECODE_CMD_BTR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3829: FILE: target/i386/hvf-utils/x86_decode.c:1026:
+ {0xba, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_btgroup, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3830: FILE: target/i386/hvf-utils/x86_decode.c:1027:
+ {0xbb, X86_DECODE_CMD_BTC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3831: FILE: target/i386/hvf-utils/x86_decode.c:1028:
+ {0xbc, X86_DECODE_CMD_BSF, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: line over 90 characters
#3832: FILE: target/i386/hvf-utils/x86_decode.c:1029:
+ {0xbd, X86_DECODE_CMD_BSR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3833: FILE: target/i386/hvf-utils/x86_decode.c:1030:
+ $
ERROR: line over 90 characters
#3834: FILE: target/i386/hvf-utils/x86_decode.c:1031:
+ {0xc1, X86_DECODE_CMD_XADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
ERROR: trailing whitespace
#3835: FILE: target/i386/hvf-utils/x86_decode.c:1032:
+ $
ERROR: line over 90 characters
#3836: FILE: target/i386/hvf-utils/x86_decode.c:1033:
+ {0xc7, X86_DECODE_CMD_CMPXCHG8B, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_ZF},
ERROR: trailing whitespace
#3837: FILE: target/i386/hvf-utils/x86_decode.c:1034:
+ $
ERROR: line over 90 characters
#3838: FILE: target/i386/hvf-utils/x86_decode.c:1035:
+ {0xc8, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3839: FILE: target/i386/hvf-utils/x86_decode.c:1036:
+ {0xc9, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3840: FILE: target/i386/hvf-utils/x86_decode.c:1037:
+ {0xca, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3841: FILE: target/i386/hvf-utils/x86_decode.c:1038:
+ {0xcb, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3842: FILE: target/i386/hvf-utils/x86_decode.c:1039:
+ {0xcc, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3843: FILE: target/i386/hvf-utils/x86_decode.c:1040:
+ {0xcd, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3844: FILE: target/i386/hvf-utils/x86_decode.c:1041:
+ {0xce, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3845: FILE: target/i386/hvf-utils/x86_decode.c:1042:
+ {0xcf, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3848: FILE: target/i386/hvf-utils/x86_decode.c:1045:
+struct decode_x87_tbl invl_inst_x87 = {0x0, 0, 0, 0, 0, false, false, NULL, NULL, decode_invalid, 0};
ERROR: that open brace { should be on the previous line
#3851: FILE: target/i386/hvf-utils/x86_decode.c:1048:
+struct decode_x87_tbl _x87_inst[] =
+{
ERROR: line over 90 characters
#3852: FILE: target/i386/hvf-utils/x86_decode.c:1049:
+ {0xd8, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3853: FILE: target/i386/hvf-utils/x86_decode.c:1050:
+ {0xd8, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3854: FILE: target/i386/hvf-utils/x86_decode.c:1051:
+ {0xd8, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3855: FILE: target/i386/hvf-utils/x86_decode.c:1052:
+ {0xd8, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3856: FILE: target/i386/hvf-utils/x86_decode.c:1053:
+ {0xd8, 4, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3857: FILE: target/i386/hvf-utils/x86_decode.c:1054:
+ {0xd8, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3858: FILE: target/i386/hvf-utils/x86_decode.c:1055:
+ {0xd8, 5, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3859: FILE: target/i386/hvf-utils/x86_decode.c:1056:
+ {0xd8, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3860: FILE: target/i386/hvf-utils/x86_decode.c:1057:
+ {0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: space required after that ',' (ctx:VxV)
#3860: FILE: target/i386/hvf-utils/x86_decode.c:1057:
+ {0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
^
ERROR: line over 90 characters
#3861: FILE: target/i386/hvf-utils/x86_decode.c:1058:
+ {0xd8, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3862: FILE: target/i386/hvf-utils/x86_decode.c:1059:
+ {0xd8, 7, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3863: FILE: target/i386/hvf-utils/x86_decode.c:1060:
+ {0xd8, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3864: FILE: target/i386/hvf-utils/x86_decode.c:1061:
+ $
ERROR: line over 90 characters
#3865: FILE: target/i386/hvf-utils/x86_decode.c:1062:
+ {0xd9, 0, 3, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3866: FILE: target/i386/hvf-utils/x86_decode.c:1063:
+ {0xd9, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3867: FILE: target/i386/hvf-utils/x86_decode.c:1064:
+ {0xd9, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3868: FILE: target/i386/hvf-utils/x86_decode.c:1065:
+ {0xd9, 1, 0, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3869: FILE: target/i386/hvf-utils/x86_decode.c:1066:
+ {0xd9, 2, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3870: FILE: target/i386/hvf-utils/x86_decode.c:1067:
+ {0xd9, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3871: FILE: target/i386/hvf-utils/x86_decode.c:1068:
+ {0xd9, 3, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3872: FILE: target/i386/hvf-utils/x86_decode.c:1069:
+ {0xd9, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3873: FILE: target/i386/hvf-utils/x86_decode.c:1070:
+ {0xd9, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, decode_d9_4, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3874: FILE: target/i386/hvf-utils/x86_decode.c:1071:
+ {0xd9, 4, 0, X86_DECODE_CMD_INVL, 4, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3875: FILE: target/i386/hvf-utils/x86_decode.c:1072:
+ {0xd9, 5, 3, X86_DECODE_CMD_FLDxx, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3876: FILE: target/i386/hvf-utils/x86_decode.c:1073:
+ {0xd9, 5, 0, X86_DECODE_CMD_FLDCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: do not use C99 // comments
#3877: FILE: target/i386/hvf-utils/x86_decode.c:1074:
+ //
ERROR: line over 90 characters
#3878: FILE: target/i386/hvf-utils/x86_decode.c:1075:
+ {0xd9, 7, 3, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3879: FILE: target/i386/hvf-utils/x86_decode.c:1076:
+ {0xd9, 7, 0, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3880: FILE: target/i386/hvf-utils/x86_decode.c:1077:
+ $
ERROR: line over 90 characters
#3881: FILE: target/i386/hvf-utils/x86_decode.c:1078:
+ {0xda, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3882: FILE: target/i386/hvf-utils/x86_decode.c:1079:
+ {0xda, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3883: FILE: target/i386/hvf-utils/x86_decode.c:1080:
+ {0xda, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3884: FILE: target/i386/hvf-utils/x86_decode.c:1081:
+ {0xda, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3885: FILE: target/i386/hvf-utils/x86_decode.c:1082:
+ {0xda, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3886: FILE: target/i386/hvf-utils/x86_decode.c:1083:
+ {0xda, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3887: FILE: target/i386/hvf-utils/x86_decode.c:1084:
+ {0xda, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3888: FILE: target/i386/hvf-utils/x86_decode.c:1085:
+ {0xda, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3889: FILE: target/i386/hvf-utils/x86_decode.c:1086:
+ {0xda, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3890: FILE: target/i386/hvf-utils/x86_decode.c:1087:
+ {0xda, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3891: FILE: target/i386/hvf-utils/x86_decode.c:1088:
+ {0xda, 6, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3892: FILE: target/i386/hvf-utils/x86_decode.c:1089:
+ {0xda, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3893: FILE: target/i386/hvf-utils/x86_decode.c:1090:
+ {0xda, 7, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3894: FILE: target/i386/hvf-utils/x86_decode.c:1091:
+ {0xda, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3895: FILE: target/i386/hvf-utils/x86_decode.c:1092:
+ $
ERROR: line over 90 characters
#3896: FILE: target/i386/hvf-utils/x86_decode.c:1093:
+ {0xdb, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3897: FILE: target/i386/hvf-utils/x86_decode.c:1094:
+ {0xdb, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3898: FILE: target/i386/hvf-utils/x86_decode.c:1095:
+ {0xdb, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3899: FILE: target/i386/hvf-utils/x86_decode.c:1096:
+ {0xdb, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3900: FILE: target/i386/hvf-utils/x86_decode.c:1097:
+ {0xdb, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3901: FILE: target/i386/hvf-utils/x86_decode.c:1098:
+ {0xdb, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3902: FILE: target/i386/hvf-utils/x86_decode.c:1099:
+ {0xdb, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3903: FILE: target/i386/hvf-utils/x86_decode.c:1100:
+ {0xdb, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, decode_db_4, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3904: FILE: target/i386/hvf-utils/x86_decode.c:1101:
+ {0xdb, 4, 0, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3905: FILE: target/i386/hvf-utils/x86_decode.c:1102:
+ {0xdb, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3906: FILE: target/i386/hvf-utils/x86_decode.c:1103:
+ {0xdb, 5, 0, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3907: FILE: target/i386/hvf-utils/x86_decode.c:1104:
+ {0xdb, 7, 0, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3908: FILE: target/i386/hvf-utils/x86_decode.c:1105:
+ $
ERROR: line over 90 characters
#3909: FILE: target/i386/hvf-utils/x86_decode.c:1106:
+ {0xdc, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3910: FILE: target/i386/hvf-utils/x86_decode.c:1107:
+ {0xdc, 0, 0, X86_DECODE_CMD_FADD, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3911: FILE: target/i386/hvf-utils/x86_decode.c:1108:
+ {0xdc, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3912: FILE: target/i386/hvf-utils/x86_decode.c:1109:
+ {0xdc, 1, 0, X86_DECODE_CMD_FMUL, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3913: FILE: target/i386/hvf-utils/x86_decode.c:1110:
+ {0xdc, 4, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3914: FILE: target/i386/hvf-utils/x86_decode.c:1111:
+ {0xdc, 4, 0, X86_DECODE_CMD_FSUB, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3915: FILE: target/i386/hvf-utils/x86_decode.c:1112:
+ {0xdc, 5, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3916: FILE: target/i386/hvf-utils/x86_decode.c:1113:
+ {0xdc, 5, 0, X86_DECODE_CMD_FSUB, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3917: FILE: target/i386/hvf-utils/x86_decode.c:1114:
+ {0xdc, 6, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3918: FILE: target/i386/hvf-utils/x86_decode.c:1115:
+ {0xdc, 6, 0, X86_DECODE_CMD_FDIV, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3919: FILE: target/i386/hvf-utils/x86_decode.c:1116:
+ {0xdc, 7, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3920: FILE: target/i386/hvf-utils/x86_decode.c:1117:
+ {0xdc, 7, 0, X86_DECODE_CMD_FDIV, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3921: FILE: target/i386/hvf-utils/x86_decode.c:1118:
+ $
ERROR: line over 90 characters
#3922: FILE: target/i386/hvf-utils/x86_decode.c:1119:
+ {0xdd, 0, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3923: FILE: target/i386/hvf-utils/x86_decode.c:1120:
+ {0xdd, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3924: FILE: target/i386/hvf-utils/x86_decode.c:1121:
+ {0xdd, 2, 3, X86_DECODE_CMD_FST, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3925: FILE: target/i386/hvf-utils/x86_decode.c:1122:
+ {0xdd, 2, 0, X86_DECODE_CMD_FST, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3926: FILE: target/i386/hvf-utils/x86_decode.c:1123:
+ {0xdd, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3927: FILE: target/i386/hvf-utils/x86_decode.c:1124:
+ {0xdd, 3, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3928: FILE: target/i386/hvf-utils/x86_decode.c:1125:
+ {0xdd, 4, 3, X86_DECODE_CMD_FUCOM, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3929: FILE: target/i386/hvf-utils/x86_decode.c:1126:
+ {0xdd, 4, 0, X86_DECODE_CMD_FRSTOR, 8, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3930: FILE: target/i386/hvf-utils/x86_decode.c:1127:
+ {0xdd, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3931: FILE: target/i386/hvf-utils/x86_decode.c:1128:
+ {0xdd, 7, 0, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3932: FILE: target/i386/hvf-utils/x86_decode.c:1129:
+ {0xdd, 7, 3, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3933: FILE: target/i386/hvf-utils/x86_decode.c:1130:
+ $
ERROR: line over 90 characters
#3934: FILE: target/i386/hvf-utils/x86_decode.c:1131:
+ {0xde, 0, 3, X86_DECODE_CMD_FADD, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3935: FILE: target/i386/hvf-utils/x86_decode.c:1132:
+ {0xde, 0, 0, X86_DECODE_CMD_FADD, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3936: FILE: target/i386/hvf-utils/x86_decode.c:1133:
+ {0xde, 1, 3, X86_DECODE_CMD_FMUL, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3937: FILE: target/i386/hvf-utils/x86_decode.c:1134:
+ {0xde, 1, 0, X86_DECODE_CMD_FMUL, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3938: FILE: target/i386/hvf-utils/x86_decode.c:1135:
+ {0xde, 4, 3, X86_DECODE_CMD_FSUB, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3939: FILE: target/i386/hvf-utils/x86_decode.c:1136:
+ {0xde, 4, 0, X86_DECODE_CMD_FSUB, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3940: FILE: target/i386/hvf-utils/x86_decode.c:1137:
+ {0xde, 5, 3, X86_DECODE_CMD_FSUB, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3941: FILE: target/i386/hvf-utils/x86_decode.c:1138:
+ {0xde, 5, 0, X86_DECODE_CMD_FSUB, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3942: FILE: target/i386/hvf-utils/x86_decode.c:1139:
+ {0xde, 6, 3, X86_DECODE_CMD_FDIV, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3943: FILE: target/i386/hvf-utils/x86_decode.c:1140:
+ {0xde, 6, 0, X86_DECODE_CMD_FDIV, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3944: FILE: target/i386/hvf-utils/x86_decode.c:1141:
+ {0xde, 7, 3, X86_DECODE_CMD_FDIV, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3945: FILE: target/i386/hvf-utils/x86_decode.c:1142:
+ {0xde, 7, 0, X86_DECODE_CMD_FDIV, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
ERROR: trailing whitespace
#3946: FILE: target/i386/hvf-utils/x86_decode.c:1143:
+ $
ERROR: line over 90 characters
#3947: FILE: target/i386/hvf-utils/x86_decode.c:1144:
+ {0xdf, 0, 0, X86_DECODE_CMD_FLD, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3948: FILE: target/i386/hvf-utils/x86_decode.c:1145:
+ {0xdf, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3949: FILE: target/i386/hvf-utils/x86_decode.c:1146:
+ {0xdf, 2, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3950: FILE: target/i386/hvf-utils/x86_decode.c:1147:
+ {0xdf, 2, 0, X86_DECODE_CMD_FST, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3951: FILE: target/i386/hvf-utils/x86_decode.c:1148:
+ {0xdf, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3952: FILE: target/i386/hvf-utils/x86_decode.c:1149:
+ {0xdf, 3, 0, X86_DECODE_CMD_FST, 2, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3953: FILE: target/i386/hvf-utils/x86_decode.c:1150:
+ {0xdf, 4, 3, X86_DECODE_CMD_FNSTSW, 2, false, true, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3954: FILE: target/i386/hvf-utils/x86_decode.c:1151:
+ {0xdf, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3955: FILE: target/i386/hvf-utils/x86_decode.c:1152:
+ {0xdf, 5, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3956: FILE: target/i386/hvf-utils/x86_decode.c:1153:
+ {0xdf, 7, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
ERROR: line over 90 characters
#3959: FILE: target/i386/hvf-utils/x86_decode.c:1156:
+void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: braces {} are necessary for all arms of this statement
#3969: FILE: target/i386/hvf-utils/x86_decode.c:1166:
+ if (decode->displacement_size)
[...]
ERROR: switch and case should be at the same indent
#3972: FILE: target/i386/hvf-utils/x86_decode.c:1169:
+ switch (decode->modrm.rm) {
+ case 0:
[...]
+ case 1:
[...]
+ case 2:
[...]
+ case 3:
[...]
+ case 4:
[...]
+ case 5:
[...]
+ case 6:
[...]
+ case 7:
ERROR: braces {} are necessary for all arms of this statement
#4002: FILE: target/i386/hvf-utils/x86_decode.c:1199:
+ if (X86_DECODE_CMD_LEA == decode->cmd)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4013: FILE: target/i386/hvf-utils/x86_decode.c:1210:
+ if (is_extended)
[...]
ERROR: switch and case should be at the same indent
#4017: FILE: target/i386/hvf-utils/x86_decode.c:1214:
+ switch (size) {
+ case 1:
[...]
+ default:
ERROR: "(foo*)" should be "(foo *)"
#4038: FILE: target/i386/hvf-utils/x86_decode.c:1235:
+ memcpy(&val, (void*)get_reg_ref(cpu, reg, is_extended, size), size);
WARNING: line over 80 characters
#4042: FILE: target/i386/hvf-utils/x86_decode.c:1239:
+static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode, x86_reg_segment *sel)
ERROR: braces {} are necessary for all arms of this statement
#4053: FILE: target/i386/hvf-utils/x86_decode.c:1250:
+ if (decode->rex.b)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4055: FILE: target/i386/hvf-utils/x86_decode.c:1252:
+ if (REG_RSP == base_reg || REG_RBP == base_reg)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4060: FILE: target/i386/hvf-utils/x86_decode.c:1257:
+ if (decode->rex.x)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4063: FILE: target/i386/hvf-utils/x86_decode.c:1260:
+ if (index_reg != REG_RSP)
[...]
ERROR: line over 90 characters
#4064: FILE: target/i386/hvf-utils/x86_decode.c:1261:
+ scaled_index = get_reg_val(cpu, index_reg, decode->rex.x, addr_size) << decode->sib.scale;
ERROR: line over 90 characters
#4068: FILE: target/i386/hvf-utils/x86_decode.c:1265:
+void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: braces {} are necessary for all arms of this statement
#4074: FILE: target/i386/hvf-utils/x86_decode.c:1271:
+ if (decode->displacement_size)
[...]
ERROR: else should follow close brace '}'
#4080: FILE: target/i386/hvf-utils/x86_decode.c:1277:
+ }
+ else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
ERROR: braces {} are necessary for all arms of this statement
#4081: FILE: target/i386/hvf-utils/x86_decode.c:1278:
+ if (x86_is_long_mode(cpu))
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#4086: FILE: target/i386/hvf-utils/x86_decode.c:1283:
+ }
+ else {
ERROR: braces {} are necessary for all arms of this statement
#4087: FILE: target/i386/hvf-utils/x86_decode.c:1284:
+ if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4092: FILE: target/i386/hvf-utils/x86_decode.c:1289:
+ if (X86_DECODE_CMD_LEA == decode->cmd)
[...]
+ else
[...]
ERROR: line over 90 characters
#4098: FILE: target/i386/hvf-utils/x86_decode.c:1295:
+void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
ERROR: trailing whitespace
#4106: FILE: target/i386/hvf-utils/x86_decode.c:1303:
+ $
ERROR: braces {} are necessary for all arms of this statement
#4107: FILE: target/i386/hvf-utils/x86_decode.c:1304:
+ if (decode->displacement_size)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4110: FILE: target/i386/hvf-utils/x86_decode.c:1307:
+ if (4 == rm)
[...]
+ else if (0 == mod && 5 == rm)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4112: FILE: target/i386/hvf-utils/x86_decode.c:1309:
+ else if (0 == mod && 5 == rm)
[...]
+ else
[...]
ERROR: trailing whitespace
#4116: FILE: target/i386/hvf-utils/x86_decode.c:1313:
+ $
ERROR: braces {} are necessary for all arms of this statement
#4117: FILE: target/i386/hvf-utils/x86_decode.c:1314:
+ if (X86_DECODE_CMD_LEA == decode->cmd)
[...]
+ else
[...]
ERROR: line over 90 characters
#4124: FILE: target/i386/hvf-utils/x86_decode.c:1321:
+void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
WARNING: line over 80 characters
#4129: FILE: target/i386/hvf-utils/x86_decode.c:1326:
+ op->ptr = get_reg_ref(cpu, decode->modrm.rm, decode->rex.b, decode->operand_size);
ERROR: switch and case should be at the same indent
#4133: FILE: target/i386/hvf-utils/x86_decode.c:1330:
+ switch (decode->addressing_size) {
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
WARNING: line over 80 characters
#4144: FILE: target/i386/hvf-utils/x86_decode.c:1341:
+ VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
ERROR: switch and case should be at the same indent
#4153: FILE: target/i386/hvf-utils/x86_decode.c:1350:
+ switch (byte) {
+ case PREFIX_LOCK:
[...]
+ case PREFIX_REPN:
+ case PREFIX_REP:
[...]
+ case PREFIX_CS_SEG_OVEERIDE:
+ case PREFIX_SS_SEG_OVEERIDE:
+ case PREFIX_DS_SEG_OVEERIDE:
+ case PREFIX_ES_SEG_OVEERIDE:
+ case PREFIX_FS_SEG_OVEERIDE:
+ case PREFIX_GS_SEG_OVEERIDE:
[...]
+ case PREFIX_OP_SIZE_OVERRIDE:
[...]
+ case PREFIX_ADDR_SIZE_OVERRIDE:
[...]
+ case PREFIX_REX ... (PREFIX_REX + 0xf):
[...]
+ default:
ERROR: do not use C99 // comments
#4180: FILE: target/i386/hvf-utils/x86_decode.c:1377:
+ // fall through when not in long mode
ERROR: spaces required around that ':' (ctx:VxE)
#4181: FILE: target/i386/hvf-utils/x86_decode.c:1378:
+ default:
^
ERROR: braces {} are necessary for all arms of this statement
#4192: FILE: target/i386/hvf-utils/x86_decode.c:1389:
+ if (decode->addr_size_override)
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#4197: FILE: target/i386/hvf-utils/x86_decode.c:1394:
+ }
+ else if (!x86_is_long_mode(cpu)) {
ERROR: do not use C99 // comments
#4198: FILE: target/i386/hvf-utils/x86_decode.c:1395:
+ // protected
ERROR: do not use C99 // comments
#4201: FILE: target/i386/hvf-utils/x86_decode.c:1398:
+ // check db
ERROR: braces {} are necessary for all arms of this statement
#4203: FILE: target/i386/hvf-utils/x86_decode.c:1400:
+ if (decode->addr_size_override)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4208: FILE: target/i386/hvf-utils/x86_decode.c:1405:
+ if (decode->addr_size_override)
[...]
+ else
[...]
ERROR: do not use C99 // comments
#4214: FILE: target/i386/hvf-utils/x86_decode.c:1411:
+ // long
ERROR: braces {} are necessary for all arms of this statement
#4215: FILE: target/i386/hvf-utils/x86_decode.c:1412:
+ if (decode->addr_size_override)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4226: FILE: target/i386/hvf-utils/x86_decode.c:1423:
+ if (decode->op_size_override)
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#4231: FILE: target/i386/hvf-utils/x86_decode.c:1428:
+ }
+ else if (!x86_is_long_mode(cpu)) {
ERROR: do not use C99 // comments
#4232: FILE: target/i386/hvf-utils/x86_decode.c:1429:
+ // protected
ERROR: do not use C99 // comments
#4235: FILE: target/i386/hvf-utils/x86_decode.c:1432:
+ // check db
ERROR: braces {} are necessary for all arms of this statement
#4237: FILE: target/i386/hvf-utils/x86_decode.c:1434:
+ if (decode->op_size_override)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4242: FILE: target/i386/hvf-utils/x86_decode.c:1439:
+ if (decode->op_size_override)
[...]
+ else
[...]
ERROR: do not use C99 // comments
#4248: FILE: target/i386/hvf-utils/x86_decode.c:1445:
+ // long
ERROR: braces {} are necessary for all arms of this statement
#4249: FILE: target/i386/hvf-utils/x86_decode.c:1446:
+ if (decode->op_size_override)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4254: FILE: target/i386/hvf-utils/x86_decode.c:1451:
+ if (decode->rex.w)
[...]
ERROR: line over 90 characters
#4261: FILE: target/i386/hvf-utils/x86_decode.c:1458:
+ if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) && (decode->addressing_size != 2)) {
ERROR: line over 90 characters
#4269: FILE: target/i386/hvf-utils/x86_decode.c:1466:
+ * 00 [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] [disp16] [BX]
ERROR: code indent should never use tabs
#4269: FILE: target/i386/hvf-utils/x86_decode.c:1466:
+ * 00^I[BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] [disp16]^I[BX]$
ERROR: line over 90 characters
#4270: FILE: target/i386/hvf-utils/x86_decode.c:1467:
+ * 01 [BX+SI+disp8] [BX+DI+disp8] [BP+SI+disp8] [BP+DI+disp8] [SI+disp8] [DI+disp8] [BP+disp8] [BX+disp8]
ERROR: code indent should never use tabs
#4270: FILE: target/i386/hvf-utils/x86_decode.c:1467:
+ * 01^I[BX+SI+disp8]^I[BX+DI+disp8]^I[BP+SI+disp8]^I[BP+DI+disp8]^I[SI+disp8]^I[DI+disp8]^I[BP+disp8]^I[BX+disp8]$
ERROR: line over 90 characters
#4271: FILE: target/i386/hvf-utils/x86_decode.c:1468:
+ * 10 [BX+SI+disp16] [BX+DI+disp16] [BP+SI+disp16] [BP+DI+disp16] [SI+disp16] [DI+disp16] [BP+disp16] [BX+disp16]
ERROR: code indent should never use tabs
#4271: FILE: target/i386/hvf-utils/x86_decode.c:1468:
+ * 10^I[BX+SI+disp16]^I[BX+DI+disp16]^I[BP+SI+disp16]^I[BP+DI+disp16]^I[SI+disp16]^I[DI+disp16]^I[BP+disp16]^I[BX+disp16]$
ERROR: line over 90 characters
#4272: FILE: target/i386/hvf-utils/x86_decode.c:1469:
+ * 11 - - - - - - - -
ERROR: that open brace { should be on the previous line
#4275: FILE: target/i386/hvf-utils/x86_decode.c:1472:
+int disp16_tbl[4][8] =
+ {{0, 0, 0, 0, 0, 0, 2, 0},
ERROR: space required after that close brace '}'
#4278: FILE: target/i386/hvf-utils/x86_decode.c:1475:
+ {0, 0, 0, 0, 0, 0, 0, 0}};
ERROR: code indent should never use tabs
#4281: FILE: target/i386/hvf-utils/x86_decode.c:1478:
+ 32/64-bit^I modrm$
ERROR: line over 90 characters
#4283: FILE: target/i386/hvf-utils/x86_decode.c:1480:
+ 00 [r/m] [r/m] [r/m] [r/m] [SIB] [RIP/EIP1,2+disp32] [r/m] [r/m]
ERROR: line over 90 characters
#4284: FILE: target/i386/hvf-utils/x86_decode.c:1481:
+ 01 [r/m+disp8] [r/m+disp8] [r/m+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8]
ERROR: line over 90 characters
#4285: FILE: target/i386/hvf-utils/x86_decode.c:1482:
+ 10 [r/m+disp32] [r/m+disp32] [r/m+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32]
ERROR: code indent should never use tabs
#4285: FILE: target/i386/hvf-utils/x86_decode.c:1482:
+ 10 [r/m+disp32] [r/m+disp32] [r/m+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32] [SIB+disp32]^I [r/m+disp32]$
ERROR: line over 90 characters
#4286: FILE: target/i386/hvf-utils/x86_decode.c:1483:
+ 11 - - - - - - - -
ERROR: that open brace { should be on the previous line
#4289: FILE: target/i386/hvf-utils/x86_decode.c:1486:
+int disp32_tbl[4][8] =
+ {{0, 0, 0, 0, -1, 4, 0, 0},
ERROR: space required after that close brace '}'
#4292: FILE: target/i386/hvf-utils/x86_decode.c:1489:
+ {0, 0, 0, 0, 0, 0, 0, 0}};
ERROR: trailing whitespace
#4299: FILE: target/i386/hvf-utils/x86_decode.c:1496:
+ $
ERROR: switch and case should be at the same indent
#4301: FILE: target/i386/hvf-utils/x86_decode.c:1498:
+ switch (addressing_size) {
+ case 2:
[...]
+ case 4:
+ case 8:
ERROR: braces {} are necessary for all arms of this statement
#4304: FILE: target/i386/hvf-utils/x86_decode.c:1501:
+ if (decode->displacement_size)
[...]
ERROR: line over 90 characters
#4305: FILE: target/i386/hvf-utils/x86_decode.c:1502:
+ decode->displacement = (uint16_t)decode_bytes(cpu, decode, decode->displacement_size);
ERROR: braces {} are necessary for all arms of this statement
#4309: FILE: target/i386/hvf-utils/x86_decode.c:1506:
+ if (-1 == disp32_tbl[mod][rm]) {
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#4310: FILE: target/i386/hvf-utils/x86_decode.c:1507:
+ if (5 == decode->sib.base)
[...]
ERROR: else should follow close brace '}'
#4313: FILE: target/i386/hvf-utils/x86_decode.c:1510:
+ }
+ else
ERROR: trailing whitespace
#4315: FILE: target/i386/hvf-utils/x86_decode.c:1512:
+ $
ERROR: braces {} are necessary for all arms of this statement
#4316: FILE: target/i386/hvf-utils/x86_decode.c:1513:
+ if (decode->displacement_size)
[...]
ERROR: line over 90 characters
#4317: FILE: target/i386/hvf-utils/x86_decode.c:1514:
+ decode->displacement = (uint32_t)decode_bytes(cpu, decode, decode->displacement_size);
ERROR: trailing whitespace
#4326: FILE: target/i386/hvf-utils/x86_decode.c:1523:
+ $
ERROR: line over 90 characters
#4331: FILE: target/i386/hvf-utils/x86_decode.c:1528:
+static inline void decode_opcode_general(CPUState *cpu, struct x86_decode *decode, uint8_t opcode, struct decode_tbl *inst_decoder)
ERROR: braces {} are necessary for all arms of this statement
#4334: FILE: target/i386/hvf-utils/x86_decode.c:1531:
+ if (inst_decoder->operand_size)
[...]
ERROR: trailing whitespace
#4337: FILE: target/i386/hvf-utils/x86_decode.c:1534:
+ $
ERROR: braces {} are necessary for all arms of this statement
#4338: FILE: target/i386/hvf-utils/x86_decode.c:1535:
+ if (inst_decoder->is_modrm)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4340: FILE: target/i386/hvf-utils/x86_decode.c:1537:
+ if (inst_decoder->decode_op1)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4342: FILE: target/i386/hvf-utils/x86_decode.c:1539:
+ if (inst_decoder->decode_op2)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4344: FILE: target/i386/hvf-utils/x86_decode.c:1541:
+ if (inst_decoder->decode_op3)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4346: FILE: target/i386/hvf-utils/x86_decode.c:1543:
+ if (inst_decoder->decode_op4)
[...]
ERROR: braces {} are necessary for all arms of this statement
#4348: FILE: target/i386/hvf-utils/x86_decode.c:1545:
+ if (inst_decoder->decode_postfix)
[...]
ERROR: line over 90 characters
#4352: FILE: target/i386/hvf-utils/x86_decode.c:1549:
+static inline void decode_opcode_1(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
ERROR: line over 90 characters
#4359: FILE: target/i386/hvf-utils/x86_decode.c:1556:
+static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
ERROR: trailing whitespace
#4368: FILE: target/i386/hvf-utils/x86_decode.c:1565:
+ $
ERROR: trailing whitespace
#4389: FILE: target/i386/hvf-utils/x86_decode.c:1586:
+ $
ERROR: trailing whitespace
#4396: FILE: target/i386/hvf-utils/x86_decode.c:1593:
+ $
ERROR: braces {} are necessary even for single statement blocks
#4397: FILE: target/i386/hvf-utils/x86_decode.c:1594:
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
+ memcpy(_decode_tbl1, &invl_inst, sizeof(invl_inst));
ERROR: braces {} are necessary even for single statement blocks
#4399: FILE: target/i386/hvf-utils/x86_decode.c:1596:
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
+ memcpy(_decode_tbl2, &invl_inst, sizeof(invl_inst));
ERROR: braces {} are necessary even for single statement blocks
#4401: FILE: target/i386/hvf-utils/x86_decode.c:1598:
+ for (i = 0; i < ARRAY_SIZE(_decode_tbl3); i++)
+ memcpy(_decode_tbl3, &invl_inst, sizeof(invl_inst_x87));
ERROR: trailing whitespace
#4403: FILE: target/i386/hvf-utils/x86_decode.c:1600:
+ $
ERROR: line over 90 characters
#4411: FILE: target/i386/hvf-utils/x86_decode.c:1608:
+ int index = ((_x87_inst[i].opcode & 0xf) << 4) | ((_x87_inst[i].modrm_mod & 1) << 3) | _x87_inst[i].modrm_reg;
ERROR: line over 90 characters
#4419: FILE: target/i386/hvf-utils/x86_decode.c:1616:
+ static const char *cmds[] = {"INVL", "PUSH", "PUSH_SEG", "POP", "POP_SEG", "MOV", "MOVSX", "MOVZX", "CALL_NEAR",
ERROR: line over 90 characters
#4420: FILE: target/i386/hvf-utils/x86_decode.c:1617:
+ "CALL_NEAR_ABS_INDIRECT", "CALL_FAR_ABS_INDIRECT", "CMD_CALL_FAR", "RET_NEAR", "RET_FAR", "ADD", "OR",
ERROR: line over 90 characters
#4421: FILE: target/i386/hvf-utils/x86_decode.c:1618:
+ "ADC", "SBB", "AND", "SUB", "XOR", "CMP", "INC", "DEC", "TST", "NOT", "NEG", "JMP_NEAR", "JMP_NEAR_ABS_INDIRECT",
WARNING: line over 80 characters
#4423: FILE: target/i386/hvf-utils/x86_decode.c:1620:
+ "JCXZ", "SETXX", "MOV_TO_SEG", "MOV_FROM_SEG", "CLI", "STI", "CLD", "STD", "STC",
ERROR: line over 90 characters
#4424: FILE: target/i386/hvf-utils/x86_decode.c:1621:
+ "CLC", "OUT", "IN", "INS", "OUTS", "LIDT", "SIDT", "LGDT", "SGDT", "SMSW", "LMSW", "RDTSCP", "INVLPG", "MOV_TO_CR",
ERROR: line over 90 characters
#4425: FILE: target/i386/hvf-utils/x86_decode.c:1622:
+ "MOV_FROM_CR", "MOV_TO_DR", "MOV_FROM_DR", "PUSHF", "POPF", "CPUID", "ROL", "ROR", "RCL", "RCR", "SHL", "SAL",
ERROR: line over 90 characters
#4426: FILE: target/i386/hvf-utils/x86_decode.c:1623:
+ "SHR","SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL", "IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS",
ERROR: space required after that ',' (ctx:VxV)
#4426: FILE: target/i386/hvf-utils/x86_decode.c:1623:
+ "SHR","SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL", "IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS",
^
ERROR: line over 90 characters
#4427: FILE: target/i386/hvf-utils/x86_decode.c:1624:
+ "LODS", "STOS", "BSWAP", "XCHG", "RDTSC", "RDMSR", "WRMSR", "ENTER", "LEAVE", "BT", "BTS", "BTC", "BTR", "BSF",
ERROR: line over 90 characters
#4428: FILE: target/i386/hvf-utils/x86_decode.c:1625:
+ "BSR", "IRET", "INT", "POPA", "PUSHA", "CWD", "CBW", "DAS", "AAD", "AAM", "AAS", "LOOP", "SLDT", "STR", "LLDT",
ERROR: line over 90 characters
#4429: FILE: target/i386/hvf-utils/x86_decode.c:1626:
+ "LTR", "VERR", "VERW", "SAHF", "LAHF", "WBINVD", "LDS", "LSS", "LES", "LGS", "LFS", "CMC", "XLAT", "NOP", "CMOV",
ERROR: line over 90 characters
#4431: FILE: target/i386/hvf-utils/x86_decode.c:1628:
+ "FNINIT", "FLD", "FLDxx", "FNSTCW", "FNSTSW", "FNSETPM", "FSAVE", "FRSTOR", "FXSAVE", "FXRSTOR", "FDIV", "FMUL",
ERROR: line over 90 characters
#4432: FILE: target/i386/hvf-utils/x86_decode.c:1629:
+ "FSUB", "FADD", "EMMS", "MFENCE", "SFENCE", "LFENCE", "PREFETCH", "FST", "FABS", "FUCOM", "FUCOMI", "FLDCW",
ERROR: line over 90 characters
#4437: FILE: target/i386/hvf-utils/x86_decode.c:1634:
+addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg)
ERROR: switch and case should be at the same indent
#4439: FILE: target/i386/hvf-utils/x86_decode.c:1636:
+ switch (decode->segment_override) {
+ case PREFIX_CS_SEG_OVEERIDE:
[...]
+ case PREFIX_SS_SEG_OVEERIDE:
[...]
+ case PREFIX_DS_SEG_OVEERIDE:
[...]
+ case PREFIX_ES_SEG_OVEERIDE:
[...]
+ case PREFIX_FS_SEG_OVEERIDE:
[...]
+ case PREFIX_GS_SEG_OVEERIDE:
[...]
+ default:
ERROR: do not use C99 // comments
#4496: FILE: target/i386/hvf-utils/x86_decode.h:28:
+ // group 1
ERROR: do not use C99 // comments
#4500: FILE: target/i386/hvf-utils/x86_decode.h:32:
+ // group 2
ERROR: do not use C99 // comments
#4507: FILE: target/i386/hvf-utils/x86_decode.h:39:
+ // group 3
ERROR: do not use C99 // comments
#4509: FILE: target/i386/hvf-utils/x86_decode.h:41:
+ // group 4
ERROR: trailing whitespace
#4517: FILE: target/i386/hvf-utils/x86_decode.h:49:
+ $
ERROR: trailing whitespace
#4648: FILE: target/i386/hvf-utils/x86_decode.h:180:
+ $
ERROR: do not use C99 // comments
#4726: FILE: target/i386/hvf-utils/x86_decode.h:258:
+ // for floating point computations
ERROR: line over 90 characters
#4779: FILE: target/i386/hvf-utils/x86_decode.h:311:
+void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op);
ERROR: line over 90 characters
#4780: FILE: target/i386/hvf-utils/x86_decode.h:312:
+addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg);
ERROR: "foo* bar" should be "foo *bar"
#4782: FILE: target/i386/hvf-utils/x86_decode.h:314:
+void init_decoder(CPUState* cpu);
WARNING: line over 80 characters
#4851: FILE: target/i386/hvf-utils/x86_descr.c:63:
+x68_segment_selector vmx_read_segment_selector(CPUState *cpu, x86_reg_segment seg)
ERROR: line over 90 characters
#4858: FILE: target/i386/hvf-utils/x86_descr.c:70:
+void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg)
ERROR: line over 90 characters
#4863: FILE: target/i386/hvf-utils/x86_descr.c:75:
+void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg)
ERROR: line over 90 characters
#4871: FILE: target/i386/hvf-utils/x86_descr.c:83:
+void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg)
ERROR: line over 90 characters
#4881: FILE: target/i386/hvf-utils/x86_descr.c:93:
+void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)
ERROR: line over 90 characters
#4898: FILE: target/i386/hvf-utils/x86_descr.c:110:
+void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc)
ERROR: trailing whitespace
#4902: FILE: target/i386/hvf-utils/x86_descr.c:114:
+ $
ERROR: do not use C99 // comments
#4948: FILE: target/i386/hvf-utils/x86_descr.h:30:
+// deal with vmstate descriptors
ERROR: line over 90 characters
#4949: FILE: target/i386/hvf-utils/x86_descr.h:31:
+void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
ERROR: line over 90 characters
#4950: FILE: target/i386/hvf-utils/x86_descr.h:32:
+void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
WARNING: line over 80 characters
#4952: FILE: target/i386/hvf-utils/x86_descr.h:34:
+x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, x86_reg_segment seg);
ERROR: line over 90 characters
#4953: FILE: target/i386/hvf-utils/x86_descr.h:35:
+void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg);
WARNING: line over 80 characters
#4956: FILE: target/i386/hvf-utils/x86_descr.h:38:
+void vmx_write_segment_base(struct CPUState *cpu, x86_reg_segment seg, uint64_t base);
ERROR: line over 90 characters
#4958: FILE: target/i386/hvf-utils/x86_descr.h:40:
+void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc);
ERROR: do not use C99 // comments
#4983: FILE: target/i386/hvf-utils/x86_emu.c:19:
+/////////////////////////////////////////////////////////////////////////
ERROR: do not use C99 // comments
#4984: FILE: target/i386/hvf-utils/x86_emu.c:20:
+//
ERROR: do not use C99 // comments
#4985: FILE: target/i386/hvf-utils/x86_emu.c:21:
+// Copyright (C) 2001-2012 The Bochs Project
ERROR: do not use C99 // comments
#4986: FILE: target/i386/hvf-utils/x86_emu.c:22:
+//
ERROR: do not use C99 // comments
#4987: FILE: target/i386/hvf-utils/x86_emu.c:23:
+// This library is free software; you can redistribute it and/or
ERROR: do not use C99 // comments
#4988: FILE: target/i386/hvf-utils/x86_emu.c:24:
+// modify it under the terms of the GNU Lesser General Public
ERROR: do not use C99 // comments
#4989: FILE: target/i386/hvf-utils/x86_emu.c:25:
+// License as published by the Free Software Foundation; either
ERROR: do not use C99 // comments
#4990: FILE: target/i386/hvf-utils/x86_emu.c:26:
+// version 2 of the License, or (at your option) any later version.
ERROR: do not use C99 // comments
#4991: FILE: target/i386/hvf-utils/x86_emu.c:27:
+//
ERROR: do not use C99 // comments
#4992: FILE: target/i386/hvf-utils/x86_emu.c:28:
+// This library is distributed in the hope that it will be useful,
ERROR: do not use C99 // comments
#4993: FILE: target/i386/hvf-utils/x86_emu.c:29:
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
ERROR: do not use C99 // comments
#4994: FILE: target/i386/hvf-utils/x86_emu.c:30:
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
ERROR: do not use C99 // comments
#4995: FILE: target/i386/hvf-utils/x86_emu.c:31:
+// Lesser General Public License for more details.
ERROR: do not use C99 // comments
#4996: FILE: target/i386/hvf-utils/x86_emu.c:32:
+//
ERROR: do not use C99 // comments
#4997: FILE: target/i386/hvf-utils/x86_emu.c:33:
+// You should have received a copy of the GNU Lesser General Public
ERROR: do not use C99 // comments
#4998: FILE: target/i386/hvf-utils/x86_emu.c:34:
+// License along with this library; if not, write to the Free Software
ERROR: do not use C99 // comments
#4999: FILE: target/i386/hvf-utils/x86_emu.c:35:
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
ERROR: do not use C99 // comments
#5000: FILE: target/i386/hvf-utils/x86_emu.c:36:
+/////////////////////////////////////////////////////////////////////////
ERROR: line over 90 characters
#5013: FILE: target/i386/hvf-utils/x86_emu.c:49:
+void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count);
ERROR: externs should be avoided in .c files
#5013: FILE: target/i386/hvf-utils/x86_emu.c:49:
+void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count);
ERROR: braces {} are necessary for all arms of this statement
#5024: FILE: target/i386/hvf-utils/x86_emu.c:60:
+ if (save_res) \
[...]
ERROR: braces {} are necessary for all arms of this statement
#5034: FILE: target/i386/hvf-utils/x86_emu.c:70:
+ if (save_res) \
[...]
ERROR: braces {} are necessary for all arms of this statement
#5044: FILE: target/i386/hvf-utils/x86_emu.c:80:
+ if (save_res) \
[...]
ERROR: braces {} are necessary for all arms of this statement
#5064: FILE: target/i386/hvf-utils/x86_emu.c:100:
+ if (save_res) \
[...]
ERROR: braces {} are necessary for all arms of this statement
#5074: FILE: target/i386/hvf-utils/x86_emu.c:110:
+ if (save_res) \
[...]
ERROR: braces {} are necessary for all arms of this statement
#5084: FILE: target/i386/hvf-utils/x86_emu.c:120:
+ if (save_res) \
[...]
ERROR: "foo* bar" should be "foo *bar"
#5094: FILE: target/i386/hvf-utils/x86_emu.c:130:
+addr_t read_reg(struct CPUState* cpu, int reg, int size)
ERROR: switch and case should be at the same indent
#5096: FILE: target/i386/hvf-utils/x86_emu.c:132:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: "foo* bar" should be "foo *bar"
#5111: FILE: target/i386/hvf-utils/x86_emu.c:147:
+void write_reg(struct CPUState* cpu, int reg, addr_t val, int size)
ERROR: switch and case should be at the same indent
#5113: FILE: target/i386/hvf-utils/x86_emu.c:149:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: trailing whitespace
#5134: FILE: target/i386/hvf-utils/x86_emu.c:170:
+ $
ERROR: switch and case should be at the same indent
#5135: FILE: target/i386/hvf-utils/x86_emu.c:171:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: "(foo*)" should be "(foo *)"
#5137: FILE: target/i386/hvf-utils/x86_emu.c:173:
+ val = *(uint8_t*)reg_ptr;
ERROR: "(foo*)" should be "(foo *)"
#5140: FILE: target/i386/hvf-utils/x86_emu.c:176:
+ val = *(uint16_t*)reg_ptr;
ERROR: "(foo*)" should be "(foo *)"
#5143: FILE: target/i386/hvf-utils/x86_emu.c:179:
+ val = *(uint32_t*)reg_ptr;
ERROR: "(foo*)" should be "(foo *)"
#5146: FILE: target/i386/hvf-utils/x86_emu.c:182:
+ val = *(uint64_t*)reg_ptr;
ERROR: switch and case should be at the same indent
#5157: FILE: target/i386/hvf-utils/x86_emu.c:193:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: "(foo*)" should be "(foo *)"
#5159: FILE: target/i386/hvf-utils/x86_emu.c:195:
+ *(uint8_t*)reg_ptr = val;
ERROR: "(foo*)" should be "(foo *)"
#5162: FILE: target/i386/hvf-utils/x86_emu.c:198:
+ *(uint16_t*)reg_ptr = val;
ERROR: "(foo*)" should be "(foo *)"
#5165: FILE: target/i386/hvf-utils/x86_emu.c:201:
+ *(uint64_t*)reg_ptr = (uint32_t)val;
ERROR: "(foo*)" should be "(foo *)"
#5168: FILE: target/i386/hvf-utils/x86_emu.c:204:
+ *(uint64_t*)reg_ptr = val;
ERROR: "foo* bar" should be "foo *bar"
#5176: FILE: target/i386/hvf-utils/x86_emu.c:212:
+static bool is_host_reg(struct CPUState* cpu, addr_t ptr) {
ERROR: open brace '{' following function declarations go on the next line
#5176: FILE: target/i386/hvf-utils/x86_emu.c:212:
+static bool is_host_reg(struct CPUState* cpu, addr_t ptr) {
ERROR: line over 90 characters
#5178: FILE: target/i386/hvf-utils/x86_emu.c:214:
+ (ptr > (addr_t)cpu->hvf_x86 && ptr < (addr_t)(cpu->hvf_x86 + sizeof(struct hvf_x86_state)));
ERROR: "foo* bar" should be "foo *bar"
#5181: FILE: target/i386/hvf-utils/x86_emu.c:217:
+void write_val_ext(struct CPUState* cpu, addr_t ptr, addr_t val, int size)
ERROR: "foo* bar" should be "foo *bar"
#5196: FILE: target/i386/hvf-utils/x86_emu.c:232:
+addr_t read_val_ext(struct CPUState* cpu, addr_t ptr, int size)
ERROR: trailing whitespace
#5200: FILE: target/i386/hvf-utils/x86_emu.c:236:
+ $
ERROR: trailing whitespace
#5204: FILE: target/i386/hvf-utils/x86_emu.c:240:
+ $
ERROR: switch and case should be at the same indent
#5206: FILE: target/i386/hvf-utils/x86_emu.c:242:
+ switch (size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ case 8:
[...]
+ default:
ERROR: "(foo*)" should be "(foo *)"
#5208: FILE: target/i386/hvf-utils/x86_emu.c:244:
+ val = *(uint8_t*)mmio_ptr;
ERROR: "(foo*)" should be "(foo *)"
#5211: FILE: target/i386/hvf-utils/x86_emu.c:247:
+ val = *(uint16_t*)mmio_ptr;
ERROR: "(foo*)" should be "(foo *)"
#5214: FILE: target/i386/hvf-utils/x86_emu.c:250:
+ val = *(uint32_t*)mmio_ptr;
ERROR: "(foo*)" should be "(foo *)"
#5217: FILE: target/i386/hvf-utils/x86_emu.c:253:
+ val = *(uint64_t*)mmio_ptr;
ERROR: line over 90 characters
#5226: FILE: target/i386/hvf-utils/x86_emu.c:262:
+static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode, int n, bool val_op0, bool val_op1, bool val_op2)
ERROR: switch and case should be at the same indent
#5232: FILE: target/i386/hvf-utils/x86_emu.c:268:
+ switch (decode->op[i].type) {
+ case X86_VAR_IMMEDIATE:
[...]
+ case X86_VAR_REG:
[...]
+ case X86_VAR_RM:
[...]
+ case X86_VAR_OFFSET:
[...]
+ default:
ERROR: braces {} are necessary for all arms of this statement
#5237: FILE: target/i386/hvf-utils/x86_emu.c:273:
+ if (calc_val[i])
[...]
ERROR: line over 90 characters
#5238: FILE: target/i386/hvf-utils/x86_emu.c:274:
+ decode->op[i].val = read_val_from_reg(decode->op[i].ptr, decode->operand_size);
ERROR: braces {} are necessary for all arms of this statement
#5242: FILE: target/i386/hvf-utils/x86_emu.c:278:
+ if (calc_val[i])
[...]
ERROR: line over 90 characters
#5243: FILE: target/i386/hvf-utils/x86_emu.c:279:
+ decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
ERROR: line over 90 characters
#5246: FILE: target/i386/hvf-utils/x86_emu.c:282:
+ decode->op[i].ptr = decode_linear_addr(cpu, decode, decode->op[i].ptr, REG_SEG_DS);
ERROR: braces {} are necessary for all arms of this statement
#5247: FILE: target/i386/hvf-utils/x86_emu.c:283:
+ if (calc_val[i])
[...]
ERROR: line over 90 characters
#5248: FILE: target/i386/hvf-utils/x86_emu.c:284:
+ decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
WARNING: line over 80 characters
#5259: FILE: target/i386/hvf-utils/x86_emu.c:295:
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
ERROR: spaces required around that '+' (ctx:WxV)
#5278: FILE: target/i386/hvf-utils/x86_emu.c:314:
+ EXEC_2OP_ARITH_CMD(cpu, decode, +get_CF(cpu)+, SET_FLAGS_OSZAPC_ADD, true);
^
ERROR: spaces required around that '+' (ctx:VxO)
#5278: FILE: target/i386/hvf-utils/x86_emu.c:314:
+ EXEC_2OP_ARITH_CMD(cpu, decode, +get_CF(cpu)+, SET_FLAGS_OSZAPC_ADD, true);
^
ERROR: spaces required around that '-' (ctx:VxO)
#5284: FILE: target/i386/hvf-utils/x86_emu.c:320:
+ EXEC_2OP_ARITH_CMD(cpu, decode, -get_CF(cpu)-, SET_FLAGS_OSZAPC_SUB, true);
^
ERROR: do not use C99 // comments
#5308: FILE: target/i386/hvf-utils/x86_emu.c:344:
+ //EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
ERROR: else should follow close brace '}'
#5318: FILE: target/i386/hvf-utils/x86_emu.c:354:
+ }
+ else if (2 == decode->operand_size) {
ERROR: else should follow close brace '}'
#5321: FILE: target/i386/hvf-utils/x86_emu.c:357:
+ }
+ else if (1 == decode->operand_size) {
ERROR: do not use C99 // comments
#5327: FILE: target/i386/hvf-utils/x86_emu.c:363:
+ //lflags_to_rflags(cpu);
ERROR: spaces required around that '+' (ctx:WxV)
#5342: FILE: target/i386/hvf-utils/x86_emu.c:378:
+ EXEC_2OP_ARITH_CMD(cpu, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
^
ERROR: spaces required around that '+' (ctx:VxO)
#5342: FILE: target/i386/hvf-utils/x86_emu.c:378:
+ EXEC_2OP_ARITH_CMD(cpu, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
^
ERROR: spaces required around that '-' (ctx:VxO)
#5352: FILE: target/i386/hvf-utils/x86_emu.c:388:
+ EXEC_2OP_ARITH_CMD(cpu, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
^
WARNING: line over 80 characters
#5366: FILE: target/i386/hvf-utils/x86_emu.c:402:
+ write_val_ext(cpu, decode->op[0].ptr, ~decode->op[0].val, decode->operand_size);
ERROR: braces {} are necessary for all arms of this statement
#5377: FILE: target/i386/hvf-utils/x86_emu.c:413:
+ if (0xb6 == decode->opcode[1])
[...]
+ else
[...]
ERROR: switch and case should be at the same indent
#5391: FILE: target/i386/hvf-utils/x86_emu.c:427:
+ switch (decode->opcode[0]) {
+ case 0xe6:
[...]
+ case 0xe7:
[...]
+ case 0xee:
[...]
+ case 0xef:
[...]
+ default:
WARNING: line over 80 characters
#5396: FILE: target/i386/hvf-utils/x86_emu.c:432:
+ hvf_handle_io(cpu, decode->op[0].val, &RAX(cpu), 1, decode->operand_size, 1);
ERROR: switch and case should be at the same indent
#5414: FILE: target/i386/hvf-utils/x86_emu.c:450:
+ switch (decode->opcode[0]) {
+ case 0xe4:
[...]
+ case 0xe5:
[...]
+ case 0xec:
[...]
+ case 0xed:
[...]
+ default:
WARNING: line over 80 characters
#5419: FILE: target/i386/hvf-utils/x86_emu.c:455:
+ hvf_handle_io(cpu, decode->op[0].val, &val, 0, decode->operand_size, 1);
ERROR: braces {} are necessary for all arms of this statement
#5420: FILE: target/i386/hvf-utils/x86_emu.c:456:
+ if (decode->operand_size == 2)
[...]
+ else
[...]
ERROR: braces {} are necessary for all arms of this statement
#5430: FILE: target/i386/hvf-utils/x86_emu.c:466:
+ if (decode->operand_size == 2)
[...]
+ else
[...]
ERROR: line over 90 characters
#5444: FILE: target/i386/hvf-utils/x86_emu.c:480:
+static inline void string_increment_reg(struct CPUState * cpu, int reg, struct x86_decode *decode)
ERROR: "foo * bar" should be "foo *bar"
#5444: FILE: target/i386/hvf-utils/x86_emu.c:480:
+static inline void string_increment_reg(struct CPUState * cpu, int reg, struct x86_decode *decode)
ERROR: braces {} are necessary for all arms of this statement
#5447: FILE: target/i386/hvf-utils/x86_emu.c:483:
+ if (cpu->hvf_x86->rflags.df)
[...]
+ else
[...]
ERROR: line over 90 characters
#5454: FILE: target/i386/hvf-utils/x86_emu.c:490:
+static inline void string_rep(struct CPUState * cpu, struct x86_decode *decode, void (*func)(struct CPUState *cpu, struct x86_decode *ins), int rep)
ERROR: "foo * bar" should be "foo *bar"
#5454: FILE: target/i386/hvf-utils/x86_emu.c:490:
+static inline void string_rep(struct CPUState * cpu, struct x86_decode *decode, void (*func)(struct CPUState *cpu, struct x86_decode *ins), int rep)
ERROR: braces {} are necessary for all arms of this statement
#5460: FILE: target/i386/hvf-utils/x86_emu.c:496:
+ if ((PREFIX_REP == rep) && !get_ZF(cpu))
[...]
ERROR: braces {} are necessary for all arms of this statement
#5462: FILE: target/i386/hvf-utils/x86_emu.c:498:
+ if ((PREFIX_REPN == rep) && get_ZF(cpu))
[...]
WARNING: line over 80 characters
#5469: FILE: target/i386/hvf-utils/x86_emu.c:505:
+ addr_t addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
WARNING: line over 80 characters
#5471: FILE: target/i386/hvf-utils/x86_emu.c:507:
+ hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 0, decode->operand_size, 1);
ERROR: braces {} are necessary for all arms of this statement
#5479: FILE: target/i386/hvf-utils/x86_emu.c:515:
+ if (decode->rep)
[...]
+ else
[...]
WARNING: line over 80 characters
#5492: FILE: target/i386/hvf-utils/x86_emu.c:528:
+ hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 1, decode->operand_size, 1);
ERROR: braces {} are necessary for all arms of this statement
#5499: FILE: target/i386/hvf-utils/x86_emu.c:535:
+ if (decode->rep)
[...]
+ else
[...]
ERROR: trailing whitespace
#5503: FILE: target/i386/hvf-utils/x86_emu.c:539:
+ $
ERROR: trailing whitespace
#5512: FILE: target/i386/hvf-utils/x86_emu.c:548:
+ $
WARNING: line over 80 characters
#5514: FILE: target/i386/hvf-utils/x86_emu.c:550:
+ dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
ERROR: trailing whitespace
#5515: FILE: target/i386/hvf-utils/x86_emu.c:551:
+ $
ERROR: braces {} are necessary for all arms of this statement
#5525: FILE: target/i386/hvf-utils/x86_emu.c:561:
+ if (decode->rep) {
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#5528: FILE: target/i386/hvf-utils/x86_emu.c:564:
+ }
+ else
WARNING: line over 80 characters
#5540: FILE: target/i386/hvf-utils/x86_emu.c:576:
+ dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
ERROR: braces {} are necessary for all arms of this statement
#5555: FILE: target/i386/hvf-utils/x86_emu.c:591:
+ if (decode->rep) {
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#5558: FILE: target/i386/hvf-utils/x86_emu.c:594:
+ }
+ else
ERROR: braces {} are necessary for all arms of this statement
#5579: FILE: target/i386/hvf-utils/x86_emu.c:615:
+ if (decode->rep) {
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#5582: FILE: target/i386/hvf-utils/x86_emu.c:618:
+ }
+ else
ERROR: trailing whitespace
#5591: FILE: target/i386/hvf-utils/x86_emu.c:627:
+ $
ERROR: braces {} are necessary for all arms of this statement
#5604: FILE: target/i386/hvf-utils/x86_emu.c:640:
+ if (decode->rep) {
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#5607: FILE: target/i386/hvf-utils/x86_emu.c:643:
+ }
+ else
ERROR: trailing whitespace
#5617: FILE: target/i386/hvf-utils/x86_emu.c:653:
+ $
ERROR: braces {} are necessary for all arms of this statement
#5627: FILE: target/i386/hvf-utils/x86_emu.c:663:
+ if (decode->rep) {
[...]
+ else
[...]
ERROR: else should follow close brace '}'
#5630: FILE: target/i386/hvf-utils/x86_emu.c:666:
+ }
+ else
ERROR: code indent should never use tabs
#5636: FILE: target/i386/hvf-utils/x86_emu.c:672:
+#define MSR_IA32_UCODE_REV ^I^I0x00000017$
ERROR: switch and case should be at the same indent
#5645: FILE: target/i386/hvf-utils/x86_emu.c:681:
+ switch (msr) {
+ case MSR_IA32_TSC:
[...]
+ case MSR_IA32_APICBASE:
[...]
+ case MSR_IA32_UCODE_REV:
[...]
+ case MSR_EFER:
[...]
+ case MSR_FSBASE:
[...]
+ case MSR_GSBASE:
[...]
+ case MSR_KERNELGSBASE:
[...]
+ case MSR_STAR:
[...]
+ case MSR_LSTAR:
[...]
+ case MSR_CSTAR:
[...]
+ case MSR_IA32_MISC_ENABLE:
[...]
+ case MSR_MTRRphysBase(0):
+ case MSR_MTRRphysBase(1):
+ case MSR_MTRRphysBase(2):
+ case MSR_MTRRphysBase(3):
+ case MSR_MTRRphysBase(4):
+ case MSR_MTRRphysBase(5):
+ case MSR_MTRRphysBase(6):
+ case MSR_MTRRphysBase(7):
[...]
+ case MSR_MTRRphysMask(0):
+ case MSR_MTRRphysMask(1):
+ case MSR_MTRRphysMask(2):
+ case MSR_MTRRphysMask(3):
+ case MSR_MTRRphysMask(4):
+ case MSR_MTRRphysMask(5):
+ case MSR_MTRRphysMask(6):
+ case MSR_MTRRphysMask(7):
[...]
+ case MSR_MTRRfix64K_00000:
[...]
+ case MSR_MTRRfix16K_80000:
+ case MSR_MTRRfix16K_A0000:
[...]
+ case MSR_MTRRfix4K_C0000:
+ case MSR_MTRRfix4K_C8000:
+ case MSR_MTRRfix4K_D0000:
+ case MSR_MTRRfix4K_D8000:
+ case MSR_MTRRfix4K_E0000:
+ case MSR_MTRRfix4K_E8000:
+ case MSR_MTRRfix4K_F0000:
+ case MSR_MTRRfix4K_F8000:
[...]
+ case MSR_MTRRdefType:
[...]
+ default:
ERROR: do not use C99 // comments
#5720: FILE: target/i386/hvf-utils/x86_emu.c:756:
+ // fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr);
ERROR: switch and case should be at the same indent
#5742: FILE: target/i386/hvf-utils/x86_emu.c:778:
+ switch (msr) {
+ case MSR_IA32_TSC:
[...]
+ case MSR_IA32_APICBASE:
[...]
+ case MSR_FSBASE:
[...]
+ case MSR_GSBASE:
[...]
+ case MSR_KERNELGSBASE:
[...]
+ case MSR_STAR:
[...]
+ case MSR_LSTAR:
[...]
+ case MSR_CSTAR:
[...]
+ case MSR_EFER:
[...]
+ case MSR_MTRRphysBase(0):
+ case MSR_MTRRphysBase(1):
+ case MSR_MTRRphysBase(2):
+ case MSR_MTRRphysBase(3):
+ case MSR_MTRRphysBase(4):
+ case MSR_MTRRphysBase(5):
+ case MSR_MTRRphysBase(6):
+ case MSR_MTRRphysBase(7):
[...]
+ case MSR_MTRRphysMask(0):
+ case MSR_MTRRphysMask(1):
+ case MSR_MTRRphysMask(2):
+ case MSR_MTRRphysMask(3):
+ case MSR_MTRRphysMask(4):
+ case MSR_MTRRphysMask(5):
+ case MSR_MTRRphysMask(6):
+ case MSR_MTRRphysMask(7):
[...]
+ case MSR_MTRRfix64K_00000:
[...]
+ case MSR_MTRRfix16K_80000:
+ case MSR_MTRRfix16K_A0000:
[...]
+ case MSR_MTRRfix4K_C0000:
+ case MSR_MTRRfix4K_C8000:
+ case MSR_MTRRfix4K_D0000:
+ case MSR_MTRRfix4K_D8000:
+ case MSR_MTRRfix4K_E0000:
+ case MSR_MTRRfix4K_E8000:
+ case MSR_MTRRfix4K_F0000:
+ case MSR_MTRRfix4K_F8000:
[...]
+ case MSR_MTRRdefType:
[...]
+ default:
ERROR: do not use C99 // comments
#5744: FILE: target/i386/hvf-utils/x86_emu.c:780:
+ // if (!osx_is_sierra())
ERROR: do not use C99 // comments
#5745: FILE: target/i386/hvf-utils/x86_emu.c:781:
+ // wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp());
ERROR: do not use C99 // comments
#5746: FILE: target/i386/hvf-utils/x86_emu.c:782:
+ //hv_vm_sync_tsc(data);
ERROR: do not use C99 // comments
#5771: FILE: target/i386/hvf-utils/x86_emu.c:807:
+ //printf("new efer %llx\n", EFER(cpu));
ERROR: braces {} are necessary for all arms of this statement
#5773: FILE: target/i386/hvf-utils/x86_emu.c:809:
+ if (data & EFER_NXE)
[...]
ERROR: do not use C99 // comments
#5821: FILE: target/i386/hvf-utils/x86_emu.c:857:
+ // if (g_hypervisor_iface)
ERROR: do not use C99 // comments
#5822: FILE: target/i386/hvf-utils/x86_emu.c:858:
+ // g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
ERROR: do not use C99 // comments
#5824: FILE: target/i386/hvf-utils/x86_emu.c:860:
+ //printf("write msr %llx\n", RCX(cpu));
WARNING: line over 80 characters
#5860: FILE: target/i386/hvf-utils/x86_emu.c:896:
+ decode->op[0].val = read_val_ext(cpu, decode->op[0].ptr, decode->operand_size);
ERROR: switch and case should be at the same indent
#5863: FILE: target/i386/hvf-utils/x86_emu.c:899:
+ switch (flag) {
+ case 0:
[...]
+ case 1:
[...]
+ case 2:
[...]
+ case 3:
WARNING: line over 80 characters
#5877: FILE: target/i386/hvf-utils/x86_emu.c:913:
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[0].val, decode->operand_size);
ERROR: do not use C99 // comments
#5913: FILE: target/i386/hvf-utils/x86_emu.c:949:
+ count &= 0x1f; // count is masked to 5 bits
ERROR: braces {} are necessary for all arms of this statement
#5914: FILE: target/i386/hvf-utils/x86_emu.c:950:
+ if (!count)
[...]
ERROR: switch and case should be at the same indent
#5917: FILE: target/i386/hvf-utils/x86_emu.c:953:
+ switch (decode->operand_size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
[...]
+ default:
ERROR: do not use C99 // comments
#5940: FILE: target/i386/hvf-utils/x86_emu.c:976:
+ of = cf ^ (res >> 15); // of = cf ^ result15
ERROR: trailing whitespace
#5951: FILE: target/i386/hvf-utils/x86_emu.c:987:
+ $
ERROR: do not use C99 // comments
#5955: FILE: target/i386/hvf-utils/x86_emu.c:991:
+ of = cf ^ (res >> 31); // of = cf ^ result31
ERROR: do not use C99 // comments
#5964: FILE: target/i386/hvf-utils/x86_emu.c:1000:
+ //lflags_to_rflags(cpu);
ERROR: braces {} are necessary for all arms of this statement
#5975: FILE: target/i386/hvf-utils/x86_emu.c:1011:
+ if (0xbe == decode->opcode[1])
[...]
+ else
[...]
ERROR: line over 90 characters
#5982: FILE: target/i386/hvf-utils/x86_emu.c:1018:
+ decode->op[1].val = sign(read_val_ext(cpu, decode->op[1].ptr, src_op_size), src_op_size);
ERROR: switch and case should be at the same indent
#5996: FILE: target/i386/hvf-utils/x86_emu.c:1032:
+ switch (decode->operand_size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
ERROR: line over 90 characters
#6010: FILE: target/i386/hvf-utils/x86_emu.c:1046:
+ res = ((uint8_t)decode->op[0].val >> count) | ((uint8_t)decode->op[0].val << (8 - count));
ERROR: do not use C99 // comments
#6028: FILE: target/i386/hvf-utils/x86_emu.c:1064:
+ // of = result14 ^ result15
ERROR: do not use C99 // comments
#6032: FILE: target/i386/hvf-utils/x86_emu.c:1068:
+ count &= 0x0f; // use only 4 LSB's
ERROR: line over 90 characters
#6033: FILE: target/i386/hvf-utils/x86_emu.c:1069:
+ res = ((uint16_t)decode->op[0].val >> count) | ((uint16_t)decode->op[0].val << (16 - count));
ERROR: do not use C99 // comments
#6038: FILE: target/i386/hvf-utils/x86_emu.c:1074:
+ // of = result14 ^ result15
ERROR: line over 90 characters
#6050: FILE: target/i386/hvf-utils/x86_emu.c:1086:
+ res = ((uint32_t)decode->op[0].val >> count) | ((uint32_t)decode->op[0].val << (32 - count));
ERROR: do not use C99 // comments
#6055: FILE: target/i386/hvf-utils/x86_emu.c:1091:
+ // of = result30 ^ result31
ERROR: switch and case should be at the same indent
#6071: FILE: target/i386/hvf-utils/x86_emu.c:1107:
+ switch (decode->operand_size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
ERROR: do not use C99 // comments
#6084: FILE: target/i386/hvf-utils/x86_emu.c:1120:
+ count &= 0x7; // use only lowest 3 bits
ERROR: line over 90 characters
#6085: FILE: target/i386/hvf-utils/x86_emu.c:1121:
+ res = ((uint8_t)decode->op[0].val << count) | ((uint8_t)decode->op[0].val >> (8 - count));
ERROR: do not use C99 // comments
#6106: FILE: target/i386/hvf-utils/x86_emu.c:1142:
+ // of = cf ^ result15
ERROR: do not use C99 // comments
#6110: FILE: target/i386/hvf-utils/x86_emu.c:1146:
+ count &= 0x0f; // only use bottom 4 bits
ERROR: line over 90 characters
#6111: FILE: target/i386/hvf-utils/x86_emu.c:1147:
+ res = ((uint16_t)decode->op[0].val << count) | ((uint16_t)decode->op[0].val >> (16 - count));
ERROR: do not use C99 // comments
#6116: FILE: target/i386/hvf-utils/x86_emu.c:1152:
+ // of = cf ^ result15
ERROR: line over 90 characters
#6128: FILE: target/i386/hvf-utils/x86_emu.c:1164:
+ res = ((uint32_t)decode->op[0].val << count) | ((uint32_t)decode->op[0].val >> (32 - count));
ERROR: do not use C99 // comments
#6133: FILE: target/i386/hvf-utils/x86_emu.c:1169:
+ // of = cf ^ result31
ERROR: switch and case should be at the same indent
#6151: FILE: target/i386/hvf-utils/x86_emu.c:1187:
+ switch(decode->operand_size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
ERROR: space required before the open parenthesis '('
#6151: FILE: target/i386/hvf-utils/x86_emu.c:1187:
+ switch(decode->operand_size) {
ERROR: braces {} are necessary for all arms of this statement
#6157: FILE: target/i386/hvf-utils/x86_emu.c:1193:
+ if (!count)
[...]
ERROR: braces {} are necessary for all arms of this statement
#6160: FILE: target/i386/hvf-utils/x86_emu.c:1196:
+ if (1 == count)
[...]
+ else
[...]
ERROR: line over 90 characters
#6163: FILE: target/i386/hvf-utils/x86_emu.c:1199:
+ res = (op1_8 << count) | (get_CF(cpu) << (count - 1)) | (op1_8 >> (9 - count));
ERROR: do not use C99 // comments
#6168: FILE: target/i386/hvf-utils/x86_emu.c:1204:
+ of = cf ^ (res >> 7); // of = cf ^ result7
ERROR: braces {} are necessary for all arms of this statement
#6178: FILE: target/i386/hvf-utils/x86_emu.c:1214:
+ if (!count)
[...]
ERROR: braces {} are necessary for all arms of this statement
#6181: FILE: target/i386/hvf-utils/x86_emu.c:1217:
+ if (1 == count)
[...]
+ else if (count == 16)
[...]
+ else // 2..15
[...]
ERROR: braces {} are necessary for all arms of this statement
#6183: FILE: target/i386/hvf-utils/x86_emu.c:1219:
+ else if (count == 16)
[...]
+ else // 2..15
[...]
ERROR: do not use C99 // comments
#6185: FILE: target/i386/hvf-utils/x86_emu.c:1221:
+ else // 2..15
ERROR: line over 90 characters
#6186: FILE: target/i386/hvf-utils/x86_emu.c:1222:
+ res = (op1_16 << count) | (get_CF(cpu) << (count - 1)) | (op1_16 >> (17 - count));
ERROR: trailing whitespace
#6187: FILE: target/i386/hvf-utils/x86_emu.c:1223:
+ $
ERROR: trailing whitespace
#6189: FILE: target/i386/hvf-utils/x86_emu.c:1225:
+ $
ERROR: do not use C99 // comments
#6191: FILE: target/i386/hvf-utils/x86_emu.c:1227:
+ of = cf ^ (res >> 15); // of = cf ^ result15
ERROR: braces {} are necessary for all arms of this statement
#6200: FILE: target/i386/hvf-utils/x86_emu.c:1236:
+ if (!count)
[...]
ERROR: braces {} are necessary for all arms of this statement
#6203: FILE: target/i386/hvf-utils/x86_emu.c:1239:
+ if (1 == count)
[...]
+ else
[...]
ERROR: line over 90 characters
#6206: FILE: target/i386/hvf-utils/x86_emu.c:1242:
+ res = (op1_32 << count) | (get_CF(cpu) << (count - 1)) | (op1_32 >> (33 - count));
ERROR: do not use C99 // comments
#6211: FILE: target/i386/hvf-utils/x86_emu.c:1247:
+ of = cf ^ (res >> 31); // of = cf ^ result31
ERROR: switch and case should be at the same indent
#6227: FILE: target/i386/hvf-utils/x86_emu.c:1263:
+ switch(decode->operand_size) {
+ case 1:
[...]
+ case 2:
[...]
+ case 4:
ERROR: space required before the open parenthesis '('
#6227: FILE: target/i386/hvf-utils/x86_emu.c:1263:
+ switch(decode->operand_size) {
ERROR: braces {} are necessary for all arms of this statement
#6234: FILE: target/i386/hvf-utils/x86_emu.c:1270:
+ if (!count)
[...]
ERROR: line over 90 characters
#6236: FILE: target/i386/hvf-utils/x86_emu.c:1272:
+ res = (op1_8 >> count) | (get_CF(cpu) << (8 - count)) | (op1_8 << (9 - count));
ERROR: do not use C99 // comments
#6241: FILE: target/i386/hvf-utils/x86_emu.c:1277:
+ of = (((res << 1) ^ res) >> 7) & 0x1; // of = result6 ^ result7
ERROR: braces {} are necessary for all arms of this statement
#6251: FILE: target/i386/hvf-utils/x86_emu.c:1287:
+ if (!count)
[...]
ERROR: line over 90 characters
#6253: FILE: target/i386/hvf-utils/x86_emu.c:1289:
+ res = (op1_16 >> count) | (get_CF(cpu) << (16 - count)) | (op1_16 << (17 - count));
WARNING: line over 80 characters
#6258: FILE: target/i386/hvf-utils/x86_emu.c:1294:
+ of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; // of = result15 ^ result14
ERROR: do not use C99 // comments
#6258: FILE: target/i386/hvf-utils/x86_emu.c:1294:
+ of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; // of = result15 ^ result14
ERROR: braces {} are necessary for all arms of this statement
#6267: FILE: target/i386/hvf-utils/x86_emu.c:1303:
+ if (!count)
[...]
ERROR: trailing whitespace
#6269: FILE: target/i386/hvf-utils/x86_emu.c:1305:
+ $
ERROR: braces {} are necessary for all arms of this statement
#6270: FILE: target/i386/hvf-utils/x86_emu.c:1306:
+ if (1 == count)
[...]
+ else
[...]
ERROR: line over 90 characters
#6273: FILE: target/i386/hvf-utils/x86_emu.c:1309:
+ res = (op1_32 >> count) | (get_CF(cpu) << (32 - count)) | (op1_32 << (33 - count));
ERROR: do not use C99 // comments
#6278: FILE: target/i386/hvf-utils/x86_emu.c:1314:
+ of = ((res << 1) ^ res) >> 31; // of = result30 ^ result31
WARNING: line over 80 characters
#6290: FILE: target/i386/hvf-utils/x86_emu.c:1326:
+ write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
WARNING: line over 80 characters
#6291: FILE: target/i386/hvf-utils/x86_emu.c:1327:
+ write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
WARNING: line over 80 characters
#6299: FILE: target/i386/hvf-utils/x86_emu.c:1335:
+ write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
ERROR: braces {} are necessary even for single statement blocks
#6355: FILE: target/i386/hvf-utils/x86_emu.c:1391:
+ for (i = 0; i < ARRAY_SIZE(handlers); i++)
+ _cmd_handler[handlers[i].cmd] = handlers[i];
ERROR: line over 90 characters
#6361: FILE: target/i386/hvf-utils/x86_emu.c:1397:
+ printf("%llx: eax %llx ebx %llx ecx %llx edx %llx esi %llx edi %llx ebp %llx esp %llx flags %llx\n", RIP(cpu), RAX(cpu), RBX(cpu), RCX(cpu), RDX(cpu), RSI(cpu), RDI(cpu), RBP(cpu), RSP(cpu), EFLAGS(cpu));
ERROR: braces {} are necessary even for single statement blocks
#6375: FILE: target/i386/hvf-utils/x86_emu.c:1411:
+ for (i = 8; i < 16; i++)
+ RRX(cpu, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
ERROR: trailing whitespace
#6377: FILE: target/i386/hvf-utils/x86_emu.c:1413:
+ $
ERROR: do not use C99 // comments
#6382: FILE: target/i386/hvf-utils/x86_emu.c:1418:
+ //print_debug(cpu);
ERROR: braces {} are necessary even for single statement blocks
#6396: FILE: target/i386/hvf-utils/x86_emu.c:1432:
+ for (i = 8; i < 16; i++)
+ wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(cpu, i));
ERROR: trailing whitespace
#6398: FILE: target/i386/hvf-utils/x86_emu.c:1434:
+ $
ERROR: do not use C99 // comments
#6403: FILE: target/i386/hvf-utils/x86_emu.c:1439:
+ //print_debug(cpu);
ERROR: do not use C99 // comments
#6408: FILE: target/i386/hvf-utils/x86_emu.c:1444:
+ //if (hvf_vcpu_id(cpu))
ERROR: line over 90 characters
#6409: FILE: target/i386/hvf-utils/x86_emu.c:1445:
+ //printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu), decode_cmd_to_string(ins->cmd));
ERROR: do not use C99 // comments
#6409: FILE: target/i386/hvf-utils/x86_emu.c:1445:
+ //printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu), decode_cmd_to_string(ins->cmd));
ERROR: trailing whitespace
#6410: FILE: target/i386/hvf-utils/x86_emu.c:1446:
+ $
ERROR: line over 90 characters
#6415: FILE: target/i386/hvf-utils/x86_emu.c:1451:
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0],
ERROR: unnecessary whitespace before a quoted newline
#6415: FILE: target/i386/hvf-utils/x86_emu.c:1451:
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0],
ERROR: trailing whitespace
#6420: FILE: target/i386/hvf-utils/x86_emu.c:1456:
+ $
ERROR: line over 90 characters
#6421: FILE: target/i386/hvf-utils/x86_emu.c:1457:
+ VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler, "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0);
ERROR: unnecessary whitespace before a quoted newline
#6421: FILE: target/i386/hvf-utils/x86_emu.c:1457:
+ VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler, "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0);
WARNING: architecture specific defines should be avoided
#6437: FILE: target/i386/hvf-utils/x86_emu.h:1:
+#ifndef __X86_EMU_H__
ERROR: do not use C99 // comments
#6459: FILE: target/i386/hvf-utils/x86_flags.c:1:
+/////////////////////////////////////////////////////////////////////////
ERROR: do not use C99 // comments
#6460: FILE: target/i386/hvf-utils/x86_flags.c:2:
+//
ERROR: do not use C99 // comments
#6461: FILE: target/i386/hvf-utils/x86_flags.c:3:
+// Copyright (C) 2001-2012 The Bochs Project
ERROR: do not use C99 // comments
#6462: FILE: target/i386/hvf-utils/x86_flags.c:4:
+// Copyright (C) 2017 Google Inc.
ERROR: do not use C99 // comments
#6463: FILE: target/i386/hvf-utils/x86_flags.c:5:
+//
ERROR: do not use C99 // comments
#6464: FILE: target/i386/hvf-utils/x86_flags.c:6:
+// This library is free software; you can redistribute it and/or
ERROR: do not use C99 // comments
#6465: FILE: target/i386/hvf-utils/x86_flags.c:7:
+// modify it under the terms of the GNU Lesser General Public
ERROR: do not use C99 // comments
#6466: FILE: target/i386/hvf-utils/x86_flags.c:8:
+// License as published by the Free Software Foundation; either
ERROR: do not use C99 // comments
#6467: FILE: target/i386/hvf-utils/x86_flags.c:9:
+// version 2 of the License, or (at your option) any later version.
ERROR: do not use C99 // comments
#6468: FILE: target/i386/hvf-utils/x86_flags.c:10:
+//
ERROR: do not use C99 // comments
#6469: FILE: target/i386/hvf-utils/x86_flags.c:11:
+// This library is distributed in the hope that it will be useful,
ERROR: do not use C99 // comments
#6470: FILE: target/i386/hvf-utils/x86_flags.c:12:
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
ERROR: do not use C99 // comments
#6471: FILE: target/i386/hvf-utils/x86_flags.c:13:
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
ERROR: do not use C99 // comments
#6472: FILE: target/i386/hvf-utils/x86_flags.c:14:
+// Lesser General Public License for more details.
ERROR: do not use C99 // comments
#6473: FILE: target/i386/hvf-utils/x86_flags.c:15:
+//
ERROR: do not use C99 // comments
#6474: FILE: target/i386/hvf-utils/x86_flags.c:16:
+// You should have received a copy of the GNU Lesser General Public
ERROR: do not use C99 // comments
#6475: FILE: target/i386/hvf-utils/x86_flags.c:17:
+// License along with this library; if not, write to the Free Software
ERROR: do not use C99 // comments
#6476: FILE: target/i386/hvf-utils/x86_flags.c:18:
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
ERROR: do not use C99 // comments
#6477: FILE: target/i386/hvf-utils/x86_flags.c:19:
+/////////////////////////////////////////////////////////////////////////
WARNING: line over 80 characters
#6493: FILE: target/i386/hvf-utils/x86_flags.c:35:
+ cpu->hvf_x86->lflags.auxbits |= (temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF);
WARNING: line over 80 characters
#6496: FILE: target/i386/hvf-utils/x86_flags.c:38:
+void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
WARNING: line over 80 characters
#6501: FILE: target/i386/hvf-utils/x86_flags.c:43:
+void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
WARNING: line over 80 characters
#6506: FILE: target/i386/hvf-utils/x86_flags.c:48:
+void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
WARNING: line over 80 characters
#6511: FILE: target/i386/hvf-utils/x86_flags.c:53:
+void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
WARNING: line over 80 characters
#6516: FILE: target/i386/hvf-utils/x86_flags.c:58:
+void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
WARNING: line over 80 characters
#6521: FILE: target/i386/hvf-utils/x86_flags.c:63:
+void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
WARNING: line over 80 characters
#6526: FILE: target/i386/hvf-utils/x86_flags.c:68:
+void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
WARNING: line over 80 characters
#6531: FILE: target/i386/hvf-utils/x86_flags.c:73:
+void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
WARNING: line over 80 characters
#6536: FILE: target/i386/hvf-utils/x86_flags.c:78:
+void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
WARNING: line over 80 characters
#6541: FILE: target/i386/hvf-utils/x86_flags.c:83:
+void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
WARNING: line over 80 characters
#6546: FILE: target/i386/hvf-utils/x86_flags.c:88:
+void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
WARNING: line over 80 characters
#6551: FILE: target/i386/hvf-utils/x86_flags.c:93:
+void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
WARNING: line over 80 characters
#6678: FILE: target/i386/hvf-utils/x86_flags.c:220:
+ return ((cpu->hvf_x86->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
ERROR: braces {} are necessary for all arms of this statement
#6724: FILE: target/i386/hvf-utils/x86_flags.c:266:
+ if (val) {
[...]
+ } else
[...]
ERROR: line over 90 characters
#6725: FILE: target/i386/hvf-utils/x86_flags.c:267:
+ cpu->hvf_x86->lflags.auxbits ^= (((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
ERROR: do not use C99 // comments
#6726: FILE: target/i386/hvf-utils/x86_flags.c:268:
+ // merge the parity bits into the Parity Delta Byte
ERROR: do not use C99 // comments
#6729: FILE: target/i386/hvf-utils/x86_flags.c:271:
+ // now zero the .result value
ERROR: line over 90 characters
#6737: FILE: target/i386/hvf-utils/x86_flags.c:279:
+ return ((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) ^ (cpu->hvf_x86->lflags.auxbits >> LF_BIT_SD)) & 1;
ERROR: do not use C99 // comments
#6782: FILE: target/i386/hvf-utils/x86_flags.h:1:
+/////////////////////////////////////////////////////////////////////////
ERROR: do not use C99 // comments
#6783: FILE: target/i386/hvf-utils/x86_flags.h:2:
+//
ERROR: do not use C99 // comments
#6784: FILE: target/i386/hvf-utils/x86_flags.h:3:
+// Copyright (C) 2001-2012 The Bochs Project
ERROR: do not use C99 // comments
#6785: FILE: target/i386/hvf-utils/x86_flags.h:4:
+// Copyright (C) 2017 Google Inc.
ERROR: do not use C99 // comments
#6786: FILE: target/i386/hvf-utils/x86_flags.h:5:
+//
ERROR: do not use C99 // comments
#6787: FILE: target/i386/hvf-utils/x86_flags.h:6:
+// This library is free software; you can redistribute it and/or
ERROR: do not use C99 // comments
#6788: FILE: target/i386/hvf-utils/x86_flags.h:7:
+// modify it under the terms of the GNU Lesser General Public
ERROR: do not use C99 // comments
#6789: FILE: target/i386/hvf-utils/x86_flags.h:8:
+// License as published by the Free Software Foundation; either
ERROR: do not use C99 // comments
#6790: FILE: target/i386/hvf-utils/x86_flags.h:9:
+// version 2 of the License, or (at your option) any later version.
ERROR: do not use C99 // comments
#6791: FILE: target/i386/hvf-utils/x86_flags.h:10:
+//
ERROR: do not use C99 // comments
#6792: FILE: target/i386/hvf-utils/x86_flags.h:11:
+// This library is distributed in the hope that it will be useful,
ERROR: do not use C99 // comments
#6793: FILE: target/i386/hvf-utils/x86_flags.h:12:
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
ERROR: do not use C99 // comments
#6794: FILE: target/i386/hvf-utils/x86_flags.h:13:
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
ERROR: do not use C99 // comments
#6795: FILE: target/i386/hvf-utils/x86_flags.h:14:
+// Lesser General Public License for more details.
ERROR: do not use C99 // comments
#6796: FILE: target/i386/hvf-utils/x86_flags.h:15:
+//
ERROR: do not use C99 // comments
#6797: FILE: target/i386/hvf-utils/x86_flags.h:16:
+// You should have received a copy of the GNU Lesser General Public
ERROR: do not use C99 // comments
#6798: FILE: target/i386/hvf-utils/x86_flags.h:17:
+// License along with this library; if not, write to the Free Software
ERROR: do not use C99 // comments
#6799: FILE: target/i386/hvf-utils/x86_flags.h:18:
+// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
ERROR: do not use C99 // comments
#6800: FILE: target/i386/hvf-utils/x86_flags.h:19:
+/////////////////////////////////////////////////////////////////////////
WARNING: architecture specific defines should be avoided
#6804: FILE: target/i386/hvf-utils/x86_flags.h:23:
+#ifndef __X86_FLAGS_H__
ERROR: do not use C99 // comments
#6839: FILE: target/i386/hvf-utils/x86_flags.h:58:
+// *******************
ERROR: do not use C99 // comments
#6840: FILE: target/i386/hvf-utils/x86_flags.h:59:
+// OSZAPC
ERROR: do not use C99 // comments
#6841: FILE: target/i386/hvf-utils/x86_flags.h:60:
+// *******************
ERROR: trailing statements should be on next line
#6848: FILE: target/i386/hvf-utils/x86_flags.h:67:
+ if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
ERROR: braces {} are necessary for all arms of this statement
#6848: FILE: target/i386/hvf-utils/x86_flags.h:67:
+ if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
[...]
WARNING: line over 80 characters
#6849: FILE: target/i386/hvf-utils/x86_flags.h:68:
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
ERROR: trailing statements should be on next line
#6849: FILE: target/i386/hvf-utils/x86_flags.h:68:
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
ERROR: braces {} are necessary for all arms of this statement
#6849: FILE: target/i386/hvf-utils/x86_flags.h:68:
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
[...]
WARNING: line over 80 characters
#6850: FILE: target/i386/hvf-utils/x86_flags.h:69:
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
ERROR: trailing statements should be on next line
#6850: FILE: target/i386/hvf-utils/x86_flags.h:69:
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
ERROR: braces {} are necessary for all arms of this statement
#6850: FILE: target/i386/hvf-utils/x86_flags.h:69:
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
[...]
WARNING: line over 80 characters
#6851: FILE: target/i386/hvf-utils/x86_flags.h:70:
+ else VM_PANIC("unimplemented"); \
ERROR: trailing statements should be on next line
#6851: FILE: target/i386/hvf-utils/x86_flags.h:70:
+ else VM_PANIC("unimplemented"); \
ERROR: braces {} are necessary even for single statement blocks
#6851: FILE: target/i386/hvf-utils/x86_flags.h:70:
+ else VM_PANIC("unimplemented"); \
ERROR: space required after that ';' (ctx:VxV)
#6871: FILE: target/i386/hvf-utils/x86_flags.h:90:
+ if (32 == size) {SET_FLAGS_OSZAPC_LOGIC_32(result);} \
^
ERROR: trailing statements should be on next line
#6871: FILE: target/i386/hvf-utils/x86_flags.h:90:
+ if (32 == size) {SET_FLAGS_OSZAPC_LOGIC_32(result);} \
ERROR: space required after that ';' (ctx:VxV)
#6872: FILE: target/i386/hvf-utils/x86_flags.h:91:
+ else if (16 == size) {SET_FLAGS_OSZAPC_LOGIC_16(result);} \
^
ERROR: trailing statements should be on next line
#6872: FILE: target/i386/hvf-utils/x86_flags.h:91:
+ else if (16 == size) {SET_FLAGS_OSZAPC_LOGIC_16(result);} \
ERROR: space required after that ';' (ctx:VxV)
#6873: FILE: target/i386/hvf-utils/x86_flags.h:92:
+ else if (8 == size) {SET_FLAGS_OSZAPC_LOGIC_8(result);} \
^
ERROR: trailing statements should be on next line
#6873: FILE: target/i386/hvf-utils/x86_flags.h:92:
+ else if (8 == size) {SET_FLAGS_OSZAPC_LOGIC_8(result);} \
ERROR: trailing statements should be on next line
#6874: FILE: target/i386/hvf-utils/x86_flags.h:93:
+ else VM_PANIC("unimplemented"); \
ERROR: braces {} are necessary even for single statement blocks
#6874: FILE: target/i386/hvf-utils/x86_flags.h:93:
+ else VM_PANIC("unimplemented"); \
ERROR: do not use C99 // comments
#6893: FILE: target/i386/hvf-utils/x86_flags.h:112:
+// *******************
ERROR: do not use C99 // comments
#6894: FILE: target/i386/hvf-utils/x86_flags.h:113:
+// OSZAP
ERROR: do not use C99 // comments
#6895: FILE: target/i386/hvf-utils/x86_flags.h:114:
+// *******************
ERROR: trailing statements should be on next line
#6900: FILE: target/i386/hvf-utils/x86_flags.h:119:
+ if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
ERROR: braces {} are necessary for all arms of this statement
#6900: FILE: target/i386/hvf-utils/x86_flags.h:119:
+ if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
[...]
WARNING: line over 80 characters
#6901: FILE: target/i386/hvf-utils/x86_flags.h:120:
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
ERROR: trailing statements should be on next line
#6901: FILE: target/i386/hvf-utils/x86_flags.h:120:
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
ERROR: braces {} are necessary for all arms of this statement
#6901: FILE: target/i386/hvf-utils/x86_flags.h:120:
+ else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
[...]
WARNING: line over 80 characters
#6902: FILE: target/i386/hvf-utils/x86_flags.h:121:
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
ERROR: trailing statements should be on next line
#6902: FILE: target/i386/hvf-utils/x86_flags.h:121:
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
ERROR: braces {} are necessary for all arms of this statement
#6902: FILE: target/i386/hvf-utils/x86_flags.h:121:
+ else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
[...]
WARNING: line over 80 characters
#6903: FILE: target/i386/hvf-utils/x86_flags.h:122:
+ else VM_PANIC("unimplemented"); \
ERROR: trailing statements should be on next line
#6903: FILE: target/i386/hvf-utils/x86_flags.h:122:
+ else VM_PANIC("unimplemented"); \
ERROR: braces {} are necessary even for single statement blocks
#6903: FILE: target/i386/hvf-utils/x86_flags.h:122:
+ else VM_PANIC("unimplemented"); \
ERROR: do not use C99 // comments
#6934: FILE: target/i386/hvf-utils/x86_flags.h:153:
+// *******************
ERROR: do not use C99 // comments
#6935: FILE: target/i386/hvf-utils/x86_flags.h:154:
+// OSZAxC
ERROR: do not use C99 // comments
#6936: FILE: target/i386/hvf-utils/x86_flags.h:155:
+// *******************
ERROR: line over 90 characters
#6967: FILE: target/i386/hvf-utils/x86_flags.h:186:
+void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
ERROR: line over 90 characters
#6968: FILE: target/i386/hvf-utils/x86_flags.h:187:
+void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
WARNING: line over 80 characters
#6969: FILE: target/i386/hvf-utils/x86_flags.h:188:
+void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
ERROR: line over 90 characters
#6971: FILE: target/i386/hvf-utils/x86_flags.h:190:
+void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
ERROR: line over 90 characters
#6972: FILE: target/i386/hvf-utils/x86_flags.h:191:
+void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
WARNING: line over 80 characters
#6973: FILE: target/i386/hvf-utils/x86_flags.h:192:
+void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
WARNING: line over 80 characters
#6975: FILE: target/i386/hvf-utils/x86_flags.h:194:
+void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
WARNING: line over 80 characters
#6976: FILE: target/i386/hvf-utils/x86_flags.h:195:
+void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
WARNING: line over 80 characters
#6977: FILE: target/i386/hvf-utils/x86_flags.h:196:
+void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
WARNING: line over 80 characters
#6979: FILE: target/i386/hvf-utils/x86_flags.h:198:
+void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
WARNING: line over 80 characters
#6980: FILE: target/i386/hvf-utils/x86_flags.h:199:
+void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
WARNING: line over 80 characters
#6981: FILE: target/i386/hvf-utils/x86_flags.h:200:
+void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
WARNING: architecture specific defines should be avoided
#7006: FILE: target/i386/hvf-utils/x86_gen.h:1:
+#ifndef __X86_GEN_H__
ERROR: braces {} are necessary for all arms of this statement
#7104: FILE: target/i386/hvf-utils/x86_mmu.c:57:
+ if (!pae)
[...]
ERROR: braces {} are necessary for all arms of this statement
#7106: FILE: target/i386/hvf-utils/x86_mmu.c:59:
+ if (x86_is_long_mode(cpu))
[...]
WARNING: line over 80 characters
#7115: FILE: target/i386/hvf-utils/x86_mmu.c:68:
+ return (addr >> (level_shift * (level - 1) + 12)) & ((1 << level_shift) - 1);
ERROR: line over 90 characters
#7124: FILE: target/i386/hvf-utils/x86_mmu.c:77:
+static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool pae)
ERROR: braces {} are necessary for all arms of this statement
#7131: FILE: target/i386/hvf-utils/x86_mmu.c:84:
+ if (level == 3 && !x86_is_long_mode(cpu))
[...]
ERROR: line over 90 characters
#7135: FILE: target/i386/hvf-utils/x86_mmu.c:88:
+ address_space_rw(&address_space_memory, gpa + index * pte_size(pae), MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0);
ERROR: line over 90 characters
#7143: FILE: target/i386/hvf-utils/x86_mmu.c:96:
+static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae)
ERROR: trailing whitespace
#7146: FILE: target/i386/hvf-utils/x86_mmu.c:99:
+ $
ERROR: braces {} are necessary for all arms of this statement
#7147: FILE: target/i386/hvf-utils/x86_mmu.c:100:
+ if (pt->write_access)
[...]
ERROR: braces {} are necessary for all arms of this statement
#7149: FILE: target/i386/hvf-utils/x86_mmu.c:102:
+ if (pt->user_access)
[...]
ERROR: braces {} are necessary for all arms of this statement
#7151: FILE: target/i386/hvf-utils/x86_mmu.c:104:
+ if (pt->exec_access)
[...]
ERROR: trailing whitespace
#7158: FILE: target/i386/hvf-utils/x86_mmu.c:111:
+ $
ERROR: braces {} are necessary for all arms of this statement
#7159: FILE: target/i386/hvf-utils/x86_mmu.c:112:
+ if (pae && !x86_is_long_mode(cpu) && 2 == level)
[...]
ERROR: trailing whitespace
#7161: FILE: target/i386/hvf-utils/x86_mmu.c:114:
+ $
ERROR: braces {} are necessary for all arms of this statement
#7166: FILE: target/i386/hvf-utils/x86_mmu.c:119:
+ if (!level)
[...]
ERROR: trailing whitespace
#7168: FILE: target/i386/hvf-utils/x86_mmu.c:121:
+ $
ERROR: trailing whitespace
#7184: FILE: target/i386/hvf-utils/x86_mmu.c:137:
+ $
ERROR: braces {} are necessary for all arms of this statement
#7199: FILE: target/i386/hvf-utils/x86_mmu.c:152:
+ if (pae)
[...]
ERROR: trailing whitespace
#7201: FILE: target/i386/hvf-utils/x86_mmu.c:154:
+ $
ERROR: line over 90 characters
#7208: FILE: target/i386/hvf-utils/x86_mmu.c:161:
+static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code, struct gpt_translation* pt, bool pae)
ERROR: trailing whitespace
#7214: FILE: target/i386/hvf-utils/x86_mmu.c:167:
+ $
ERROR: trailing whitespace
#7223: FILE: target/i386/hvf-utils/x86_mmu.c:176:
+ $
ERROR: braces {} are necessary for all arms of this statement
#7231: FILE: target/i386/hvf-utils/x86_mmu.c:184:
+ if (is_large)
[...]
ERROR: braces {} are necessary for all arms of this statement
#7235: FILE: target/i386/hvf-utils/x86_mmu.c:188:
+ if (!is_large)
[...]
+ else
[...]
ERROR: "foo* bar" should be "foo *bar"
#7264: FILE: target/i386/hvf-utils/x86_mmu.c:217:
+void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes)
ERROR: do not use C99 // comments
#7269: FILE: target/i386/hvf-utils/x86_mmu.c:222:
+ // copy page
WARNING: line over 80 characters
#7273: FILE: target/i386/hvf-utils/x86_mmu.c:226:
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
ERROR: __func__ should be used instead of gcc specific __FUNCTION__
#7273: FILE: target/i386/hvf-utils/x86_mmu.c:226:
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
ERROR: line over 90 characters
#7275: FILE: target/i386/hvf-utils/x86_mmu.c:228:
+ address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 1);
ERROR: "foo* bar" should be "foo *bar"
#7284: FILE: target/i386/hvf-utils/x86_mmu.c:237:
+void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes)
ERROR: do not use C99 // comments
#7289: FILE: target/i386/hvf-utils/x86_mmu.c:242:
+ // copy page
WARNING: line over 80 characters
#7293: FILE: target/i386/hvf-utils/x86_mmu.c:246:
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
ERROR: __func__ should be used instead of gcc specific __FUNCTION__
#7293: FILE: target/i386/hvf-utils/x86_mmu.c:246:
+ VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
ERROR: line over 90 characters
#7295: FILE: target/i386/hvf-utils/x86_mmu.c:248:
+ address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 0);
WARNING: architecture specific defines should be avoided
#7308: FILE: target/i386/hvf-utils/x86_mmu.h:1:
+#ifndef __X86_MMU_H__
ERROR: do not use C99 // comments
#7324: FILE: target/i386/hvf-utils/x86_mmu.h:17:
+// error codes
ERROR: "foo* bar" should be "foo *bar"
#7332: FILE: target/i386/hvf-utils/x86_mmu.h:25:
+void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes);
ERROR: "foo* bar" should be "foo *bar"
#7333: FILE: target/i386/hvf-utils/x86_mmu.h:26:
+void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes);
ERROR: "foo* bar" should be "foo *bar"
#7379: FILE: target/i386/hvf-utils/x86hvf.c:38:
+void hvf_cpu_synchronize_state(struct CPUState* cpu_state);
ERROR: externs should be avoided in .c files
#7379: FILE: target/i386/hvf-utils/x86hvf.c:38:
+void hvf_cpu_synchronize_state(struct CPUState* cpu_state);
ERROR: line over 90 characters
#7381: FILE: target/i386/hvf-utils/x86hvf.c:40:
+void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr)
WARNING: line over 80 characters
#7388: FILE: target/i386/hvf-utils/x86hvf.c:47:
+ // the TR register is usable after processor reset despite having a null selector
ERROR: do not use C99 // comments
#7388: FILE: target/i386/hvf-utils/x86hvf.c:47:
+ // the TR register is usable after processor reset despite having a null selector
ERROR: trailing whitespace
#7422: FILE: target/i386/hvf-utils/x86hvf.c:81:
+ $
ERROR: trailing whitespace
#7424: FILE: target/i386/hvf-utils/x86hvf.c:83:
+ memset(xsave, 0, sizeof(*xsave)); $
ERROR: trailing whitespace
#7425: FILE: target/i386/hvf-utils/x86hvf.c:84:
+ $
ERROR: line over 90 characters
#7426: FILE: target/i386/hvf-utils/x86hvf.c:85:
+ memcpy(&xsave->data[4], &X86_CPU(cpu_state)->env.fpdp, sizeof(X86_CPU(cpu_state)->env.fpdp));
ERROR: line over 90 characters
#7427: FILE: target/i386/hvf-utils/x86hvf.c:86:
+ memcpy(&xsave->data[2], &X86_CPU(cpu_state)->env.fpip, sizeof(X86_CPU(cpu_state)->env.fpip));
ERROR: line over 90 characters
#7428: FILE: target/i386/hvf-utils/x86hvf.c:87:
+ memcpy(&xsave->data[8], &X86_CPU(cpu_state)->env.fpregs, sizeof(X86_CPU(cpu_state)->env.fpregs));
ERROR: line over 90 characters
#7429: FILE: target/i386/hvf-utils/x86hvf.c:88:
+ memcpy(&xsave->data[144], &X86_CPU(cpu_state)->env.ymmh_regs, sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
ERROR: line over 90 characters
#7430: FILE: target/i386/hvf-utils/x86hvf.c:89:
+ memcpy(&xsave->data[288], &X86_CPU(cpu_state)->env.zmmh_regs, sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
ERROR: line over 90 characters
#7431: FILE: target/i386/hvf-utils/x86hvf.c:90:
+ memcpy(&xsave->data[272], &X86_CPU(cpu_state)->env.opmask_regs, sizeof(X86_CPU(cpu_state)->env.opmask_regs));
ERROR: line over 90 characters
#7432: FILE: target/i386/hvf-utils/x86hvf.c:91:
+ memcpy(&xsave->data[240], &X86_CPU(cpu_state)->env.bnd_regs, sizeof(X86_CPU(cpu_state)->env.bnd_regs));
ERROR: line over 90 characters
#7433: FILE: target/i386/hvf-utils/x86hvf.c:92:
+ memcpy(&xsave->data[256], &X86_CPU(cpu_state)->env.bndcs_regs, sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
ERROR: line over 90 characters
#7434: FILE: target/i386/hvf-utils/x86hvf.c:93:
+ memcpy(&xsave->data[416], &X86_CPU(cpu_state)->env.hi16_zmm_regs, sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
ERROR: trailing whitespace
#7435: FILE: target/i386/hvf-utils/x86hvf.c:94:
+ $
ERROR: trailing whitespace
#7439: FILE: target/i386/hvf-utils/x86hvf.c:98:
+ $
ERROR: braces {} are necessary even for single statement blocks
#7440: FILE: target/i386/hvf-utils/x86hvf.c:99:
+ for (x = 0; x < 8; ++x)
+ xsave->data[1] |= ((!X86_CPU(cpu_state)->env.fptags[x]) << x);
ERROR: trailing whitespace
#7443: FILE: target/i386/hvf-utils/x86hvf.c:102:
+ $
ERROR: line over 90 characters
#7444: FILE: target/i386/hvf-utils/x86hvf.c:103:
+ memcpy(&xsave->data[40], &X86_CPU(cpu_state)->env.xmm_regs, sizeof(X86_CPU(cpu_state)->env.xmm_regs));
ERROR: trailing whitespace
#7445: FILE: target/i386/hvf-utils/x86hvf.c:104:
+ $
ERROR: trailing whitespace
#7448: FILE: target/i386/hvf-utils/x86hvf.c:107:
+ $
ERROR: space required before the open brace '{'
#7449: FILE: target/i386/hvf-utils/x86hvf.c:108:
+ if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, xsave->data, 4096)){
ERROR: externs should be avoided in .c files
#7454: FILE: target/i386/hvf-utils/x86hvf.c:113:
+void vmx_update_tpr(CPUState *cpu);
ERROR: trailing whitespace
#7459: FILE: target/i386/hvf-utils/x86hvf.c:118:
+ $
ERROR: do not use C99 // comments
#7466: FILE: target/i386/hvf-utils/x86hvf.c:125:
+ //wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]);
ERROR: trailing whitespace
#7476: FILE: target/i386/hvf-utils/x86hvf.c:135:
+ $
ERROR: trailing whitespace
#7497: FILE: target/i386/hvf-utils/x86hvf.c:156:
+ $
ERROR: trailing whitespace
#7500: FILE: target/i386/hvf-utils/x86hvf.c:159:
+ $
WARNING: line over 80 characters
#7505: FILE: target/i386/hvf-utils/x86hvf.c:164:
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
WARNING: line over 80 characters
#7506: FILE: target/i386/hvf-utils/x86hvf.c:165:
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
WARNING: line over 80 characters
#7507: FILE: target/i386/hvf-utils/x86hvf.c:166:
+ hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
ERROR: do not use C99 // comments
#7521: FILE: target/i386/hvf-utils/x86hvf.c:180:
+ // if (!osx_is_sierra())
ERROR: do not use C99 // comments
#7522: FILE: target/i386/hvf-utils/x86hvf.c:181:
+ // wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());
ERROR: trailing whitespace
#7531: FILE: target/i386/hvf-utils/x86hvf.c:190:
+ $
ERROR: trailing whitespace
#7533: FILE: target/i386/hvf-utils/x86hvf.c:192:
+ $
ERROR: line over 90 characters
#7538: FILE: target/i386/hvf-utils/x86hvf.c:197:
+ memcpy(&X86_CPU(cpu_state)->env.fpdp, &xsave->data[4], sizeof(X86_CPU(cpu_state)->env.fpdp));
ERROR: line over 90 characters
#7539: FILE: target/i386/hvf-utils/x86hvf.c:198:
+ memcpy(&X86_CPU(cpu_state)->env.fpip, &xsave->data[2], sizeof(X86_CPU(cpu_state)->env.fpip));
ERROR: line over 90 characters
#7540: FILE: target/i386/hvf-utils/x86hvf.c:199:
+ memcpy(&X86_CPU(cpu_state)->env.fpregs, &xsave->data[8], sizeof(X86_CPU(cpu_state)->env.fpregs));
ERROR: line over 90 characters
#7541: FILE: target/i386/hvf-utils/x86hvf.c:200:
+ memcpy(&X86_CPU(cpu_state)->env.ymmh_regs, &xsave->data[144], sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
ERROR: line over 90 characters
#7542: FILE: target/i386/hvf-utils/x86hvf.c:201:
+ memcpy(&X86_CPU(cpu_state)->env.zmmh_regs, &xsave->data[288], sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
ERROR: line over 90 characters
#7543: FILE: target/i386/hvf-utils/x86hvf.c:202:
+ memcpy(&X86_CPU(cpu_state)->env.opmask_regs, &xsave->data[272], sizeof(X86_CPU(cpu_state)->env.opmask_regs));
ERROR: line over 90 characters
#7544: FILE: target/i386/hvf-utils/x86hvf.c:203:
+ memcpy(&X86_CPU(cpu_state)->env.bnd_regs, &xsave->data[240], sizeof(X86_CPU(cpu_state)->env.bnd_regs));
ERROR: line over 90 characters
#7545: FILE: target/i386/hvf-utils/x86hvf.c:204:
+ memcpy(&X86_CPU(cpu_state)->env.bndcs_regs, &xsave->data[256], sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
ERROR: line over 90 characters
#7546: FILE: target/i386/hvf-utils/x86hvf.c:205:
+ memcpy(&X86_CPU(cpu_state)->env.hi16_zmm_regs, &xsave->data[416], sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
ERROR: trailing whitespace
#7547: FILE: target/i386/hvf-utils/x86hvf.c:206:
+ $
ERROR: trailing whitespace
#7548: FILE: target/i386/hvf-utils/x86hvf.c:207:
+ $
ERROR: trailing whitespace
#7553: FILE: target/i386/hvf-utils/x86hvf.c:212:
+ $
ERROR: suspect code indent for conditional statements (4, 7)
#7554: FILE: target/i386/hvf-utils/x86hvf.c:213:
+ for (x = 0; x < 8; ++x)
+ X86_CPU(cpu_state)->env.fptags[x] =
ERROR: trailing whitespace
#7557: FILE: target/i386/hvf-utils/x86hvf.c:216:
+ $
ERROR: line over 90 characters
#7558: FILE: target/i386/hvf-utils/x86hvf.c:217:
+ memcpy(&X86_CPU(cpu_state)->env.xmm_regs, &xsave->data[40], sizeof(X86_CPU(cpu_state)->env.xmm_regs));
ERROR: trailing whitespace
#7574: FILE: target/i386/hvf-utils/x86hvf.c:233:
+ $
ERROR: trailing whitespace
#7605: FILE: target/i386/hvf-utils/x86hvf.c:264:
+ $
ERROR: trailing whitespace
#7613: FILE: target/i386/hvf-utils/x86hvf.c:272:
+ $
ERROR: trailing whitespace
#7616: FILE: target/i386/hvf-utils/x86hvf.c:275:
+ $
ERROR: trailing whitespace
#7633: FILE: target/i386/hvf-utils/x86hvf.c:292:
+ $
ERROR: trailing whitespace
#7660: FILE: target/i386/hvf-utils/x86hvf.c:319:
+ $
ERROR: trailing whitespace
#7662: FILE: target/i386/hvf-utils/x86hvf.c:321:
+ $
ERROR: trailing whitespace
#7664: FILE: target/i386/hvf-utils/x86hvf.c:323:
+ $
ERROR: trailing whitespace
#7666: FILE: target/i386/hvf-utils/x86hvf.c:325:
+ $
ERROR: trailing whitespace
#7668: FILE: target/i386/hvf-utils/x86hvf.c:327:
+ $
ERROR: trailing whitespace
#7677: FILE: target/i386/hvf-utils/x86hvf.c:336:
+ $
ERROR: trailing whitespace
#7703: FILE: target/i386/hvf-utils/x86hvf.c:362:
+ $
ERROR: trailing whitespace
#7706: FILE: target/i386/hvf-utils/x86hvf.c:365:
+ $
ERROR: trailing whitespace
#7709: FILE: target/i386/hvf-utils/x86hvf.c:368:
+ $
ERROR: trailing whitespace
#7712: FILE: target/i386/hvf-utils/x86hvf.c:371:
+ $
ERROR: trailing whitespace
#7721: FILE: target/i386/hvf-utils/x86hvf.c:380:
+ $
ERROR: line over 90 characters
#7729: FILE: target/i386/hvf-utils/x86hvf.c:388:
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
ERROR: line over 90 characters
#7736: FILE: target/i386/hvf-utils/x86hvf.c:395:
+ wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
ERROR: line over 90 characters
#7744: FILE: target/i386/hvf-utils/x86hvf.c:403:
+ int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
ERROR: trailing whitespace
#7748: FILE: target/i386/hvf-utils/x86hvf.c:407:
+ $
ERROR: trailing whitespace
#7753: FILE: target/i386/hvf-utils/x86hvf.c:412:
+ $
ERROR: trailing whitespace
#7759: FILE: target/i386/hvf-utils/x86hvf.c:418:
+ $
WARNING: line over 80 characters
#7765: FILE: target/i386/hvf-utils/x86hvf.c:424:
+ uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
WARNING: line over 80 characters
#7775: FILE: target/i386/hvf-utils/x86hvf.c:434:
+ uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
ERROR: trailing whitespace
#7778: FILE: target/i386/hvf-utils/x86hvf.c:437:
+ $
ERROR: do not use C99 // comments
#7784: FILE: target/i386/hvf-utils/x86hvf.c:443:
+ //printf("reinject %lx err %d\n", info, err);
ERROR: line over 90 characters
#7799: FILE: target/i386/hvf-utils/x86hvf.c:458:
+ if (cpu_state->hvf_x86->interruptable && (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
ERROR: braces {} are necessary for all arms of this statement
#7803: FILE: target/i386/hvf-utils/x86hvf.c:462:
+ if (line >= 0)
[...]
ERROR: line over 90 characters
#7804: FILE: target/i386/hvf-utils/x86hvf.c:463:
+ wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
ERROR: braces {} are necessary for all arms of this statement
#7806: FILE: target/i386/hvf-utils/x86hvf.c:465:
+ if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD)
[...]
ERROR: trailing whitespace
#7814: FILE: target/i386/hvf-utils/x86hvf.c:473:
+ $
ERROR: line over 90 characters
#7826: FILE: target/i386/hvf-utils/x86hvf.c:485:
+ if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu_state) & IF_MASK)) ||
ERROR: line over 90 characters
#7858: FILE: target/i386/hvf-utils/x86hvf.h:10:
+void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr);
total: 1560 errors, 156 warnings, 7707 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/14: hvf: add conditional macros around hvf code in cpus.c...
Checking PATCH 4/14: hvf: add fields to CPUState and CPUX86State; add definitions...
ERROR: do not use C99 // comments
#21: FILE: include/qom/cpu.h:411:
+ // HVF
ERROR: do not use C99 // comments
#23: FILE: include/qom/cpu.h:413:
+ uint64_t hvf_fd; // fd of vcpu created by HVF
ERROR: do not use C99 // comments
#24: FILE: include/qom/cpu.h:414:
+ // Supporting data structures for VMCS capabilities
ERROR: do not use C99 // comments
#25: FILE: include/qom/cpu.h:415:
+ // and x86 emulation state
ERROR: "foo* bar" should be "foo *bar"
#26: FILE: include/qom/cpu.h:416:
+ struct hvf_vcpu_caps* hvf_caps;
ERROR: "foo* bar" should be "foo *bar"
#27: FILE: include/qom/cpu.h:417:
+ struct hvf_x86_state* hvf_x86;
total: 6 errors, 0 warnings, 71 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/14: hvf: use new helper functions for put/get xsave...
Checking PATCH 6/14: hvf: add compilation rules to Makefile.objs...
WARNING: architecture specific defines should be avoided
#32: FILE: vl.c:3754:
+#if defined(__APPLE__)
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/14: hvf: run hvf code through checkpatch.pl and fix style issues...
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
ERROR: space required before the open brace '{'
#291: FILE: target/i386/hvf-all.c:247:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}},
ERROR: space required after that close brace '}'
#291: FILE: target/i386/hvf-all.c:247:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}},
ERROR: space required before the open brace '{'
#293: FILE: target/i386/hvf-all.c:249:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}},
ERROR: space required after that close brace '}'
#293: FILE: target/i386/hvf-all.c:249:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}},
ERROR: space required before the open brace '{'
#295: FILE: target/i386/hvf-all.c:251:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}},
ERROR: space required after that close brace '}'
#295: FILE: target/i386/hvf-all.c:251:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}},
ERROR: space required before the open brace '{'
#297: FILE: target/i386/hvf-all.c:253:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}},
ERROR: space required after that close brace '}'
#297: FILE: target/i386/hvf-all.c:253:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}},
ERROR: space required before the open brace '{'
#299: FILE: target/i386/hvf-all.c:255:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}},
ERROR: space required after that close brace '}'
#299: FILE: target/i386/hvf-all.c:255:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}},
ERROR: space required before the open brace '{'
#301: FILE: target/i386/hvf-all.c:257:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}},
ERROR: space required after that close brace '}'
#301: FILE: target/i386/hvf-all.c:257:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}},
ERROR: space required before the open brace '{'
#303: FILE: target/i386/hvf-all.c:259:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}},
ERROR: space required after that close brace '}'
#303: FILE: target/i386/hvf-all.c:259:
+ vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}},
WARNING: line over 80 characters
#448: FILE: target/i386/hvf-all.c:420:
+static void do_hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
ERROR: trailing whitespace
#554: FILE: target/i386/hvf-all.c:500:
+ $
ERROR: trailing whitespace
#560: FILE: target/i386/hvf-all.c:504:
+ $
ERROR: trailing whitespace
#567: FILE: target/i386/hvf-all.c:510:
+ $
ERROR: trailing whitespace
#573: FILE: target/i386/hvf-all.c:515:
+ $
ERROR: trailing whitespace
#579: FILE: target/i386/hvf-all.c:520:
+ $
ERROR: trailing whitespace
#585: FILE: target/i386/hvf-all.c:525:
+ $
ERROR: trailing whitespace
#591: FILE: target/i386/hvf-all.c:530:
+ $
ERROR: trailing whitespace
#597: FILE: target/i386/hvf-all.c:535:
+ $
ERROR: trailing whitespace
#603: FILE: target/i386/hvf-all.c:540:
+ $
ERROR: trailing whitespace
#609: FILE: target/i386/hvf-all.c:545:
+ $
ERROR: trailing whitespace
#613: FILE: target/i386/hvf-all.c:548:
+ $
ERROR: trailing whitespace
#618: FILE: target/i386/hvf-all.c:551:
+ $
ERROR: trailing whitespace
#622: FILE: target/i386/hvf-all.c:554:
+ $
ERROR: trailing whitespace
#633: FILE: target/i386/hvf-all.c:565:
+ $
WARNING: line over 80 characters
#671: FILE: target/i386/hvf-all.c:607:
+ cpu->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#671: FILE: target/i386/hvf-all.c:607:
+ cpu->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
WARNING: line over 80 characters
#672: FILE: target/i386/hvf-all.c:608:
+ cpu->hvf_x86 = (struct hvf_x86_state *)g_malloc0(sizeof(struct hvf_x86_state));
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#672: FILE: target/i386/hvf-all.c:608:
+ cpu->hvf_x86 = (struct hvf_x86_state *)g_malloc0(sizeof(struct hvf_x86_state));
WARNING: line over 80 characters
#2448: FILE: target/i386/hvf-utils/x86.h:468:
+ "shl $32,%%rdx; " /* shift higher 32 bits stored in rdx up */
ERROR: externs should be avoided in .c files
#5918: FILE: target/i386/hvf-utils/x86_emu.c:48:
+void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data,
ERROR: unnecessary whitespace before a quoted newline
#7707: FILE: target/i386/hvf-utils/x86_emu.c:1512:
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu),
ERROR: unnecessary whitespace before a quoted newline
#7717: FILE: target/i386/hvf-utils/x86_emu.c:1520:
+ "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu),
total: 33 errors, 4 warnings, 8321 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 8/14: apic: add function to apic that will be used by hvf...
Checking PATCH 9/14: hvf: implement hvf_get_supported_cpuid...
ERROR: return is not a function, parentheses are not required
#46: FILE: target/i386/hvf-utils/x86_cpuid.c:116:
+ return ((cap_exit & (1 << 23)) && (cap_entry & (1 << 16)));
WARNING: line over 80 characters
#142: FILE: target/i386/hvf-utils/x86_cpuid.c:388:
+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
WARNING: line over 80 characters
#144: FILE: target/i386/hvf-utils/x86_cpuid.c:390:
+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |
WARNING: line over 80 characters
#145: FILE: target/i386/hvf-utils/x86_cpuid.c:391:
+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;
total: 1 errors, 3 warnings, 153 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 10/14: hvf: refactor cpuid code...
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
ERROR: trailing whitespace
#218: FILE: target/i386/cpu.c:1742:
+ } $
WARNING: line over 80 characters
#367: FILE: target/i386/hvf-all.c:607:
+ hvf_state->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#367: FILE: target/i386/hvf-all.c:607:
+ hvf_state->hvf_caps = (struct hvf_vcpu_caps *)g_malloc0(sizeof(struct hvf_vcpu_caps));
WARNING: line over 80 characters
#413: FILE: target/i386/hvf-all.c:645:
+ wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(hvf_state->hvf_caps->vmx_cap_entry,
total: 2 errors, 2 warnings, 361 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/14: hvf: implement vga dirty page tracking...
ERROR: braces {} are necessary for all arms of this statement
#104: FILE: target/i386/hvf-all.c:507:
+ if (old != 0)
[...]
ERROR: braces {} are necessary for all arms of this statement
#113: FILE: target/i386/hvf-all.c:516:
+ if (new != 0)
[...]
total: 2 errors, 0 warnings, 130 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 12/14: hvf: move fields from CPUState to CPUX86State...
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Argument "m" isn't numeric in numeric eq (==) at ./scripts/checkpatch.pl line 2479.
Use of uninitialized value $1 in concatenation (.) or string at ./scripts/checkpatch.pl line 2480.
WARNING: line over 80 characters
#206: FILE: target/i386/hvf-all.c:678:
+ env->hvf_emul = (HVFX86EmulatorState *)g_malloc0(sizeof(HVFX86EmulatorState));
ERROR: unnecessary cast may hide bugs, use g_new0 instead
#206: FILE: target/i386/hvf-all.c:678:
+ env->hvf_emul = (HVFX86EmulatorState *)g_malloc0(sizeof(HVFX86EmulatorState));
WARNING: line over 80 characters
#1339: FILE: target/i386/hvf-utils/x86_decode.c:1988:
+static inline void decode_displacement(CPUX86State *env, struct x86_decode *decode)
WARNING: line over 80 characters
#1487: FILE: target/i386/hvf-utils/x86_decode.c:2185:
+ return linear_addr_size(ENV_GET_CPU(env), addr, decode->addressing_size, seg);
WARNING: line over 80 characters
#1681: FILE: target/i386/hvf-utils/x86_emu.c:221:
+ return (ptr - (addr_t)&env->hvf_emul->regs[0]) < sizeof(env->hvf_emul->regs);
ERROR: spaces required around that '+' (ctx:WxV)
#1793: FILE: target/i386/hvf-utils/x86_emu.c:331:
+ EXEC_2OP_ARITH_CMD(env, decode, +get_CF(env)+, SET_FLAGS_OSZAPC_ADD, true);
^
ERROR: spaces required around that '+' (ctx:VxO)
#1793: FILE: target/i386/hvf-utils/x86_emu.c:331:
+ EXEC_2OP_ARITH_CMD(env, decode, +get_CF(env)+, SET_FLAGS_OSZAPC_ADD, true);
^
ERROR: spaces required around that '-' (ctx:VxO)
#1802: FILE: target/i386/hvf-utils/x86_emu.c:337:
+ EXEC_2OP_ARITH_CMD(env, decode, -get_CF(env)-, SET_FLAGS_OSZAPC_SUB, true);
^
ERROR: spaces required around that '+' (ctx:WxV)
#1874: FILE: target/i386/hvf-utils/x86_emu.c:393:
+ EXEC_2OP_ARITH_CMD(env, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
^
ERROR: spaces required around that '+' (ctx:VxO)
#1874: FILE: target/i386/hvf-utils/x86_emu.c:393:
+ EXEC_2OP_ARITH_CMD(env, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
^
ERROR: spaces required around that '-' (ctx:VxO)
#1888: FILE: target/i386/hvf-utils/x86_emu.c:403:
+ EXEC_2OP_ARITH_CMD(env, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
^
WARNING: line over 80 characters
#1959: FILE: target/i386/hvf-utils/x86_emu.c:456:
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), &RAX(env), 1, decode->operand_size, 1);
ERROR: line over 90 characters
#1980: FILE: target/i386/hvf-utils/x86_emu.c:473:
+ hvf_handle_io(ENV_GET_CPU(env), decode->op[0].val, &val, 0, decode->operand_size, 1);
WARNING: line over 80 characters
#1995: FILE: target/i386/hvf-utils/x86_emu.c:484:
+ hvf_handle_io(ENV_GET_CPU(env), DX(env), &val, 0, decode->operand_size, 1);
WARNING: line over 80 characters
#2031: FILE: target/i386/hvf-utils/x86_emu.c:512:
+static inline void string_rep(struct CPUX86State *env, struct x86_decode *decode,
WARNING: line over 80 characters
#2057: FILE: target/i386/hvf-utils/x86_emu.c:531:
+ addr_t addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
WARNING: line over 80 characters
#2064: FILE: target/i386/hvf-utils/x86_emu.c:536:
+ vmx_write_mem(ENV_GET_CPU(env), addr, env->hvf_emul->mmio_buf, decode->operand_size);
WARNING: line over 80 characters
#2093: FILE: target/i386/hvf-utils/x86_emu.c:556:
+ vmx_read_mem(ENV_GET_CPU(env), env->hvf_emul->mmio_buf, addr, decode->operand_size);
WARNING: line over 80 characters
#2126: FILE: target/i386/hvf-utils/x86_emu.c:581:
+ dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
WARNING: line over 80 characters
#2164: FILE: target/i386/hvf-utils/x86_emu.c:608:
+ dst_addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size,
ERROR: line over 90 characters
#2207: FILE: target/i386/hvf-utils/x86_emu.c:638:
+ addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, REG_SEG_ES);
ERROR: line over 90 characters
#2237: FILE: target/i386/hvf-utils/x86_emu.c:661:
+ addr = linear_addr_size(ENV_GET_CPU(env), RDI(env), decode->addressing_size, REG_SEG_ES);
WARNING: line over 80 characters
#2240: FILE: target/i386/hvf-utils/x86_emu.c:663:
+ vmx_read_mem(ENV_GET_CPU(env), &decode->op[1].val, addr, decode->operand_size);
ERROR: unnecessary whitespace before a quoted newline
#3032: FILE: target/i386/hvf-utils/x86_emu.c:1517:
+ printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env),
ERROR: unnecessary whitespace before a quoted newline
#3042: FILE: target/i386/hvf-utils/x86_emu.c:1525:
+ "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(env),
WARNING: line over 80 characters
#3357: FILE: target/i386/hvf-utils/x86_flags.c:233:
+ return ((env->hvf_emul->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
total: 12 errors, 14 warnings, 3527 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 13/14: hvf: refactor event injection code for hvf...
WARNING: line over 80 characters
#36: FILE: target/i386/hvf-all.c:753:
+static void hvf_store_events(CPUState *cpu, uint32_t ins_len, uint64_t idtvec_info)
total: 0 errors, 1 warnings, 222 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 14/14: hvf: inject General Protection Fault when vmexit through vmcall...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script
2017-08-28 1:56 ` [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script Sergio Andres Gomez Del Real
@ 2017-08-29 9:00 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:00 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:41PM -0500, Sergio Andres Gomez Del Real wrote:
> @@ -3619,6 +3619,16 @@ applicable to MAC and Windows platform, and thus does not conflict with
> KVM.
> ETEXI
>
> +DEF("enable-hvf", 0, QEMU_OPTION_enable_hvf, \
> + "-enable-hvf enable Hypervisor.framework virtualization support\n", QEMU_ARCH_I386)
> +STEXI
> +@item -enable-hvf
> +@findex -enable-hvf
> +Enable Hypervisor.framework support. This option is only available if
> +HVF support is enabled when compiling. HVF is only applicable to MAC
> +platform, and thus does not conflict with KVM.
> +ETEXI
-enable-$ACCEL is a legacy option. The preferred syntax is -M accel=$ACCL.
There's no need to add -enable-hvf, please remove it in the next
revision of this patch. Users that want hvf should use the modern -M
accel=hvf syntax.
Besides this:
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository
2017-08-28 1:56 ` [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository Sergio Andres Gomez Del Real
@ 2017-08-29 9:12 ` Stefan Hajnoczi
2017-08-29 11:22 ` Daniel P. Berrange
1 sibling, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:12 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:42PM -0500, Sergio Andres Gomez Del Real wrote:
> This file begins tracking the files that will be the code base for HVF
> support in QEMU.
In order to merge a big chunk of third-party code the following items
must be clear:
1. What functionality is supported by this code (i.e. why merge this)?
2. What functionality is missing or known issues in this code?
3. Which git repos does this code come from?
4. Each file's license and copyright information?
5. Future strategy for syncing changes from upstream repos?
6. That coding style violations are resolved by patches that follow?
Please address these points in the patch (e.g. README.md) or the commit
description. The license and copyright information must be in each file
so that the origins of the code stay clear as it evolves in the future.
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
> ---
> cpus.c | 42 +
> include/sysemu/hvf.h | 96 ++
> target/i386/hvf-all.c | 982 +++++++++++++++++++++
> target/i386/hvf-i386.h | 48 +
> target/i386/hvf-utils/Makefile.objs | 1 +
> target/i386/hvf-utils/README.md | 7 +
> target/i386/hvf-utils/vmcs.h | 368 ++++++++
> target/i386/hvf-utils/vmx.h | 200 +++++
> target/i386/hvf-utils/x86.c | 174 ++++
> target/i386/hvf-utils/x86.h | 470 ++++++++++
> target/i386/hvf-utils/x86_cpuid.c | 270 ++++++
> target/i386/hvf-utils/x86_cpuid.h | 51 ++
> target/i386/hvf-utils/x86_decode.c | 1659 +++++++++++++++++++++++++++++++++++
> target/i386/hvf-utils/x86_decode.h | 314 +++++++
> target/i386/hvf-utils/x86_descr.c | 124 +++
> target/i386/hvf-utils/x86_descr.h | 40 +
> target/i386/hvf-utils/x86_emu.c | 1466 +++++++++++++++++++++++++++++++
> target/i386/hvf-utils/x86_emu.h | 16 +
> target/i386/hvf-utils/x86_flags.c | 317 +++++++
> target/i386/hvf-utils/x86_flags.h | 218 +++++
> target/i386/hvf-utils/x86_gen.h | 36 +
> target/i386/hvf-utils/x86_mmu.c | 254 ++++++
> target/i386/hvf-utils/x86_mmu.h | 28 +
> target/i386/hvf-utils/x86hvf.c | 501 +++++++++++
> target/i386/hvf-utils/x86hvf.h | 19 +
> 25 files changed, 7701 insertions(+)
> create mode 100644 include/sysemu/hvf.h
> create mode 100644 target/i386/hvf-all.c
> create mode 100644 target/i386/hvf-i386.h
> create mode 100644 target/i386/hvf-utils/Makefile.objs
> create mode 100644 target/i386/hvf-utils/README.md
> create mode 100644 target/i386/hvf-utils/vmcs.h
> create mode 100644 target/i386/hvf-utils/vmx.h
> create mode 100644 target/i386/hvf-utils/x86.c
> create mode 100644 target/i386/hvf-utils/x86.h
> create mode 100644 target/i386/hvf-utils/x86_cpuid.c
> create mode 100644 target/i386/hvf-utils/x86_cpuid.h
> create mode 100644 target/i386/hvf-utils/x86_decode.c
> create mode 100644 target/i386/hvf-utils/x86_decode.h
> create mode 100644 target/i386/hvf-utils/x86_descr.c
> create mode 100644 target/i386/hvf-utils/x86_descr.h
> create mode 100644 target/i386/hvf-utils/x86_emu.c
> create mode 100644 target/i386/hvf-utils/x86_emu.h
> create mode 100644 target/i386/hvf-utils/x86_flags.c
> create mode 100644 target/i386/hvf-utils/x86_flags.h
> create mode 100644 target/i386/hvf-utils/x86_gen.h
> create mode 100644 target/i386/hvf-utils/x86_mmu.c
> create mode 100644 target/i386/hvf-utils/x86_mmu.h
> create mode 100644 target/i386/hvf-utils/x86hvf.c
> create mode 100644 target/i386/hvf-utils/x86hvf.h
>
> diff --git a/cpus.c b/cpus.c
> index 9bed61eefc..a2cd9dfa5d 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -1434,6 +1434,48 @@ static void *qemu_hax_cpu_thread_fn(void *arg)
> return NULL;
> }
>
> +/* The HVF-specific vCPU thread function. This one should only run when the host
> + * CPU supports the VMX "unrestricted guest" feature. */
> +static void *qemu_hvf_cpu_thread_fn(void *arg)
> +{
> + CPUState *cpu = arg;
> +
> + int r;
> +
> + assert(hvf_enabled());
> +
> + rcu_register_thread();
> +
> + qemu_mutex_lock_iothread();
> + qemu_thread_get_self(cpu->thread);
> +
> + cpu->thread_id = qemu_get_thread_id();
> + cpu->can_do_io = 1;
> + current_cpu = cpu;
> +
> + hvf_init_vcpu(cpu);
> +
> + /* signal CPU creation */
> + cpu->created = true;
> + qemu_cond_signal(&qemu_cpu_cond);
> +
> + do {
> + if (cpu_can_run(cpu)) {
> + r = hvf_vcpu_exec(cpu);
> + if (r == EXCP_DEBUG) {
> + cpu_handle_guest_debug(cpu);
> + }
> + }
> + qemu_hvf_wait_io_event(cpu);
> + } while (!cpu->unplug || cpu_can_run(cpu));
> +
> + hvf_vcpu_destroy(cpu);
> + cpu->created = false;
> + qemu_cond_signal(&qemu_cpu_cond);
> + qemu_mutex_unlock_iothread();
> + return NULL;
> +}
> +
> #ifdef _WIN32
> static void CALLBACK dummy_apc_func(ULONG_PTR unused)
> {
> diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h
> new file mode 100644
> index 0000000000..b96bd5e8ba
> --- /dev/null
> +++ b/include/sysemu/hvf.h
> @@ -0,0 +1,96 @@
> +/*
> + * QEMU Hypervisor.framework (HVF) support
> + *
> + * Copyright Google Inc., 2017
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +/* header to be included in non-HVF-specific code */
> +#ifndef _HVF_H
> +#define _HVF_H
> +
> +#include "config-host.h"
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "hw/hw.h"
> +#include "target/i386/cpu.h"
> +#include "qemu/bitops.h"
> +#include "exec/memory.h"
> +#include "sysemu/accel.h"
> +#include <Hypervisor/hv.h>
> +#include <Hypervisor/hv_vmx.h>
> +#include <Hypervisor/hv_error.h>
> +
> +
> +typedef struct hvf_slot {
> + uint64_t start;
> + uint64_t size;
> + uint8_t *mem;
> + int slot_id;
> +} hvf_slot;
> +
> +typedef struct HVFState {
> + AccelState parent;
> + hvf_slot slots[32];
> + int num_slots;
> +} HVFState;
> +
> +struct hvf_vcpu_caps {
> + uint64_t vmx_cap_pinbased;
> + uint64_t vmx_cap_procbased;
> + uint64_t vmx_cap_procbased2;
> + uint64_t vmx_cap_entry;
> + uint64_t vmx_cap_exit;
> + uint64_t vmx_cap_preemption_timer;
> +};
> +
> +int __hvf_set_memory(hvf_slot *);
> +void hvf_set_phys_mem(MemoryRegionSection *, bool);
> +void hvf_handle_io(CPUArchState *, uint16_t, void *,
> + int, int, int);
> +hvf_slot *hvf_find_overlap_slot(uint64_t, uint64_t);
> +
> +/* Returns 1 if HVF is available and enabled, 0 otherwise. */
> +int hvf_enabled(void);
> +
> +/* Disable HVF if |disable| is 1, otherwise, enable it iff it is supported by the host CPU.
> + * Use hvf_enabled() after this to get the result. */
> +void hvf_disable(int disable);
> +
> +/* Returns non-0 if the host CPU supports the VMX "unrestricted guest" feature which
> + * allows the virtual CPU to directly run in "real mode". If true, this allows QEMU to run
> + * several vCPU threads in parallel (see cpus.c). Otherwise, only a a single TCG thread
> + * can run, and it will call HVF to run the current instructions, except in case of
> + * "real mode" (paging disabled, typically at boot time), or MMIO operations. */
> +// int hvf_ug_platform(void); does not apply to HVF; assume we must be in UG mode
> +
> +int hvf_sync_vcpus(void);
> +
> +int hvf_init_vcpu(CPUState *);
> +int hvf_vcpu_exec(CPUState *);
> +int hvf_smp_cpu_exec(CPUState *);
> +void hvf_cpu_synchronize_state(CPUState *);
> +void hvf_cpu_synchronize_post_reset(CPUState *);
> +void hvf_cpu_synchronize_post_init(CPUState *);
> +void _hvf_cpu_synchronize_post_init(CPUState *, run_on_cpu_data);
> +
> +void hvf_vcpu_destroy(CPUState *);
> +void hvf_raise_event(CPUState *);
> +// void hvf_reset_vcpu_state(void *opaque);
> +void vmx_reset_vcpu(CPUState *);
> +void __hvf_cpu_synchronize_state(CPUState *, run_on_cpu_data);
> +void __hvf_cpu_synchronize_post_reset(CPUState *, run_on_cpu_data);
> +void vmx_update_tpr(CPUState *);
> +void update_apic_tpr(CPUState *);
> +int apic_get_highest_priority_irr(DeviceState *);
> +int hvf_put_registers(CPUState *);
> +
> +#define TYPE_HVF_ACCEL ACCEL_CLASS_NAME("hvf")
> +
> +#define HVF_STATE(obj) \
> + OBJECT_CHECK(HVFState, (obj), TYPE_HVF_ACCEL)
> +
> +#endif
> diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
> new file mode 100644
> index 0000000000..06cd8429eb
> --- /dev/null
> +++ b/target/i386/hvf-all.c
> @@ -0,0 +1,982 @@
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +
> +#include "sysemu/hvf.h"
> +#include "hvf-i386.h"
> +#include "hvf-utils/vmcs.h"
> +#include "hvf-utils/vmx.h"
> +#include "hvf-utils/x86.h"
> +#include "hvf-utils/x86_descr.h"
> +#include "hvf-utils/x86_mmu.h"
> +#include "hvf-utils/x86_decode.h"
> +#include "hvf-utils/x86_emu.h"
> +#include "hvf-utils/x86_cpuid.h"
> +#include "hvf-utils/x86hvf.h"
> +
> +#include <Hypervisor/hv.h>
> +#include <Hypervisor/hv_vmx.h>
> +
> +#include "exec/address-spaces.h"
> +#include "exec/exec-all.h"
> +#include "exec/ioport.h"
> +#include "hw/i386/apic_internal.h"
> +#include "hw/boards.h"
> +#include "qemu/main-loop.h"
> +#include "strings.h"
> +#include "trace.h"
> +#include "sysemu/accel.h"
> +#include "sysemu/sysemu.h"
> +#include "target/i386/cpu.h"
> +
> +pthread_rwlock_t mem_lock = PTHREAD_RWLOCK_INITIALIZER;
> +HVFState *hvf_state;
> +static int hvf_disabled = 1;
> +
> +static void assert_hvf_ok(hv_return_t ret)
> +{
> + if (ret == HV_SUCCESS)
> + return;
> +
> + switch (ret) {
> + case HV_ERROR:
> + fprintf(stderr, "Error: HV_ERROR\n");
> + break;
> + case HV_BUSY:
> + fprintf(stderr, "Error: HV_BUSY\n");
> + break;
> + case HV_BAD_ARGUMENT:
> + fprintf(stderr, "Error: HV_BAD_ARGUMENT\n");
> + break;
> + case HV_NO_RESOURCES:
> + fprintf(stderr, "Error: HV_NO_RESOURCES\n");
> + break;
> + case HV_NO_DEVICE:
> + fprintf(stderr, "Error: HV_NO_DEVICE\n");
> + break;
> + case HV_UNSUPPORTED:
> + fprintf(stderr, "Error: HV_UNSUPPORTED\n");
> + break;
> + default:
> + fprintf(stderr, "Unknown Error\n");
> + }
> +
> + abort();
> +}
> +
> +// Memory slots/////////////////////////////////////////////////////////////////
> +
> +hvf_slot *hvf_find_overlap_slot(uint64_t start, uint64_t end) {
> + hvf_slot *slot;
> + int x;
> + for (x = 0; x < hvf_state->num_slots; ++x) {
> + slot = &hvf_state->slots[x];
> + if (slot->size && start < (slot->start + slot->size) && end > slot->start)
> + return slot;
> + }
> + return NULL;
> +}
> +
> +struct mac_slot {
> + int present;
> + uint64_t size;
> + uint64_t gpa_start;
> + uint64_t gva;
> +};
> +
> +struct mac_slot mac_slots[32];
> +#define ALIGN(x, y) (((x)+(y)-1) & ~((y)-1))
> +
> +int __hvf_set_memory(hvf_slot *slot)
> +{
> + struct mac_slot *macslot;
> + hv_memory_flags_t flags;
> + pthread_rwlock_wrlock(&mem_lock);
> + hv_return_t ret;
> +
> + macslot = &mac_slots[slot->slot_id];
> +
> + if (macslot->present) {
> + if (macslot->size != slot->size) {
> + macslot->present = 0;
> + ret = hv_vm_unmap(macslot->gpa_start, macslot->size);
> + assert_hvf_ok(ret);
> + }
> + }
> +
> + if (!slot->size) {
> + pthread_rwlock_unlock(&mem_lock);
> + return 0;
> + }
> +
> + flags = HV_MEMORY_READ | HV_MEMORY_WRITE | HV_MEMORY_EXEC;
> +
> + macslot->present = 1;
> + macslot->gpa_start = slot->start;
> + macslot->size = slot->size;
> + ret = hv_vm_map((hv_uvaddr_t)slot->mem, slot->start, slot->size, flags);
> + assert_hvf_ok(ret);
> + pthread_rwlock_unlock(&mem_lock);
> + return 0;
> +}
> +
> +void hvf_set_phys_mem(MemoryRegionSection* section, bool add)
> +{
> + hvf_slot *mem;
> + MemoryRegion *area = section->mr;
> +
> + if (!memory_region_is_ram(area)) return;
> +
> + mem = hvf_find_overlap_slot(
> + section->offset_within_address_space,
> + section->offset_within_address_space + int128_get64(section->size));
> +
> + if (mem && add) {
> + if (mem->size == int128_get64(section->size) &&
> + mem->start == section->offset_within_address_space &&
> + mem->mem == (memory_region_get_ram_ptr(area) + section->offset_within_region))
> + return; // Same region was attempted to register, go away.
> + }
> +
> + // Region needs to be reset. set the size to 0 and remap it.
> + if (mem) {
> + mem->size = 0;
> + if (__hvf_set_memory(mem)) {
> + fprintf(stderr, "Failed to reset overlapping slot\n");
> + abort();
> + }
> + }
> +
> + if (!add) return;
> +
> + // Now make a new slot.
> + int x;
> +
> + for (x = 0; x < hvf_state->num_slots; ++x) {
> + mem = &hvf_state->slots[x];
> + if (!mem->size)
> + break;
> + }
> +
> + if (x == hvf_state->num_slots) {
> + fprintf(stderr, "No free slots\n");
> + abort();
> + }
> +
> + mem->size = int128_get64(section->size);
> + mem->mem = memory_region_get_ram_ptr(area) + section->offset_within_region;
> + mem->start = section->offset_within_address_space;
> +
> + if (__hvf_set_memory(mem)) {
> + fprintf(stderr, "Error registering new memory slot\n");
> + abort();
> + }
> +}
> +
> +/* return -1 if no bit is set */
> +static int get_highest_priority_int(uint32_t *tab)
> +{
> + int i;
> + for (i = 7; i >= 0; i--) {
> + if (tab[i] != 0) {
> + return i * 32 + apic_fls_bit(tab[i]);
> + }
> + }
> + return -1;
> +}
> +
> +void vmx_update_tpr(CPUState *cpu)
> +{
> + // TODO: need integrate APIC handling
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4;
> + int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);
> +
> + wreg(cpu->hvf_fd, HV_X86_TPR, tpr);
> + if (irr == -1)
> + wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
> + else
> + wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : irr >> 4);
> +}
> +
> +void update_apic_tpr(CPUState *cpu)
> +{
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + int tpr = rreg(cpu->hvf_fd, HV_X86_TPR) >> 4;
> + cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
> +}
> +
> +#define VECTORING_INFO_VECTOR_MASK 0xff
> +
> +// TODO: taskswitch handling
> +static void save_state_to_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
> +{
> + /* CR3 and ldt selector are not saved intentionally */
> + tss->eip = EIP(cpu);
> + tss->eflags = EFLAGS(cpu);
> + tss->eax = EAX(cpu);
> + tss->ecx = ECX(cpu);
> + tss->edx = EDX(cpu);
> + tss->ebx = EBX(cpu);
> + tss->esp = ESP(cpu);
> + tss->ebp = EBP(cpu);
> + tss->esi = ESI(cpu);
> + tss->edi = EDI(cpu);
> +
> + tss->es = vmx_read_segment_selector(cpu, REG_SEG_ES).sel;
> + tss->cs = vmx_read_segment_selector(cpu, REG_SEG_CS).sel;
> + tss->ss = vmx_read_segment_selector(cpu, REG_SEG_SS).sel;
> + tss->ds = vmx_read_segment_selector(cpu, REG_SEG_DS).sel;
> + tss->fs = vmx_read_segment_selector(cpu, REG_SEG_FS).sel;
> + tss->gs = vmx_read_segment_selector(cpu, REG_SEG_GS).sel;
> +}
> +
> +static void load_state_from_tss32(CPUState *cpu, struct x86_tss_segment32 *tss)
> +{
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, tss->cr3);
> +
> + RIP(cpu) = tss->eip;
> + EFLAGS(cpu) = tss->eflags | 2;
> +
> + /* General purpose registers */
> + RAX(cpu) = tss->eax;
> + RCX(cpu) = tss->ecx;
> + RDX(cpu) = tss->edx;
> + RBX(cpu) = tss->ebx;
> + RSP(cpu) = tss->esp;
> + RBP(cpu) = tss->ebp;
> + RSI(cpu) = tss->esi;
> + RDI(cpu) = tss->edi;
> +
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ldt}}, REG_SEG_LDTR);
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->es}}, REG_SEG_ES);
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->cs}}, REG_SEG_CS);
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ss}}, REG_SEG_SS);
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->ds}}, REG_SEG_DS);
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->fs}}, REG_SEG_FS);
> + vmx_write_segment_selector(cpu, (x68_segment_selector){{tss->gs}}, REG_SEG_GS);
> +
> +#if 0
> + load_segment(cpu, REG_SEG_LDTR, tss->ldt);
> + load_segment(cpu, REG_SEG_ES, tss->es);
> + load_segment(cpu, REG_SEG_CS, tss->cs);
> + load_segment(cpu, REG_SEG_SS, tss->ss);
> + load_segment(cpu, REG_SEG_DS, tss->ds);
> + load_segment(cpu, REG_SEG_FS, tss->fs);
> + load_segment(cpu, REG_SEG_GS, tss->gs);
> +#endif
> +}
> +
> +static int task_switch_32(CPUState *cpu, x68_segment_selector tss_sel, x68_segment_selector old_tss_sel,
> + uint64_t old_tss_base, struct x86_segment_descriptor *new_desc)
> +{
> + struct x86_tss_segment32 tss_seg;
> + uint32_t new_tss_base = x86_segment_base(new_desc);
> + uint32_t eip_offset = offsetof(struct x86_tss_segment32, eip);
> + uint32_t ldt_sel_offset = offsetof(struct x86_tss_segment32, ldt);
> +
> + vmx_read_mem(cpu, &tss_seg, old_tss_base, sizeof(tss_seg));
> + save_state_to_tss32(cpu, &tss_seg);
> +
> + vmx_write_mem(cpu, old_tss_base + eip_offset, &tss_seg.eip, ldt_sel_offset - eip_offset);
> + vmx_read_mem(cpu, &tss_seg, new_tss_base, sizeof(tss_seg));
> +
> + if (old_tss_sel.sel != 0xffff) {
> + tss_seg.prev_tss = old_tss_sel.sel;
> +
> + vmx_write_mem(cpu, new_tss_base, &tss_seg.prev_tss, sizeof(tss_seg.prev_tss));
> + }
> + load_state_from_tss32(cpu, &tss_seg);
> + return 0;
> +}
> +
> +static void vmx_handle_task_switch(CPUState *cpu, x68_segment_selector tss_sel, int reason, bool gate_valid, uint8_t gate, uint64_t gate_type)
> +{
> + uint64_t rip = rreg(cpu->hvf_fd, HV_X86_RIP);
> + if (!gate_valid || (gate_type != VMCS_INTR_T_HWEXCEPTION &&
> + gate_type != VMCS_INTR_T_HWINTR &&
> + gate_type != VMCS_INTR_T_NMI)) {
> + int ins_len = rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
> + macvm_set_rip(cpu, rip + ins_len);
> + return;
> + }
> +
> + load_regs(cpu);
> +
> + struct x86_segment_descriptor curr_tss_desc, next_tss_desc;
> + int ret;
> + x68_segment_selector old_tss_sel = vmx_read_segment_selector(cpu, REG_SEG_TR);
> + uint64_t old_tss_base = vmx_read_segment_base(cpu, REG_SEG_TR);
> + uint32_t desc_limit;
> + struct x86_call_gate task_gate_desc;
> + struct vmx_segment vmx_seg;
> +
> + x86_read_segment_descriptor(cpu, &next_tss_desc, tss_sel);
> + x86_read_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
> +
> + if (reason == TSR_IDT_GATE && gate_valid) {
> + int dpl;
> +
> + ret = x86_read_call_gate(cpu, &task_gate_desc, gate);
> +
> + dpl = task_gate_desc.dpl;
> + x68_segment_selector cs = vmx_read_segment_selector(cpu, REG_SEG_CS);
> + if (tss_sel.rpl > dpl || cs.rpl > dpl)
> + ;//DPRINTF("emulate_gp");
> + }
> +
> + desc_limit = x86_segment_limit(&next_tss_desc);
> + if (!next_tss_desc.p || ((desc_limit < 0x67 && (next_tss_desc.type & 8)) || desc_limit < 0x2b)) {
> + VM_PANIC("emulate_ts");
> + }
> +
> + if (reason == TSR_IRET || reason == TSR_JMP) {
> + curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
> + x86_write_segment_descriptor(cpu, &curr_tss_desc, old_tss_sel);
> + }
> +
> + if (reason == TSR_IRET)
> + EFLAGS(cpu) &= ~RFLAGS_NT;
> +
> + if (reason != TSR_CALL && reason != TSR_IDT_GATE)
> + old_tss_sel.sel = 0xffff;
> +
> + if (reason != TSR_IRET) {
> + next_tss_desc.type |= (1 << 1); /* set busy flag */
> + x86_write_segment_descriptor(cpu, &next_tss_desc, tss_sel);
> + }
> +
> + if (next_tss_desc.type & 8)
> + ret = task_switch_32(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
> + else
> + //ret = task_switch_16(cpu, tss_sel, old_tss_sel, old_tss_base, &next_tss_desc);
> + VM_PANIC("task_switch_16");
> +
> + macvm_set_cr0(cpu->hvf_fd, rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0) | CR0_TS);
> + x86_segment_descriptor_to_vmx(cpu, tss_sel, &next_tss_desc, &vmx_seg);
> + vmx_write_segment_descriptor(cpu, &vmx_seg, REG_SEG_TR);
> +
> + store_regs(cpu);
> +
> + hv_vcpu_invalidate_tlb(cpu->hvf_fd);
> + hv_vcpu_flush(cpu->hvf_fd);
> +}
> +
> +static void hvf_handle_interrupt(CPUState * cpu, int mask)
> +{
> + cpu->interrupt_request |= mask;
> + if (!qemu_cpu_is_self(cpu)) {
> + qemu_cpu_kick(cpu);
> + }
> +}
> +
> +void hvf_handle_io(CPUArchState * env, uint16_t port, void* buffer,
> + int direction, int size, int count)
> +{
> + int i;
> + uint8_t *ptr = buffer;
> +
> + for (i = 0; i < count; i++) {
> + address_space_rw(&address_space_io, port, MEMTXATTRS_UNSPECIFIED,
> + ptr, size,
> + direction);
> + ptr += size;
> + }
> +}
> +//
> +// TODO: synchronize vcpu state
> +void __hvf_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg)
> +{
> + CPUState *cpu_state = cpu;//(CPUState *)data;
> + if (cpu_state->hvf_vcpu_dirty == 0)
> + hvf_get_registers(cpu_state);
> +
> + cpu_state->hvf_vcpu_dirty = 1;
> +}
> +
> +void hvf_cpu_synchronize_state(CPUState *cpu_state)
> +{
> + if (cpu_state->hvf_vcpu_dirty == 0)
> + run_on_cpu(cpu_state, __hvf_cpu_synchronize_state, RUN_ON_CPU_NULL);
> +}
> +
> +void __hvf_cpu_synchronize_post_reset(CPUState *cpu, run_on_cpu_data arg)
> +{
> + CPUState *cpu_state = cpu;
> + hvf_put_registers(cpu_state);
> + cpu_state->hvf_vcpu_dirty = false;
> +}
> +
> +void hvf_cpu_synchronize_post_reset(CPUState *cpu_state)
> +{
> + run_on_cpu(cpu_state, __hvf_cpu_synchronize_post_reset, RUN_ON_CPU_NULL);
> +}
> +
> +void _hvf_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg)
> +{
> + CPUState *cpu_state = cpu;
> + hvf_put_registers(cpu_state);
> + cpu_state->hvf_vcpu_dirty = false;
> +}
> +
> +void hvf_cpu_synchronize_post_init(CPUState *cpu_state)
> +{
> + run_on_cpu(cpu_state, _hvf_cpu_synchronize_post_init, RUN_ON_CPU_NULL);
> +}
> +
> +// TODO: ept fault handlig
> +void vmx_clear_int_window_exiting(CPUState *cpu);
> +static bool ept_emulation_fault(uint64_t ept_qual)
> +{
> + int read, write;
> +
> + /* EPT fault on an instruction fetch doesn't make sense here */
> + if (ept_qual & EPT_VIOLATION_INST_FETCH)
> + return false;
> +
> + /* EPT fault must be a read fault or a write fault */
> + read = ept_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
> + write = ept_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
> + if ((read | write) == 0)
> + return false;
> +
> + /*
> + * The EPT violation must have been caused by accessing a
> + * guest-physical address that is a translation of a guest-linear
> + * address.
> + */
> + if ((ept_qual & EPT_VIOLATION_GLA_VALID) == 0 ||
> + (ept_qual & EPT_VIOLATION_XLAT_VALID) == 0) {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static void hvf_region_add(MemoryListener * listener,
> + MemoryRegionSection * section)
> +{
> + hvf_set_phys_mem(section, true);
> +}
> +
> +static void hvf_region_del(MemoryListener * listener,
> + MemoryRegionSection * section)
> +{
> + hvf_set_phys_mem(section, false);
> +}
> +
> +static MemoryListener hvf_memory_listener = {
> + .priority = 10,
> + .region_add = hvf_region_add,
> + .region_del = hvf_region_del,
> +};
> +
> +static MemoryListener hvf_io_listener = {
> + .priority = 10,
> +};
> +
> +void vmx_reset_vcpu(CPUState *cpu) {
> +
> + wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, 0);
> + macvm_set_cr0(cpu->hvf_fd, 0x60000010);
> +
> + wvmcs(cpu->hvf_fd, VMCS_CR4_MASK, CR4_VMXE_MASK);
> + wvmcs(cpu->hvf_fd, VMCS_CR4_SHADOW, 0x0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CR4, CR4_VMXE_MASK);
> +
> + // set VMCS guest state fields
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_SELECTOR, 0xf000);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_LIMIT, 0xffff);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_ACCESS_RIGHTS, 0x9b);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CS_BASE, 0xffff0000);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_LIMIT, 0xffff);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_ACCESS_RIGHTS, 0x93);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_DS_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_LIMIT, 0xffff);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_ACCESS_RIGHTS, 0x93);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_ES_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_LIMIT, 0xffff);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_ACCESS_RIGHTS, 0x93);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_LIMIT, 0xffff);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_ACCESS_RIGHTS, 0x93);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_LIMIT, 0xffff);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_ACCESS_RIGHTS, 0x93);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_SS_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_ACCESS_RIGHTS, 0x10000);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_SELECTOR, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_LIMIT, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_ACCESS_RIGHTS, 0x83);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_TR_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE, 0);
> +
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT, 0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE, 0);
> +
> + //wvmcs(cpu->hvf_fd, VMCS_GUEST_CR2, 0x0);
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_CR3, 0x0);
> +
> + wreg(cpu->hvf_fd, HV_X86_RIP, 0xfff0);
> + wreg(cpu->hvf_fd, HV_X86_RDX, 0x623);
> + wreg(cpu->hvf_fd, HV_X86_RFLAGS, 0x2);
> + wreg(cpu->hvf_fd, HV_X86_RSP, 0x0);
> + wreg(cpu->hvf_fd, HV_X86_RAX, 0x0);
> + wreg(cpu->hvf_fd, HV_X86_RBX, 0x0);
> + wreg(cpu->hvf_fd, HV_X86_RCX, 0x0);
> + wreg(cpu->hvf_fd, HV_X86_RSI, 0x0);
> + wreg(cpu->hvf_fd, HV_X86_RDI, 0x0);
> + wreg(cpu->hvf_fd, HV_X86_RBP, 0x0);
> +
> + for (int i = 0; i < 8; i++)
> + wreg(cpu->hvf_fd, HV_X86_R8+i, 0x0);
> +
> + hv_vm_sync_tsc(0);
> + cpu->halted = 0;
> + hv_vcpu_invalidate_tlb(cpu->hvf_fd);
> + hv_vcpu_flush(cpu->hvf_fd);
> +}
> +
> +void hvf_vcpu_destroy(CPUState* cpu)
> +{
> + hv_return_t ret = hv_vcpu_destroy((hv_vcpuid_t)cpu->hvf_fd);
> + assert_hvf_ok(ret);
> +}
> +
> +static void dummy_signal(int sig)
> +{
> +}
> +
> +int hvf_init_vcpu(CPUState * cpu) {
> +
> + X86CPU *x86cpu;
> +
> + // init cpu signals
> + sigset_t set;
> + struct sigaction sigact;
> +
> + memset(&sigact, 0, sizeof(sigact));
> + sigact.sa_handler = dummy_signal;
> + sigaction(SIG_IPI, &sigact, NULL);
> +
> + pthread_sigmask(SIG_BLOCK, NULL, &set);
> + sigdelset(&set, SIG_IPI);
> +
> + int r;
> + init_emu(cpu);
> + init_decoder(cpu);
> + init_cpuid(cpu);
> +
> + cpu->hvf_caps = (struct hvf_vcpu_caps*)g_malloc0(sizeof(struct hvf_vcpu_caps));
> + cpu->hvf_x86 = (struct hvf_x86_state*)g_malloc0(sizeof(struct hvf_x86_state));
> +
> + r = hv_vcpu_create((hv_vcpuid_t *)&cpu->hvf_fd, HV_VCPU_DEFAULT);
> + cpu->hvf_vcpu_dirty = 1;
> + assert_hvf_ok(r);
> +
> + if (hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &cpu->hvf_caps->vmx_cap_pinbased))
> + abort();
> + if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cpu->hvf_caps->vmx_cap_procbased))
> + abort();
> + if (hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cpu->hvf_caps->vmx_cap_procbased2))
> + abort();
> + if (hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cpu->hvf_caps->vmx_cap_entry))
> + abort();
> +
> + /* set VMCS control fields */
> + wvmcs(cpu->hvf_fd, VMCS_PIN_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_pinbased, 0));
> + wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_procbased,
> + VMCS_PRI_PROC_BASED_CTLS_HLT |
> + VMCS_PRI_PROC_BASED_CTLS_MWAIT |
> + VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET |
> + VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW) |
> + VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL);
> + wvmcs(cpu->hvf_fd, VMCS_SEC_PROC_BASED_CTLS,
> + cap2ctrl(cpu->hvf_caps->vmx_cap_procbased2,VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES));
> +
> + wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, cap2ctrl(cpu->hvf_caps->vmx_cap_entry, 0));
> + wvmcs(cpu->hvf_fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */
> +
> + wvmcs(cpu->hvf_fd, VMCS_TPR_THRESHOLD, 0);
> +
> + vmx_reset_vcpu(cpu);
> +
> + x86cpu = X86_CPU(cpu);
> + x86cpu->env.kvm_xsave_buf = qemu_memalign(4096, sizeof(struct hvf_xsave_buf));
> +
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_STAR, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_LSTAR, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_CSTAR, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FMASK, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_FSBASE, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_GSBASE, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_KERNELGSBASE, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_TSC_AUX, 1);
> + //hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_TSC, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_CS, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_EIP, 1);
> + hv_vcpu_enable_native_msr(cpu->hvf_fd, MSR_IA32_SYSENTER_ESP, 1);
> +
> + return 0;
> +}
> +
> +int hvf_enabled() { return !hvf_disabled; }
> +void hvf_disable(int shouldDisable) {
> + hvf_disabled = shouldDisable;
> +}
> +
> +int hvf_vcpu_exec(CPUState* cpu) {
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + CPUX86State *env = &x86_cpu->env;
> + int ret = 0;
> + uint64_t rip = 0;
> +
> + cpu->halted = 0;
> +
> + if (hvf_process_events(cpu)) {
> + return EXCP_HLT;
> + }
> +
> + do {
> + if (cpu->hvf_vcpu_dirty) {
> + hvf_put_registers(cpu);
> + cpu->hvf_vcpu_dirty = false;
> + }
> +
> + cpu->hvf_x86->interruptable =
> + !(rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
> + (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
> +
> + hvf_inject_interrupts(cpu);
> + vmx_update_tpr(cpu);
> +
> +
> + qemu_mutex_unlock_iothread();
> + if (!cpu_is_bsp(X86_CPU(cpu)) && cpu->halted) {
> + qemu_mutex_lock_iothread();
> + return EXCP_HLT;
> + }
> +
> + hv_return_t r = hv_vcpu_run(cpu->hvf_fd);
> + assert_hvf_ok(r);
> +
> + /* handle VMEXIT */
> + uint64_t exit_reason = rvmcs(cpu->hvf_fd, VMCS_EXIT_REASON);
> + uint64_t exit_qual = rvmcs(cpu->hvf_fd, VMCS_EXIT_QUALIFICATION);
> + uint32_t ins_len = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
> + uint64_t idtvec_info = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
> + rip = rreg(cpu->hvf_fd, HV_X86_RIP);
> + RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
> + env->eflags = RFLAGS(cpu);
> +
> + trace_hvf_vm_exit(exit_reason, exit_qual);
> +
> + qemu_mutex_lock_iothread();
> +
> + update_apic_tpr(cpu);
> + current_cpu = cpu;
> +
> + ret = 0;
> + switch (exit_reason) {
> + case EXIT_REASON_HLT: {
> + macvm_set_rip(cpu, rip + ins_len);
> + if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu) & IF_MASK))
> + && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) &&
> + !(idtvec_info & VMCS_IDT_VEC_VALID)) {
> + cpu->halted = 1;
> + ret = EXCP_HLT;
> + }
> + ret = EXCP_INTERRUPT;
> + break;
> + }
> + case EXIT_REASON_MWAIT: {
> + ret = EXCP_INTERRUPT;
> + break;
> + }
> + /* Need to check if MMIO or unmmaped fault */
> + case EXIT_REASON_EPT_FAULT:
> + {
> + hvf_slot *slot;
> + addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
> + trace_hvf_vm_exit_gpa(gpa);
> +
> + if ((idtvec_info & VMCS_IDT_VEC_VALID) == 0 && (exit_qual & EXIT_QUAL_NMIUDTI) != 0)
> + vmx_set_nmi_blocking(cpu);
> +
> + slot = hvf_find_overlap_slot(gpa, gpa);
> + // mmio
> + if (ept_emulation_fault(exit_qual) && !slot) {
> + struct x86_decode decode;
> +
> + load_regs(cpu);
> + cpu->hvf_x86->fetch_rip = rip;
> +
> + decode_instruction(cpu, &decode);
> + exec_instruction(cpu, &decode);
> + store_regs(cpu);
> + break;
> + }
> +#ifdef DIRTY_VGA_TRACKING
> + if (slot) {
> + bool read = exit_qual & EPT_VIOLATION_DATA_READ ? 1 : 0;
> + bool write = exit_qual & EPT_VIOLATION_DATA_WRITE ? 1 : 0;
> + if (!read && !write)
> + break;
> + int flags = HV_MEMORY_READ | HV_MEMORY_EXEC;
> + if (write) flags |= HV_MEMORY_WRITE;
> +
> + pthread_rwlock_wrlock(&mem_lock);
> + if (write)
> + mark_slot_page_dirty(slot, gpa);
> + hv_vm_protect(gpa & ~0xfff, 4096, flags);
> + pthread_rwlock_unlock(&mem_lock);
> + }
> +#endif
> + break;
> + }
> + case EXIT_REASON_INOUT:
> + {
> + uint32_t in = (exit_qual & 8) != 0;
> + uint32_t size = (exit_qual & 7) + 1;
> + uint32_t string = (exit_qual & 16) != 0;
> + uint32_t port = exit_qual >> 16;
> + //uint32_t rep = (exit_qual & 0x20) != 0;
> +
> +#if 1
> + if (!string && in) {
> + uint64_t val = 0;
> + load_regs(cpu);
> + hvf_handle_io(env, port, &val, 0, size, 1);
> + if (size == 1) AL(cpu) = val;
> + else if (size == 2) AX(cpu) = val;
> + else if (size == 4) RAX(cpu) = (uint32_t)val;
> + else VM_PANIC("size");
> + RIP(cpu) += ins_len;
> + store_regs(cpu);
> + break;
> + } else if (!string && !in) {
> + RAX(cpu) = rreg(cpu->hvf_fd, HV_X86_RAX);
> + hvf_handle_io(env, port, &RAX(cpu), 1, size, 1);
> + macvm_set_rip(cpu, rip + ins_len);
> + break;
> + }
> +#endif
> + struct x86_decode decode;
> +
> + load_regs(cpu);
> + cpu->hvf_x86->fetch_rip = rip;
> +
> + decode_instruction(cpu, &decode);
> + VM_PANIC_ON(ins_len != decode.len);
> + exec_instruction(cpu, &decode);
> + store_regs(cpu);
> +
> + break;
> + }
> + case EXIT_REASON_CPUID: {
> + uint32_t rax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
> + uint32_t rbx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RBX);
> + uint32_t rcx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
> + uint32_t rdx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
> +
> + get_cpuid_func(cpu, rax, rcx, &rax, &rbx, &rcx, &rdx);
> +
> + wreg(cpu->hvf_fd, HV_X86_RAX, rax);
> + wreg(cpu->hvf_fd, HV_X86_RBX, rbx);
> + wreg(cpu->hvf_fd, HV_X86_RCX, rcx);
> + wreg(cpu->hvf_fd, HV_X86_RDX, rdx);
> +
> + macvm_set_rip(cpu, rip + ins_len);
> + break;
> + }
> + case EXIT_REASON_XSETBV: {
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + CPUX86State *env = &x86_cpu->env;
> + uint32_t eax = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RAX);
> + uint32_t ecx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RCX);
> + uint32_t edx = (uint32_t)rreg(cpu->hvf_fd, HV_X86_RDX);
> +
> + if (ecx) {
> + macvm_set_rip(cpu, rip + ins_len);
> + break;
> + }
> + env->xcr0 = ((uint64_t)edx << 32) | eax;
> + wreg(cpu->hvf_fd, HV_X86_XCR0, env->xcr0 | 1);
> + macvm_set_rip(cpu, rip + ins_len);
> + break;
> + }
> + case EXIT_REASON_INTR_WINDOW:
> + vmx_clear_int_window_exiting(cpu);
> + ret = EXCP_INTERRUPT;
> + break;
> + case EXIT_REASON_NMI_WINDOW:
> + vmx_clear_nmi_window_exiting(cpu);
> + ret = EXCP_INTERRUPT;
> + break;
> + case EXIT_REASON_EXT_INTR:
> + /* force exit and allow io handling */
> + ret = EXCP_INTERRUPT;
> + break;
> + case EXIT_REASON_RDMSR:
> + case EXIT_REASON_WRMSR:
> + {
> + load_regs(cpu);
> + if (exit_reason == EXIT_REASON_RDMSR)
> + simulate_rdmsr(cpu);
> + else
> + simulate_wrmsr(cpu);
> + RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
> + store_regs(cpu);
> + break;
> + }
> + case EXIT_REASON_CR_ACCESS: {
> + int cr;
> + int reg;
> +
> + load_regs(cpu);
> + cr = exit_qual & 15;
> + reg = (exit_qual >> 8) & 15;
> +
> + switch (cr) {
> + case 0x0: {
> + macvm_set_cr0(cpu->hvf_fd, RRX(cpu, reg));
> + break;
> + }
> + case 4: {
> + macvm_set_cr4(cpu->hvf_fd, RRX(cpu, reg));
> + break;
> + }
> + case 8: {
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + if (exit_qual & 0x10) {
> + RRX(cpu, reg) = cpu_get_apic_tpr(x86_cpu->apic_state);
> + }
> + else {
> + int tpr = RRX(cpu, reg);
> + cpu_set_apic_tpr(x86_cpu->apic_state, tpr);
> + ret = EXCP_INTERRUPT;
> + }
> + break;
> + }
> + default:
> + fprintf(stderr, "Unrecognized CR %d\n", cr);
> + abort();
> + }
> + RIP(cpu) += ins_len;
> + store_regs(cpu);
> + break;
> + }
> + case EXIT_REASON_APIC_ACCESS: { // TODO
> + struct x86_decode decode;
> +
> + load_regs(cpu);
> + cpu->hvf_x86->fetch_rip = rip;
> +
> + decode_instruction(cpu, &decode);
> + exec_instruction(cpu, &decode);
> + store_regs(cpu);
> + break;
> + }
> + case EXIT_REASON_TPR: {
> + ret = 1;
> + break;
> + }
> + case EXIT_REASON_TASK_SWITCH: {
> + uint64_t vinfo = rvmcs(cpu->hvf_fd, VMCS_IDT_VECTORING_INFO);
> + x68_segment_selector sel = {.sel = exit_qual & 0xffff};
> + vmx_handle_task_switch(cpu, sel, (exit_qual >> 30) & 0x3,
> + vinfo & VMCS_INTR_VALID, vinfo & VECTORING_INFO_VECTOR_MASK, vinfo & VMCS_INTR_T_MASK);
> + break;
> + }
> + case EXIT_REASON_TRIPLE_FAULT: {
> + //addr_t gpa = rvmcs(cpu->hvf_fd, VMCS_GUEST_PHYSICAL_ADDRESS);
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + usleep(1000 * 100);
> + ret = EXCP_INTERRUPT;
> + break;
> + }
> + case EXIT_REASON_RDPMC:
> + wreg(cpu->hvf_fd, HV_X86_RAX, 0);
> + wreg(cpu->hvf_fd, HV_X86_RDX, 0);
> + macvm_set_rip(cpu, rip + ins_len);
> + break;
> + case VMX_REASON_VMCALL:
> + // TODO: maybe just take this out?
> + // if (g_hypervisor_iface) {
> + // load_regs(cpu);
> + // g_hypervisor_iface->hypercall_handler(cpu);
> + // RIP(cpu) += rvmcs(cpu->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
> + // store_regs(cpu);
> + // }
> + break;
> + default:
> + fprintf(stderr, "%llx: unhandled exit %llx\n", rip, exit_reason);
> + }
> + } while (ret == 0);
> +
> + return ret;
> +}
> +
> +static bool hvf_allowed;
> +
> +static int hvf_accel_init(MachineState *ms)
> +{
> + int x;
> + hv_return_t ret;
> + HVFState *s;
> +
> + ret = hv_vm_create(HV_VM_DEFAULT);
> + assert_hvf_ok(ret);
> +
> + s = (HVFState *)g_malloc0(sizeof(HVFState));
> +
> + s->num_slots = 32;
> + for (x = 0; x < s->num_slots; ++x) {
> + s->slots[x].size = 0;
> + s->slots[x].slot_id = x;
> + }
> +
> + hvf_state = s;
> + cpu_interrupt_handler = hvf_handle_interrupt;
> + memory_listener_register(&hvf_memory_listener, &address_space_memory);
> + memory_listener_register(&hvf_io_listener, &address_space_io);
> + return 0;
> +}
> +
> +static void hvf_accel_class_init(ObjectClass *oc, void *data)
> +{
> + AccelClass *ac = ACCEL_CLASS(oc);
> + ac->name = "HVF";
> + ac->init_machine = hvf_accel_init;
> + ac->allowed = &hvf_allowed;
> +}
> +
> +static const TypeInfo hvf_accel_type = {
> + .name = TYPE_HVF_ACCEL,
> + .parent = TYPE_ACCEL,
> + .class_init = hvf_accel_class_init,
> +};
> +
> +static void hvf_type_init(void)
> +{
> + type_register_static(&hvf_accel_type);
> +}
> +
> +type_init(hvf_type_init);
> diff --git a/target/i386/hvf-i386.h b/target/i386/hvf-i386.h
> new file mode 100644
> index 0000000000..f3f958058a
> --- /dev/null
> +++ b/target/i386/hvf-i386.h
> @@ -0,0 +1,48 @@
> +/*
> + * QEMU Hypervisor.framework (HVF) support
> + *
> + * Copyright 2017 Google Inc
> + *
> + * Adapted from target-i386/hax-i386.h:
> + * Copyright (c) 2011 Intel Corporation
> + * Written by:
> + * Jiang Yunhong<yunhong.jiang@intel.com>
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + *
> + */
> +
> +#ifndef _HVF_I386_H
> +#define _HVF_I386_H
> +
> +#include "sysemu/hvf.h"
> +#include "cpu.h"
> +#include "hvf-utils/x86.h"
> +
> +#define HVF_MAX_VCPU 0x10
> +#define MAX_VM_ID 0x40
> +#define MAX_VCPU_ID 0x40
> +
> +extern struct hvf_state hvf_global;
> +
> +struct hvf_vm {
> + int id;
> + struct hvf_vcpu_state *vcpus[HVF_MAX_VCPU];
> +};
> +
> +struct hvf_state {
> + uint32_t version;
> + struct hvf_vm *vm;
> + uint64_t mem_quota;
> +};
> +
> +#ifdef NEED_CPU_H
> +/* Functions exported to host specific mode */
> +
> +/* Host specific functions */
> +int hvf_inject_interrupt(CPUArchState * env, int vector);
> +int hvf_vcpu_run(struct hvf_vcpu_state *vcpu);
> +#endif
> +
> +#endif
> diff --git a/target/i386/hvf-utils/Makefile.objs b/target/i386/hvf-utils/Makefile.objs
> new file mode 100644
> index 0000000000..7df219ad9c
> --- /dev/null
> +++ b/target/i386/hvf-utils/Makefile.objs
> @@ -0,0 +1 @@
> +obj-y += x86.o x86_cpuid.o x86_decode.o x86_descr.o x86_emu.o x86_flags.o x86_mmu.o x86hvf.o
> diff --git a/target/i386/hvf-utils/README.md b/target/i386/hvf-utils/README.md
> new file mode 100644
> index 0000000000..0d27a0d52b
> --- /dev/null
> +++ b/target/i386/hvf-utils/README.md
> @@ -0,0 +1,7 @@
> +# OS X Hypervisor.framework support in QEMU
> +
> +These sources (and ../hvf-all.c) are adapted from Veertu Inc's vdhh (Veertu Desktop Hosted Hypervisor) (last known location: https://github.com/veertuinc/vdhh) with some minor changes, the most significant of which were:
> +
> +1. Adapt to our current QEMU's `CPUState` structure and `address_space_rw` API; many struct members have been moved around (emulated x86 state, kvm_xsave_buf) due to historical differences + QEMU needing to handle more emulation targets.
> +2. Removal of `apic_page` and hyperv-related functionality.
> +3. More relaxed use of `qemu_mutex_lock_iothread`.
> diff --git a/target/i386/hvf-utils/vmcs.h b/target/i386/hvf-utils/vmcs.h
> new file mode 100644
> index 0000000000..6f7ccb361a
> --- /dev/null
> +++ b/target/i386/hvf-utils/vmcs.h
> @@ -0,0 +1,368 @@
> +/*-
> + * Copyright (c) 2011 NetApp, Inc.
> + * All rights reserved.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions
> + * are met:
> + * 1. Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * 2. Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + *
> + * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
> + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
> + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
> + * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
> + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
> + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
> + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
> + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
> + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
> + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
> + * SUCH DAMAGE.
> + *
> + * $FreeBSD$
> + */
> +
> +#ifndef _VMCS_H_
> +#define _VMCS_H_
> +
> +#include <Hypervisor/hv.h>
> +#include <Hypervisor/hv_vmx.h>
> +
> +#define VMCS_INITIAL 0xffffffffffffffff
> +
> +#define VMCS_IDENT(encoding) ((encoding) | 0x80000000)
> +/*
> + * VMCS field encodings from Appendix H, Intel Architecture Manual Vol3B.
> + */
> +#define VMCS_INVALID_ENCODING 0xffffffff
> +
> +/* 16-bit control fields */
> +#define VMCS_VPID 0x00000000
> +#define VMCS_PIR_VECTOR 0x00000002
> +
> +/* 16-bit guest-state fields */
> +#define VMCS_GUEST_ES_SELECTOR 0x00000800
> +#define VMCS_GUEST_CS_SELECTOR 0x00000802
> +#define VMCS_GUEST_SS_SELECTOR 0x00000804
> +#define VMCS_GUEST_DS_SELECTOR 0x00000806
> +#define VMCS_GUEST_FS_SELECTOR 0x00000808
> +#define VMCS_GUEST_GS_SELECTOR 0x0000080A
> +#define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
> +#define VMCS_GUEST_TR_SELECTOR 0x0000080E
> +#define VMCS_GUEST_INTR_STATUS 0x00000810
> +
> +/* 16-bit host-state fields */
> +#define VMCS_HOST_ES_SELECTOR 0x00000C00
> +#define VMCS_HOST_CS_SELECTOR 0x00000C02
> +#define VMCS_HOST_SS_SELECTOR 0x00000C04
> +#define VMCS_HOST_DS_SELECTOR 0x00000C06
> +#define VMCS_HOST_FS_SELECTOR 0x00000C08
> +#define VMCS_HOST_GS_SELECTOR 0x00000C0A
> +#define VMCS_HOST_TR_SELECTOR 0x00000C0C
> +
> +/* 64-bit control fields */
> +#define VMCS_IO_BITMAP_A 0x00002000
> +#define VMCS_IO_BITMAP_B 0x00002002
> +#define VMCS_MSR_BITMAP 0x00002004
> +#define VMCS_EXIT_MSR_STORE 0x00002006
> +#define VMCS_EXIT_MSR_LOAD 0x00002008
> +#define VMCS_ENTRY_MSR_LOAD 0x0000200A
> +#define VMCS_EXECUTIVE_VMCS 0x0000200C
> +#define VMCS_TSC_OFFSET 0x00002010
> +#define VMCS_VIRTUAL_APIC 0x00002012
> +#define VMCS_APIC_ACCESS 0x00002014
> +#define VMCS_PIR_DESC 0x00002016
> +#define VMCS_EPTP 0x0000201A
> +#define VMCS_EOI_EXIT0 0x0000201C
> +#define VMCS_EOI_EXIT1 0x0000201E
> +#define VMCS_EOI_EXIT2 0x00002020
> +#define VMCS_EOI_EXIT3 0x00002022
> +#define VMCS_EOI_EXIT(vector) (VMCS_EOI_EXIT0 + ((vector) / 64) * 2)
> +
> +/* 64-bit read-only fields */
> +#define VMCS_GUEST_PHYSICAL_ADDRESS 0x00002400
> +
> +/* 64-bit guest-state fields */
> +#define VMCS_LINK_POINTER 0x00002800
> +#define VMCS_GUEST_IA32_DEBUGCTL 0x00002802
> +#define VMCS_GUEST_IA32_PAT 0x00002804
> +#define VMCS_GUEST_IA32_EFER 0x00002806
> +#define VMCS_GUEST_IA32_PERF_GLOBAL_CTRL 0x00002808
> +#define VMCS_GUEST_PDPTE0 0x0000280A
> +#define VMCS_GUEST_PDPTE1 0x0000280C
> +#define VMCS_GUEST_PDPTE2 0x0000280E
> +#define VMCS_GUEST_PDPTE3 0x00002810
> +
> +/* 64-bit host-state fields */
> +#define VMCS_HOST_IA32_PAT 0x00002C00
> +#define VMCS_HOST_IA32_EFER 0x00002C02
> +#define VMCS_HOST_IA32_PERF_GLOBAL_CTRL 0x00002C04
> +
> +/* 32-bit control fields */
> +#define VMCS_PIN_BASED_CTLS 0x00004000
> +#define VMCS_PRI_PROC_BASED_CTLS 0x00004002
> +#define VMCS_EXCEPTION_BITMAP 0x00004004
> +#define VMCS_PF_ERROR_MASK 0x00004006
> +#define VMCS_PF_ERROR_MATCH 0x00004008
> +#define VMCS_CR3_TARGET_COUNT 0x0000400A
> +#define VMCS_EXIT_CTLS 0x0000400C
> +#define VMCS_EXIT_MSR_STORE_COUNT 0x0000400E
> +#define VMCS_EXIT_MSR_LOAD_COUNT 0x00004010
> +#define VMCS_ENTRY_CTLS 0x00004012
> +#define VMCS_ENTRY_MSR_LOAD_COUNT 0x00004014
> +#define VMCS_ENTRY_INTR_INFO 0x00004016
> +#define VMCS_ENTRY_EXCEPTION_ERROR 0x00004018
> +#define VMCS_ENTRY_INST_LENGTH 0x0000401A
> +#define VMCS_TPR_THRESHOLD 0x0000401C
> +#define VMCS_SEC_PROC_BASED_CTLS 0x0000401E
> +#define VMCS_PLE_GAP 0x00004020
> +#define VMCS_PLE_WINDOW 0x00004022
> +
> +/* 32-bit read-only data fields */
> +#define VMCS_INSTRUCTION_ERROR 0x00004400
> +#define VMCS_EXIT_REASON 0x00004402
> +#define VMCS_EXIT_INTR_INFO 0x00004404
> +#define VMCS_EXIT_INTR_ERRCODE 0x00004406
> +#define VMCS_IDT_VECTORING_INFO 0x00004408
> +#define VMCS_IDT_VECTORING_ERROR 0x0000440A
> +#define VMCS_EXIT_INSTRUCTION_LENGTH 0x0000440C
> +#define VMCS_EXIT_INSTRUCTION_INFO 0x0000440E
> +
> +/* 32-bit guest-state fields */
> +#define VMCS_GUEST_ES_LIMIT 0x00004800
> +#define VMCS_GUEST_CS_LIMIT 0x00004802
> +#define VMCS_GUEST_SS_LIMIT 0x00004804
> +#define VMCS_GUEST_DS_LIMIT 0x00004806
> +#define VMCS_GUEST_FS_LIMIT 0x00004808
> +#define VMCS_GUEST_GS_LIMIT 0x0000480A
> +#define VMCS_GUEST_LDTR_LIMIT 0x0000480C
> +#define VMCS_GUEST_TR_LIMIT 0x0000480E
> +#define VMCS_GUEST_GDTR_LIMIT 0x00004810
> +#define VMCS_GUEST_IDTR_LIMIT 0x00004812
> +#define VMCS_GUEST_ES_ACCESS_RIGHTS 0x00004814
> +#define VMCS_GUEST_CS_ACCESS_RIGHTS 0x00004816
> +#define VMCS_GUEST_SS_ACCESS_RIGHTS 0x00004818
> +#define VMCS_GUEST_DS_ACCESS_RIGHTS 0x0000481A
> +#define VMCS_GUEST_FS_ACCESS_RIGHTS 0x0000481C
> +#define VMCS_GUEST_GS_ACCESS_RIGHTS 0x0000481E
> +#define VMCS_GUEST_LDTR_ACCESS_RIGHTS 0x00004820
> +#define VMCS_GUEST_TR_ACCESS_RIGHTS 0x00004822
> +#define VMCS_GUEST_INTERRUPTIBILITY 0x00004824
> +#define VMCS_GUEST_ACTIVITY 0x00004826
> +#define VMCS_GUEST_SMBASE 0x00004828
> +#define VMCS_GUEST_IA32_SYSENTER_CS 0x0000482A
> +#define VMCS_PREEMPTION_TIMER_VALUE 0x0000482E
> +
> +/* 32-bit host state fields */
> +#define VMCS_HOST_IA32_SYSENTER_CS 0x00004C00
> +
> +/* Natural Width control fields */
> +#define VMCS_CR0_MASK 0x00006000
> +#define VMCS_CR4_MASK 0x00006002
> +#define VMCS_CR0_SHADOW 0x00006004
> +#define VMCS_CR4_SHADOW 0x00006006
> +#define VMCS_CR3_TARGET0 0x00006008
> +#define VMCS_CR3_TARGET1 0x0000600A
> +#define VMCS_CR3_TARGET2 0x0000600C
> +#define VMCS_CR3_TARGET3 0x0000600E
> +
> +/* Natural Width read-only fields */
> +#define VMCS_EXIT_QUALIFICATION 0x00006400
> +#define VMCS_IO_RCX 0x00006402
> +#define VMCS_IO_RSI 0x00006404
> +#define VMCS_IO_RDI 0x00006406
> +#define VMCS_IO_RIP 0x00006408
> +#define VMCS_GUEST_LINEAR_ADDRESS 0x0000640A
> +
> +/* Natural Width guest-state fields */
> +#define VMCS_GUEST_CR0 0x00006800
> +#define VMCS_GUEST_CR3 0x00006802
> +#define VMCS_GUEST_CR4 0x00006804
> +#define VMCS_GUEST_ES_BASE 0x00006806
> +#define VMCS_GUEST_CS_BASE 0x00006808
> +#define VMCS_GUEST_SS_BASE 0x0000680A
> +#define VMCS_GUEST_DS_BASE 0x0000680C
> +#define VMCS_GUEST_FS_BASE 0x0000680E
> +#define VMCS_GUEST_GS_BASE 0x00006810
> +#define VMCS_GUEST_LDTR_BASE 0x00006812
> +#define VMCS_GUEST_TR_BASE 0x00006814
> +#define VMCS_GUEST_GDTR_BASE 0x00006816
> +#define VMCS_GUEST_IDTR_BASE 0x00006818
> +#define VMCS_GUEST_DR7 0x0000681A
> +#define VMCS_GUEST_RSP 0x0000681C
> +#define VMCS_GUEST_RIP 0x0000681E
> +#define VMCS_GUEST_RFLAGS 0x00006820
> +#define VMCS_GUEST_PENDING_DBG_EXCEPTIONS 0x00006822
> +#define VMCS_GUEST_IA32_SYSENTER_ESP 0x00006824
> +#define VMCS_GUEST_IA32_SYSENTER_EIP 0x00006826
> +
> +/* Natural Width host-state fields */
> +#define VMCS_HOST_CR0 0x00006C00
> +#define VMCS_HOST_CR3 0x00006C02
> +#define VMCS_HOST_CR4 0x00006C04
> +#define VMCS_HOST_FS_BASE 0x00006C06
> +#define VMCS_HOST_GS_BASE 0x00006C08
> +#define VMCS_HOST_TR_BASE 0x00006C0A
> +#define VMCS_HOST_GDTR_BASE 0x00006C0C
> +#define VMCS_HOST_IDTR_BASE 0x00006C0E
> +#define VMCS_HOST_IA32_SYSENTER_ESP 0x00006C10
> +#define VMCS_HOST_IA32_SYSENTER_EIP 0x00006C12
> +#define VMCS_HOST_RSP 0x00006C14
> +#define VMCS_HOST_RIP 0x00006c16
> +
> +/*
> + * VM instruction error numbers
> + */
> +#define VMRESUME_WITH_NON_LAUNCHED_VMCS 5
> +
> +/*
> + * VMCS exit reasons
> + */
> +#define EXIT_REASON_EXCEPTION 0
> +#define EXIT_REASON_EXT_INTR 1
> +#define EXIT_REASON_TRIPLE_FAULT 2
> +#define EXIT_REASON_INIT 3
> +#define EXIT_REASON_SIPI 4
> +#define EXIT_REASON_IO_SMI 5
> +#define EXIT_REASON_SMI 6
> +#define EXIT_REASON_INTR_WINDOW 7
> +#define EXIT_REASON_NMI_WINDOW 8
> +#define EXIT_REASON_TASK_SWITCH 9
> +#define EXIT_REASON_CPUID 10
> +#define EXIT_REASON_GETSEC 11
> +#define EXIT_REASON_HLT 12
> +#define EXIT_REASON_INVD 13
> +#define EXIT_REASON_INVLPG 14
> +#define EXIT_REASON_RDPMC 15
> +#define EXIT_REASON_RDTSC 16
> +#define EXIT_REASON_RSM 17
> +#define EXIT_REASON_VMCALL 18
> +#define EXIT_REASON_VMCLEAR 19
> +#define EXIT_REASON_VMLAUNCH 20
> +#define EXIT_REASON_VMPTRLD 21
> +#define EXIT_REASON_VMPTRST 22
> +#define EXIT_REASON_VMREAD 23
> +#define EXIT_REASON_VMRESUME 24
> +#define EXIT_REASON_VMWRITE 25
> +#define EXIT_REASON_VMXOFF 26
> +#define EXIT_REASON_VMXON 27
> +#define EXIT_REASON_CR_ACCESS 28
> +#define EXIT_REASON_DR_ACCESS 29
> +#define EXIT_REASON_INOUT 30
> +#define EXIT_REASON_RDMSR 31
> +#define EXIT_REASON_WRMSR 32
> +#define EXIT_REASON_INVAL_VMCS 33
> +#define EXIT_REASON_INVAL_MSR 34
> +#define EXIT_REASON_MWAIT 36
> +#define EXIT_REASON_MTF 37
> +#define EXIT_REASON_MONITOR 39
> +#define EXIT_REASON_PAUSE 40
> +#define EXIT_REASON_MCE_DURING_ENTRY 41
> +#define EXIT_REASON_TPR 43
> +#define EXIT_REASON_APIC_ACCESS 44
> +#define EXIT_REASON_VIRTUALIZED_EOI 45
> +#define EXIT_REASON_GDTR_IDTR 46
> +#define EXIT_REASON_LDTR_TR 47
> +#define EXIT_REASON_EPT_FAULT 48
> +#define EXIT_REASON_EPT_MISCONFIG 49
> +#define EXIT_REASON_INVEPT 50
> +#define EXIT_REASON_RDTSCP 51
> +#define EXIT_REASON_VMX_PREEMPT 52
> +#define EXIT_REASON_INVVPID 53
> +#define EXIT_REASON_WBINVD 54
> +#define EXIT_REASON_XSETBV 55
> +#define EXIT_REASON_APIC_WRITE 56
> +
> +/*
> + * NMI unblocking due to IRET.
> + *
> + * Applies to VM-exits due to hardware exception or EPT fault.
> + */
> +#define EXIT_QUAL_NMIUDTI (1 << 12)
> +/*
> + * VMCS interrupt information fields
> + */
> +#define VMCS_INTR_VALID (1U << 31)
> +#define VMCS_INTR_T_MASK 0x700 /* Interruption-info type */
> +#define VMCS_INTR_T_HWINTR (0 << 8)
> +#define VMCS_INTR_T_NMI (2 << 8)
> +#define VMCS_INTR_T_HWEXCEPTION (3 << 8)
> +#define VMCS_INTR_T_SWINTR (4 << 8)
> +#define VMCS_INTR_T_PRIV_SWEXCEPTION (5 << 8)
> +#define VMCS_INTR_T_SWEXCEPTION (6 << 8)
> +#define VMCS_INTR_DEL_ERRCODE (1 << 11)
> +
> +/*
> + * VMCS IDT-Vectoring information fields
> + */
> +#define VMCS_IDT_VEC_VALID (1U << 31)
> +#define VMCS_IDT_VEC_TYPE 0x700
> +#define VMCS_IDT_VEC_ERRCODE_VALID (1U << 11)
> +#define VMCS_IDT_VEC_HWINTR (0 << 8)
> +#define VMCS_IDT_VEC_NMI (2 << 8)
> +#define VMCS_IDT_VEC_HWEXCEPTION (3 << 8)
> +#define VMCS_IDT_VEC_SWINTR (4 << 8)
> +
> +/*
> + * VMCS Guest interruptibility field
> + */
> +#define VMCS_INTERRUPTIBILITY_STI_BLOCKING (1 << 0)
> +#define VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING (1 << 1)
> +#define VMCS_INTERRUPTIBILITY_SMI_BLOCKING (1 << 2)
> +#define VMCS_INTERRUPTIBILITY_NMI_BLOCKING (1 << 3)
> +
> +/*
> + * Exit qualification for EXIT_REASON_INVAL_VMCS
> + */
> +#define EXIT_QUAL_NMI_WHILE_STI_BLOCKING 3
> +
> +/*
> + * Exit qualification for EPT violation
> + */
> +#define EPT_VIOLATION_DATA_READ (1UL << 0)
> +#define EPT_VIOLATION_DATA_WRITE (1UL << 1)
> +#define EPT_VIOLATION_INST_FETCH (1UL << 2)
> +#define EPT_VIOLATION_GPA_READABLE (1UL << 3)
> +#define EPT_VIOLATION_GPA_WRITEABLE (1UL << 4)
> +#define EPT_VIOLATION_GPA_EXECUTABLE (1UL << 5)
> +#define EPT_VIOLATION_GLA_VALID (1UL << 7)
> +#define EPT_VIOLATION_XLAT_VALID (1UL << 8)
> +
> +/*
> + * Exit qualification for APIC-access VM exit
> + */
> +#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
> +#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
> +
> +/*
> + * Exit qualification for APIC-write VM exit
> + */
> +#define APIC_WRITE_OFFSET(qual) ((qual) & 0xFFF)
> +
> +
> +#define VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING (1 << 2)
> +#define VMCS_PRI_PROC_BASED_CTLS_TSC_OFFSET (1 << 3)
> +#define VMCS_PRI_PROC_BASED_CTLS_HLT (1 << 7)
> +#define VMCS_PRI_PROC_BASED_CTLS_MWAIT (1 << 10)
> +#define VMCS_PRI_PROC_BASED_CTLS_TSC (1 << 12)
> +#define VMCS_PRI_PROC_BASED_CTLS_CR8_LOAD (1 << 19)
> +#define VMCS_PRI_PROC_BASED_CTLS_CR8_STORE (1 << 20)
> +#define VMCS_PRI_PROC_BASED_CTLS_TPR_SHADOW (1 << 21)
> +#define VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING (1 << 22)
> +#define VMCS_PRI_PROC_BASED_CTLS_SEC_CONTROL (1 << 31)
> +
> +#define VMCS_PRI_PROC_BASED2_CTLS_APIC_ACCESSES (1 << 0)
> +#define VMCS_PRI_PROC_BASED2_CTLS_X2APIC (1 << 4)
> +
> +enum task_switch_reason {
> + TSR_CALL,
> + TSR_IRET,
> + TSR_JMP,
> + TSR_IDT_GATE, /* task gate in IDT */
> +};
> +
> +#endif
> diff --git a/target/i386/hvf-utils/vmx.h b/target/i386/hvf-utils/vmx.h
> new file mode 100644
> index 0000000000..8a080e6777
> --- /dev/null
> +++ b/target/i386/hvf-utils/vmx.h
> @@ -0,0 +1,200 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + * Based on Veertu vddh/vmm/vmx.h
> + *
> + * Interfaces to Hypervisor.framework to read/write X86 registers and VMCS.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef VMX_H
> +#define VMX_H
> +
> +#include <stdint.h>
> +#include <Hypervisor/hv.h>
> +#include <Hypervisor/hv_vmx.h>
> +#include "vmcs.h"
> +#include "cpu.h"
> +#include "x86.h"
> +
> +#include "exec/address-spaces.h"
> +
> +static uint64_t inline rreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg)
> +{
> + uint64_t v;
> +
> + if (hv_vcpu_read_register(vcpu, reg, &v)) {
> + abort();
> + }
> +
> + return v;
> +}
> +
> +/* write GPR */
> +static void inline wreg(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t v)
> +{
> + if (hv_vcpu_write_register(vcpu, reg, v)) {
> + abort();
> + }
> +}
> +
> +/* read VMCS field */
> +static uint64_t inline rvmcs(hv_vcpuid_t vcpu, uint32_t field)
> +{
> + uint64_t v;
> +
> + hv_vmx_vcpu_read_vmcs(vcpu, field, &v);
> +
> + return v;
> +}
> +
> +/* write VMCS field */
> +static void inline wvmcs(hv_vcpuid_t vcpu, uint32_t field, uint64_t v)
> +{
> + hv_vmx_vcpu_write_vmcs(vcpu, field, v);
> +}
> +
> +/* desired control word constrained by hardware/hypervisor capabilities */
> +static uint64_t inline cap2ctrl(uint64_t cap, uint64_t ctrl)
> +{
> + return (ctrl | (cap & 0xffffffff)) & (cap >> 32);
> +}
> +
> +#define VM_ENTRY_GUEST_LMA (1LL << 9)
> +
> +#define AR_TYPE_ACCESSES_MASK 1
> +#define AR_TYPE_READABLE_MASK (1 << 1)
> +#define AR_TYPE_WRITEABLE_MASK (1 << 2)
> +#define AR_TYPE_CODE_MASK (1 << 3)
> +#define AR_TYPE_MASK 0x0f
> +#define AR_TYPE_BUSY_64_TSS 11
> +#define AR_TYPE_BUSY_32_TSS 11
> +#define AR_TYPE_BUSY_16_TSS 3
> +#define AR_TYPE_LDT 2
> +
> +static void enter_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
> +{
> + uint64_t entry_ctls;
> +
> + efer |= EFER_LMA;
> + wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
> + entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
> + wvmcs(vcpu, VMCS_ENTRY_CTLS, rvmcs(vcpu, VMCS_ENTRY_CTLS) | VM_ENTRY_GUEST_LMA);
> +
> + uint64_t guest_tr_ar = rvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS);
> + if ((efer & EFER_LME) && (guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
> + wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, (guest_tr_ar & ~AR_TYPE_MASK) | AR_TYPE_BUSY_64_TSS);
> + }
> +}
> +
> +static void exit_long_mode(hv_vcpuid_t vcpu, uint64_t cr0, uint64_t efer)
> +{
> + uint64_t entry_ctls;
> +
> + entry_ctls = rvmcs(vcpu, VMCS_ENTRY_CTLS);
> + wvmcs(vcpu, VMCS_ENTRY_CTLS, entry_ctls & ~VM_ENTRY_GUEST_LMA);
> +
> + efer &= ~EFER_LMA;
> + wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer);
> +}
> +
> +static void inline macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0)
> +{
> + int i;
> + uint64_t pdpte[4] = {0, 0, 0, 0};
> + uint64_t efer = rvmcs(vcpu, VMCS_GUEST_IA32_EFER);
> + uint64_t old_cr0 = rvmcs(vcpu, VMCS_GUEST_CR0);
> +
> + if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & EFER_LME))
> + address_space_rw(&address_space_memory, rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f,
> + MEMTXATTRS_UNSPECIFIED,
> + (uint8_t *)pdpte, 32, 0);
> +
> + for (i = 0; i < 4; i++)
> + wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]);
> +
> + wvmcs(vcpu, VMCS_CR0_MASK, CR0_CD | CR0_NE | CR0_PG);
> + wvmcs(vcpu, VMCS_CR0_SHADOW, cr0);
> +
> + cr0 &= ~CR0_CD;
> + wvmcs(vcpu, VMCS_GUEST_CR0, cr0 | CR0_NE| CR0_ET);
> +
> + if (efer & EFER_LME) {
> + if (!(old_cr0 & CR0_PG) && (cr0 & CR0_PG))
> + enter_long_mode(vcpu, cr0, efer);
> + if (/*(old_cr0 & CR0_PG) &&*/ !(cr0 & CR0_PG))
> + exit_long_mode(vcpu, cr0, efer);
> + }
> +
> + hv_vcpu_invalidate_tlb(vcpu);
> + hv_vcpu_flush(vcpu);
> +}
> +
> +static void inline macvm_set_cr4(hv_vcpuid_t vcpu, uint64_t cr4)
> +{
> + uint64_t guest_cr4 = cr4 | CR4_VMXE;
> +
> + wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4);
> + wvmcs(vcpu, VMCS_CR4_SHADOW, cr4);
> +
> + hv_vcpu_invalidate_tlb(vcpu);
> + hv_vcpu_flush(vcpu);
> +}
> +
> +static void inline macvm_set_rip(CPUState *cpu, uint64_t rip)
> +{
> + uint64_t val;
> +
> + /* BUG, should take considering overlap.. */
> + wreg(cpu->hvf_fd, HV_X86_RIP, rip);
> +
> + /* after moving forward in rip, we need to clean INTERRUPTABILITY */
> + val = rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
> + if (val & (VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING))
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY,
> + val & ~(VMCS_INTERRUPTIBILITY_STI_BLOCKING | VMCS_INTERRUPTIBILITY_MOVSS_BLOCKING));
> +}
> +
> +static void inline vmx_clear_nmi_blocking(CPUState *cpu)
> +{
> + uint32_t gi = (uint32_t) rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
> + gi &= ~VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
> +}
> +
> +static void inline vmx_set_nmi_blocking(CPUState *cpu)
> +{
> + uint32_t gi = (uint32_t)rvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY);
> + gi |= VMCS_INTERRUPTIBILITY_NMI_BLOCKING;
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY, gi);
> +}
> +
> +static void inline vmx_set_nmi_window_exiting(CPUState *cpu)
> +{
> + uint64_t val;
> + val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
> + wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
> +
> +}
> +
> +static void inline vmx_clear_nmi_window_exiting(CPUState *cpu)
> +{
> +
> + uint64_t val;
> + val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
> + wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_NMI_WINDOW_EXITING);
> +}
> +
> +#endif
> diff --git a/target/i386/hvf-utils/x86.c b/target/i386/hvf-utils/x86.c
> new file mode 100644
> index 0000000000..e3db2c9c8b
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86.c
> @@ -0,0 +1,174 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qemu-common.h"
> +#include "x86_decode.h"
> +#include "x86_emu.h"
> +#include "vmcs.h"
> +#include "vmx.h"
> +#include "x86_mmu.h"
> +#include "x86_descr.h"
> +
> +static uint32_t x86_segment_access_rights(struct x86_segment_descriptor *var)
> +{
> + uint32_t ar;
> +
> + if (!var->p) {
> + ar = 1 << 16;
> + return ar;
> + }
> +
> + ar = var->type & 15;
> + ar |= (var->s & 1) << 4;
> + ar |= (var->dpl & 3) << 5;
> + ar |= (var->p & 1) << 7;
> + ar |= (var->avl & 1) << 12;
> + ar |= (var->l & 1) << 13;
> + ar |= (var->db & 1) << 14;
> + ar |= (var->g & 1) << 15;
> + return ar;
> +}
> +
> +bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
> +{
> + addr_t base;
> + uint32_t limit;
> +
> + ZERO_INIT(*desc);
> + // valid gdt descriptors start from index 1
> + if (!sel.index && GDT_SEL == sel.ti)
> + return false;
> +
> + if (GDT_SEL == sel.ti) {
> + base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);
> + limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
> + } else {
> + base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);
> + limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);
> + }
> +
> + if (sel.index * 8 >= limit)
> + return false;
> +
> + vmx_read_mem(cpu, desc, base + sel.index * 8, sizeof(*desc));
> + return true;
> +}
> +
> +bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel)
> +{
> + addr_t base;
> + uint32_t limit;
> +
> + if (GDT_SEL == sel.ti) {
> + base = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_BASE);
> + limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
> + } else {
> + base = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_BASE);
> + limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_LDTR_LIMIT);
> + }
> +
> + if (sel.index * 8 >= limit) {
> + printf("%s: gdt limit\n", __FUNCTION__);
> + return false;
> + }
> + vmx_write_mem(cpu, base + sel.index * 8, desc, sizeof(*desc));
> + return true;
> +}
> +
> +bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate)
> +{
> + addr_t base = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_BASE);
> + uint32_t limit = rvmcs(cpu->hvf_fd, VMCS_GUEST_IDTR_LIMIT);
> +
> + ZERO_INIT(*idt_desc);
> + if (gate * 8 >= limit) {
> + printf("%s: idt limit\n", __FUNCTION__);
> + return false;
> + }
> +
> + vmx_read_mem(cpu, idt_desc, base + gate * 8, sizeof(*idt_desc));
> + return true;
> +}
> +
> +bool x86_is_protected(struct CPUState *cpu)
> +{
> + uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
> + return cr0 & CR0_PE;
> +}
> +
> +bool x86_is_real(struct CPUState *cpu)
> +{
> + return !x86_is_protected(cpu);
> +}
> +
> +bool x86_is_v8086(struct CPUState *cpu)
> +{
> + return (x86_is_protected(cpu) && (RFLAGS(cpu) & RFLAGS_VM));
> +}
> +
> +bool x86_is_long_mode(struct CPUState *cpu)
> +{
> + return rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER) & EFER_LMA;
> +}
> +
> +bool x86_is_long64_mode(struct CPUState *cpu)
> +{
> + struct vmx_segment desc;
> + vmx_read_segment_descriptor(cpu, &desc, REG_SEG_CS);
> +
> + return x86_is_long_mode(cpu) && ((desc.ar >> 13) & 1);
> +}
> +
> +bool x86_is_paging_mode(struct CPUState *cpu)
> +{
> + uint64_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
> + return cr0 & CR0_PG;
> +}
> +
> +bool x86_is_pae_enabled(struct CPUState *cpu)
> +{
> + uint64_t cr4 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR4);
> + return cr4 & CR4_PAE;
> +}
> +
> +addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg)
> +{
> + return vmx_read_segment_base(cpu, seg) + addr;
> +}
> +
> +addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg)
> +{
> + switch (size) {
> + case 2:
> + addr = (uint16_t)addr;
> + break;
> + case 4:
> + addr = (uint32_t)addr;
> + break;
> + default:
> + break;
> + }
> + return linear_addr(cpu, addr, seg);
> +}
> +
> +addr_t linear_rip(struct CPUState *cpu, addr_t rip)
> +{
> + return linear_addr(cpu, rip, REG_SEG_CS);
> +}
> diff --git a/target/i386/hvf-utils/x86.h b/target/i386/hvf-utils/x86.h
> new file mode 100644
> index 0000000000..5dffdd6568
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86.h
> @@ -0,0 +1,470 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Veertu Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#pragma once
> +
> +#include <sys/types.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <stdarg.h>
> +#include "qemu-common.h"
> +#include "x86_flags.h"
> +
> +// exceptions
> +typedef enum x86_exception {
> + EXCEPTION_DE, // divide error
> + EXCEPTION_DB, // debug fault
> + EXCEPTION_NMI, // non-maskable interrupt
> + EXCEPTION_BP, // breakpoint trap
> + EXCEPTION_OF, // overflow trap
> + EXCEPTION_BR, // boundary range exceeded fault
> + EXCEPTION_UD, // undefined opcode
> + EXCEPTION_NM, // device not available
> + EXCEPTION_DF, // double fault
> + EXCEPTION_RSVD, // not defined
> + EXCEPTION_TS, // invalid TSS fault
> + EXCEPTION_NP, // not present fault
> + EXCEPTION_GP, // general protection fault
> + EXCEPTION_PF, // page fault
> + EXCEPTION_RSVD2, // not defined
> +} x86_exception;
> +
> +// general purpose regs
> +typedef enum x86_reg_name {
> + REG_RAX = 0,
> + REG_RCX = 1,
> + REG_RDX = 2,
> + REG_RBX = 3,
> + REG_RSP = 4,
> + REG_RBP = 5,
> + REG_RSI = 6,
> + REG_RDI = 7,
> + REG_R8 = 8,
> + REG_R9 = 9,
> + REG_R10 = 10,
> + REG_R11 = 11,
> + REG_R12 = 12,
> + REG_R13 = 13,
> + REG_R14 = 14,
> + REG_R15 = 15,
> +} x86_reg_name;
> +
> +// segment regs
> +typedef enum x86_reg_segment {
> + REG_SEG_ES = 0,
> + REG_SEG_CS = 1,
> + REG_SEG_SS = 2,
> + REG_SEG_DS = 3,
> + REG_SEG_FS = 4,
> + REG_SEG_GS = 5,
> + REG_SEG_LDTR = 6,
> + REG_SEG_TR = 7,
> +} x86_reg_segment;
> +
> +typedef struct x86_register
> +{
> + union {
> + struct {
> + uint64_t rrx; // full 64 bit
> + };
> + struct {
> + uint32_t erx; // low 32 bit part
> + uint32_t hi32_unused1;
> + };
> + struct {
> + uint16_t rx; // low 16 bit part
> + uint16_t hi16_unused1;
> + uint32_t hi32_unused2;
> + };
> + struct {
> + uint8_t lx; // low 8 bit part
> + uint8_t hx; // high 8 bit
> + uint16_t hi16_unused2;
> + uint32_t hi32_unused3;
> + };
> + };
> +} __attribute__ ((__packed__)) x86_register;
> +
> +typedef enum x86_rflags {
> + RFLAGS_CF = (1L << 0),
> + RFLAGS_PF = (1L << 2),
> + RFLAGS_AF = (1L << 4),
> + RFLAGS_ZF = (1L << 6),
> + RFLAGS_SF = (1L << 7),
> + RFLAGS_TF = (1L << 8),
> + RFLAGS_IF = (1L << 9),
> + RFLAGS_DF = (1L << 10),
> + RFLAGS_OF = (1L << 11),
> + RFLAGS_IOPL = (3L << 12),
> + RFLAGS_NT = (1L << 14),
> + RFLAGS_RF = (1L << 16),
> + RFLAGS_VM = (1L << 17),
> + RFLAGS_AC = (1L << 18),
> + RFLAGS_VIF = (1L << 19),
> + RFLAGS_VIP = (1L << 20),
> + RFLAGS_ID = (1L << 21),
> +} x86_rflags;
> +
> +// rflags register
> +typedef struct x86_reg_flags {
> + union {
> + struct {
> + uint64_t rflags;
> + };
> + struct {
> + uint32_t eflags;
> + uint32_t hi32_unused1;
> + };
> + struct {
> + uint32_t cf:1;
> + uint32_t unused1:1;
> + uint32_t pf:1;
> + uint32_t unused2:1;
> + uint32_t af:1;
> + uint32_t unused3:1;
> + uint32_t zf:1;
> + uint32_t sf:1;
> + uint32_t tf:1;
> + uint32_t ief:1;
> + uint32_t df:1;
> + uint32_t of:1;
> + uint32_t iopl:2;
> + uint32_t nt:1;
> + uint32_t unused4:1;
> + uint32_t rf:1;
> + uint32_t vm:1;
> + uint32_t ac:1;
> + uint32_t vif:1;
> + uint32_t vip:1;
> + uint32_t id:1;
> + uint32_t unused5:10;
> + uint32_t hi32_unused2;
> + };
> + };
> +} __attribute__ ((__packed__)) x86_reg_flags;
> +
> +typedef enum x86_reg_efer {
> + EFER_SCE = (1L << 0),
> + EFER_LME = (1L << 8),
> + EFER_LMA = (1L << 10),
> + EFER_NXE = (1L << 11),
> + EFER_SVME = (1L << 12),
> + EFER_FXSR = (1L << 14),
> +} x86_reg_efer;
> +
> +typedef struct x86_efer {
> + uint64_t efer;
> +} __attribute__ ((__packed__)) x86_efer;
> +
> +typedef enum x86_reg_cr0 {
> + CR0_PE = (1L << 0),
> + CR0_MP = (1L << 1),
> + CR0_EM = (1L << 2),
> + CR0_TS = (1L << 3),
> + CR0_ET = (1L << 4),
> + CR0_NE = (1L << 5),
> + CR0_WP = (1L << 16),
> + CR0_AM = (1L << 18),
> + CR0_NW = (1L << 29),
> + CR0_CD = (1L << 30),
> + CR0_PG = (1L << 31),
> +} x86_reg_cr0;
> +
> +typedef enum x86_reg_cr4 {
> + CR4_VME = (1L << 0),
> + CR4_PVI = (1L << 1),
> + CR4_TSD = (1L << 2),
> + CR4_DE = (1L << 3),
> + CR4_PSE = (1L << 4),
> + CR4_PAE = (1L << 5),
> + CR4_MSE = (1L << 6),
> + CR4_PGE = (1L << 7),
> + CR4_PCE = (1L << 8),
> + CR4_OSFXSR = (1L << 9),
> + CR4_OSXMMEXCPT = (1L << 10),
> + CR4_VMXE = (1L << 13),
> + CR4_SMXE = (1L << 14),
> + CR4_FSGSBASE = (1L << 16),
> + CR4_PCIDE = (1L << 17),
> + CR4_OSXSAVE = (1L << 18),
> + CR4_SMEP = (1L << 20),
> +} x86_reg_cr4;
> +
> +// 16 bit Task State Segment
> +typedef struct x86_tss_segment16 {
> + uint16_t link;
> + uint16_t sp0;
> + uint16_t ss0;
> + uint32_t sp1;
> + uint16_t ss1;
> + uint32_t sp2;
> + uint16_t ss2;
> + uint16_t ip;
> + uint16_t flags;
> + uint16_t ax;
> + uint16_t cx;
> + uint16_t dx;
> + uint16_t bx;
> + uint16_t sp;
> + uint16_t bp;
> + uint16_t si;
> + uint16_t di;
> + uint16_t es;
> + uint16_t cs;
> + uint16_t ss;
> + uint16_t ds;
> + uint16_t ldtr;
> +} __attribute__((packed)) x86_tss_segment16;
> +
> +// 32 bit Task State Segment
> +typedef struct x86_tss_segment32
> +{
> + uint32_t prev_tss;
> + uint32_t esp0;
> + uint32_t ss0;
> + uint32_t esp1;
> + uint32_t ss1;
> + uint32_t esp2;
> + uint32_t ss2;
> + uint32_t cr3;
> + uint32_t eip;
> + uint32_t eflags;
> + uint32_t eax;
> + uint32_t ecx;
> + uint32_t edx;
> + uint32_t ebx;
> + uint32_t esp;
> + uint32_t ebp;
> + uint32_t esi;
> + uint32_t edi;
> + uint32_t es;
> + uint32_t cs;
> + uint32_t ss;
> + uint32_t ds;
> + uint32_t fs;
> + uint32_t gs;
> + uint32_t ldt;
> + uint16_t trap;
> + uint16_t iomap_base;
> +} __attribute__ ((__packed__)) x86_tss_segment32;
> +
> +// 64 bit Task State Segment
> +typedef struct x86_tss_segment64
> +{
> + uint32_t unused;
> + uint64_t rsp0;
> + uint64_t rsp1;
> + uint64_t rsp2;
> + uint64_t unused1;
> + uint64_t ist1;
> + uint64_t ist2;
> + uint64_t ist3;
> + uint64_t ist4;
> + uint64_t ist5;
> + uint64_t ist6;
> + uint64_t ist7;
> + uint64_t unused2;
> + uint16_t unused3;
> + uint16_t iomap_base;
> +} __attribute__ ((__packed__)) x86_tss_segment64;
> +
> +// segment descriptors
> +typedef struct x86_segment_descriptor {
> + uint64_t limit0:16;
> + uint64_t base0:16;
> + uint64_t base1:8;
> + uint64_t type:4;
> + uint64_t s:1;
> + uint64_t dpl:2;
> + uint64_t p:1;
> + uint64_t limit1:4;
> + uint64_t avl:1;
> + uint64_t l:1;
> + uint64_t db:1;
> + uint64_t g:1;
> + uint64_t base2:8;
> +} __attribute__ ((__packed__)) x86_segment_descriptor;
> +
> +static inline uint32_t x86_segment_base(x86_segment_descriptor *desc)
> +{
> + return (uint32_t)((desc->base2 << 24) | (desc->base1 << 16) | desc->base0);
> +}
> +
> +static inline void x86_set_segment_base(x86_segment_descriptor *desc, uint32_t base)
> +{
> + desc->base2 = base >> 24;
> + desc->base1 = (base >> 16) & 0xff;
> + desc->base0 = base & 0xffff;
> +}
> +
> +static inline uint32_t x86_segment_limit(x86_segment_descriptor *desc)
> +{
> + uint32_t limit = (uint32_t)((desc->limit1 << 16) | desc->limit0);
> + if (desc->g)
> + return (limit << 12) | 0xfff;
> + return limit;
> +}
> +
> +static inline void x86_set_segment_limit(x86_segment_descriptor *desc, uint32_t limit)
> +{
> + desc->limit0 = limit & 0xffff;
> + desc->limit1 = limit >> 16;
> +}
> +
> +typedef struct x86_call_gate {
> + uint64_t offset0:16;
> + uint64_t selector:16;
> + uint64_t param_count:4;
> + uint64_t reserved:3;
> + uint64_t type:4;
> + uint64_t dpl:1;
> + uint64_t p:1;
> + uint64_t offset1:16;
> +} __attribute__ ((__packed__)) x86_call_gate;
> +
> +static inline uint32_t x86_call_gate_offset(x86_call_gate *gate)
> +{
> + return (uint32_t)((gate->offset1 << 16) | gate->offset0);
> +}
> +
> +#define LDT_SEL 0
> +#define GDT_SEL 1
> +
> +typedef struct x68_segment_selector {
> + union {
> + uint16_t sel;
> + struct {
> + uint16_t rpl:3;
> + uint16_t ti:1;
> + uint16_t index:12;
> + };
> + };
> +} __attribute__ ((__packed__)) x68_segment_selector;
> +
> +// Definition of hvf_x86_state is here
> +struct hvf_x86_state {
> + int hlt;
> + uint64_t init_tsc;
> +
> + int interruptable;
> + uint64_t exp_rip;
> + uint64_t fetch_rip;
> + uint64_t rip;
> + struct x86_register regs[16];
> + struct x86_reg_flags rflags;
> + struct lazy_flags lflags;
> + struct x86_efer efer;
> + uint8_t mmio_buf[4096];
> + uint8_t* apic_page;
> +};
> +
> +/*
> +* hvf xsave area
> +*/
> +struct hvf_xsave_buf {
> + uint32_t data[1024];
> +};
> +
> +// useful register access macros
> +#define RIP(cpu) (cpu->hvf_x86->rip)
> +#define EIP(cpu) ((uint32_t)cpu->hvf_x86->rip)
> +#define RFLAGS(cpu) (cpu->hvf_x86->rflags.rflags)
> +#define EFLAGS(cpu) (cpu->hvf_x86->rflags.eflags)
> +
> +#define RRX(cpu, reg) (cpu->hvf_x86->regs[reg].rrx)
> +#define RAX(cpu) RRX(cpu, REG_RAX)
> +#define RCX(cpu) RRX(cpu, REG_RCX)
> +#define RDX(cpu) RRX(cpu, REG_RDX)
> +#define RBX(cpu) RRX(cpu, REG_RBX)
> +#define RSP(cpu) RRX(cpu, REG_RSP)
> +#define RBP(cpu) RRX(cpu, REG_RBP)
> +#define RSI(cpu) RRX(cpu, REG_RSI)
> +#define RDI(cpu) RRX(cpu, REG_RDI)
> +#define R8(cpu) RRX(cpu, REG_R8)
> +#define R9(cpu) RRX(cpu, REG_R9)
> +#define R10(cpu) RRX(cpu, REG_R10)
> +#define R11(cpu) RRX(cpu, REG_R11)
> +#define R12(cpu) RRX(cpu, REG_R12)
> +#define R13(cpu) RRX(cpu, REG_R13)
> +#define R14(cpu) RRX(cpu, REG_R14)
> +#define R15(cpu) RRX(cpu, REG_R15)
> +
> +#define ERX(cpu, reg) (cpu->hvf_x86->regs[reg].erx)
> +#define EAX(cpu) ERX(cpu, REG_RAX)
> +#define ECX(cpu) ERX(cpu, REG_RCX)
> +#define EDX(cpu) ERX(cpu, REG_RDX)
> +#define EBX(cpu) ERX(cpu, REG_RBX)
> +#define ESP(cpu) ERX(cpu, REG_RSP)
> +#define EBP(cpu) ERX(cpu, REG_RBP)
> +#define ESI(cpu) ERX(cpu, REG_RSI)
> +#define EDI(cpu) ERX(cpu, REG_RDI)
> +
> +#define RX(cpu, reg) (cpu->hvf_x86->regs[reg].rx)
> +#define AX(cpu) RX(cpu, REG_RAX)
> +#define CX(cpu) RX(cpu, REG_RCX)
> +#define DX(cpu) RX(cpu, REG_RDX)
> +#define BP(cpu) RX(cpu, REG_RBP)
> +#define SP(cpu) RX(cpu, REG_RSP)
> +#define BX(cpu) RX(cpu, REG_RBX)
> +#define SI(cpu) RX(cpu, REG_RSI)
> +#define DI(cpu) RX(cpu, REG_RDI)
> +
> +#define RL(cpu, reg) (cpu->hvf_x86->regs[reg].lx)
> +#define AL(cpu) RL(cpu, REG_RAX)
> +#define CL(cpu) RL(cpu, REG_RCX)
> +#define DL(cpu) RL(cpu, REG_RDX)
> +#define BL(cpu) RL(cpu, REG_RBX)
> +
> +#define RH(cpu, reg) (cpu->hvf_x86->regs[reg].hx)
> +#define AH(cpu) RH(cpu, REG_RAX)
> +#define CH(cpu) RH(cpu, REG_RCX)
> +#define DH(cpu) RH(cpu, REG_RDX)
> +#define BH(cpu) RH(cpu, REG_RBX)
> +
> +// deal with GDT/LDT descriptors in memory
> +bool x86_read_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
> +bool x86_write_segment_descriptor(struct CPUState *cpu, struct x86_segment_descriptor *desc, x68_segment_selector sel);
> +
> +bool x86_read_call_gate(struct CPUState *cpu, struct x86_call_gate *idt_desc, int gate);
> +
> +// helpers
> +bool x86_is_protected(struct CPUState *cpu);
> +bool x86_is_real(struct CPUState *cpu);
> +bool x86_is_v8086(struct CPUState *cpu);
> +bool x86_is_long_mode(struct CPUState *cpu);
> +bool x86_is_long64_mode(struct CPUState *cpu);
> +bool x86_is_paging_mode(struct CPUState *cpu);
> +bool x86_is_pae_enabled(struct CPUState *cpu);
> +
> +addr_t linear_addr(struct CPUState *cpu, addr_t addr, x86_reg_segment seg);
> +addr_t linear_addr_size(struct CPUState *cpu, addr_t addr, int size, x86_reg_segment seg);
> +addr_t linear_rip(struct CPUState *cpu, addr_t rip);
> +
> +static inline uint64_t rdtscp(void)
> +{
> + uint64_t tsc;
> + __asm__ __volatile__("rdtscp; " // serializing read of tsc
> + "shl $32,%%rdx; " // shift higher 32 bits stored in rdx up
> + "or %%rdx,%%rax" // and or onto rax
> + : "=a"(tsc) // output to tsc variable
> + :
> + : "%rcx", "%rdx"); // rcx and rdx are clobbered
> +
> + return tsc;
> +}
> +
> diff --git a/target/i386/hvf-utils/x86_cpuid.c b/target/i386/hvf-utils/x86_cpuid.c
> new file mode 100644
> index 0000000000..e496cf001c
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_cpuid.c
> @@ -0,0 +1,270 @@
> +/*
> + * i386 CPUID helper functions
> + *
> + * Copyright (c) 2003 Fabrice Bellard
> + * Copyright (c) 2017 Google Inc.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + *
> + * cpuid
> + */
> +
> +#include "qemu/osdep.h"
> +#include "x86_cpuid.h"
> +#include "x86.h"
> +#include "vmx.h"
> +
> +#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
> + CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
> + CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
> + CPUID_PAE | CPUID_SEP | CPUID_APIC)
> +
> +struct x86_cpuid builtin_cpus[] = {
> + {
> + .name = "vmx32",
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .level = 4,
> + .family = 6,
> + .model = 3,
> + .stepping = 3,
> + .features = PPRO_FEATURES,
> + .ext_features = /*CPUID_EXT_SSE3 |*/ CPUID_EXT_POPCNT, CPUID_MTRR | CPUID_CLFLUSH,
> + CPUID_PSE36,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> + .ext3_features = 0,//CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x80000004,
> + .model_id = "vmx32",
> + },
> + {
> + .name = "core2duo",
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .level = 10,
> + .family = 6,
> + .model = 15,
> + .stepping = 11,
> + .features = PPRO_FEATURES |
> + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
> + CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
> + CPUID_HT | CPUID_TM | CPUID_PBE,
> + .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_SSSE3 |
> + CPUID_EXT_DTES64 | CPUID_EXT_DSCPL |
> + CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM | CPUID_EXT_HYPERVISOR,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x80000008,
> + .model_id = "Intel(R) Core(TM)2 Duo GETCPU T7700 @ 2.40GHz",
> + },
> + {
> + .name = "vmX",
> + .vendor1 = CPUID_VENDOR_INTEL_1,
> + .vendor2 = CPUID_VENDOR_INTEL_2,
> + .vendor3 = CPUID_VENDOR_INTEL_3,
> + .level = 0xd,
> + .family = 6,
> + .model = 15,
> + .stepping = 11,
> + .features = PPRO_FEATURES |
> + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
> + CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
> + CPUID_HT | CPUID_TM | CPUID_PBE,
> + .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_SSSE3 |
> + CPUID_EXT_DTES64 | CPUID_EXT_DSCPL |
> + CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM | CPUID_EXT_HYPERVISOR,
> + .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
> + .ext3_features = CPUID_EXT3_LAHF_LM,
> + .xlevel = 0x80000008,
> + .model_id = "Common vmX processor",
> + },
> +};
> +
> +static struct x86_cpuid *_cpuid = NULL;
> +
> +void init_cpuid(struct CPUState* cpu)
> +{
> + _cpuid = &builtin_cpus[2]; // core2duo
> +}
> +
> +void get_cpuid_func(struct CPUState* cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
> +{
> + uint32_t h_rax, h_rbx, h_rcx, h_rdx;
> + host_cpuid(func, cnt, &h_rax, &h_rbx, &h_rcx, &h_rdx);
> + uint32_t apic_id = X86_CPU(cpu)->apic_id;
> +
> +
> + *eax = *ebx = *ecx = *edx = 0;
> + switch(func) {
> + case 0:
> + *eax = _cpuid->level;
> + *ebx = _cpuid->vendor1;
> + *edx = _cpuid->vendor2;
> + *ecx = _cpuid->vendor3;
> + break;
> + case 1:
> + *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
> + *ebx = (apic_id << 24) | (h_rbx & 0x00ffffff);
> + *ecx = h_rcx;
> + *edx = h_rdx;
> +
> + if (cpu->nr_cores * cpu->nr_threads > 1) {
> + *ebx |= (cpu->nr_cores * cpu->nr_threads) << 16;
> + *edx |= 1 << 28; /* Enable Hyper-Threading */
> + }
> +
> + *ecx = *ecx & ~(CPUID_EXT_OSXSAVE | CPUID_EXT_MONITOR | CPUID_EXT_X2APIC |
> + CPUID_EXT_VMX | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_TM2 | CPUID_EXT_PCID |
> + CPUID_EXT_EST | CPUID_EXT_SSE42 | CPUID_EXT_SSE41);
> + *ecx |= CPUID_EXT_HYPERVISOR;
> + break;
> + case 2:
> + /* cache info: needed for Pentium Pro compatibility */
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 4:
> + /* cache info: needed for Core compatibility */
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 5:
> + /* mwait info: needed for Core compatibility */
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 6:
> + /* Thermal and Power Leaf */
> + *eax = 0;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + break;
> + case 7:
> + *eax = h_rax;
> + *ebx = h_rbx & ~(CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF | CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
> + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_INVPCID);
> + *ecx = h_rcx & ~(CPUID_7_0_ECX_AVX512BMI);
> + *edx = h_rdx;
> + break;
> + case 9:
> + /* Direct Cache Access Information Leaf */
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 0xA:
> + /* Architectural Performance Monitoring Leaf */
> + *eax = 0;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + break;
> + case 0xB:
> + /* CPU Topology Leaf */
> + *eax = 0;
> + *ebx = 0; /* Means that we don't support this leaf */
> + *ecx = 0;
> + *edx = 0;
> + break;
> + case 0xD:
> + *eax = h_rax;
> + if (!cnt)
> + *eax &= (XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK);
> + if (1 == cnt)
> + *eax &= (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC);
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 0x80000000:
> + *eax = _cpuid->xlevel;
> + *ebx = _cpuid->vendor1;
> + *edx = _cpuid->vendor2;
> + *ecx = _cpuid->vendor3;
> + break;
> + case 0x80000001:
> + *eax = h_rax;//_cpuid->stepping | (_cpuid->model << 3) | (_cpuid->family << 6);
> + *ebx = 0;
> + *ecx = _cpuid->ext3_features & h_rcx;
> + *edx = _cpuid->ext2_features & h_rdx;
> + break;
> + case 0x80000002:
> + case 0x80000003:
> + case 0x80000004:
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 0x80000005:
> + /* cache info (L1 cache) */
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 0x80000006:
> + /* cache info (L2 cache) */
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = h_rcx;
> + *edx = h_rdx;
> + break;
> + case 0x80000007:
> + *eax = 0;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0; /* Note - We disable invariant TSC (bit 8) in purpose */
> + break;
> + case 0x80000008:
> + /* virtual & phys address size in low 2 bytes. */
> + *eax = h_rax;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + break;
> + case 0x8000000A:
> + *eax = 0;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + break;
> + case 0x80000019:
> + *eax = h_rax;
> + *ebx = h_rbx;
> + *ecx = 0;
> + *edx = 0;
> + case 0xC0000000:
> + *eax = _cpuid->xlevel2;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + break;
> + default:
> + *eax = 0;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + break;
> + }
> +}
> diff --git a/target/i386/hvf-utils/x86_cpuid.h b/target/i386/hvf-utils/x86_cpuid.h
> new file mode 100644
> index 0000000000..02f2f115b0
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_cpuid.h
> @@ -0,0 +1,51 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __CPUID_H__
> +#define __CPUID_H__
> +
> +#include <sys/types.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <stdarg.h>
> +#include "qemu-common.h"
> +#include "x86_flags.h"
> +
> +struct x86_cpuid {
> + const char *name;
> + uint32_t level;
> + uint32_t vendor1, vendor2, vendor3;
> + int family;
> + int model;
> + int stepping;
> + int tsc_khz;
> + uint32_t features, ext_features, ext2_features, ext3_features;
> + uint32_t kvm_features, svm_features;
> + uint32_t xlevel;
> + char model_id[48];
> + int vendor_override;
> + uint32_t flags;
> + uint32_t xlevel2;
> + uint32_t cpuid_7_0_ebx_features;
> +};
> +
> +struct CPUState;
> +
> +void init_cpuid(struct CPUState* cpu);
> +void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
> +
> +#endif /* __CPUID_H__ */
> +
> diff --git a/target/i386/hvf-utils/x86_decode.c b/target/i386/hvf-utils/x86_decode.c
> new file mode 100644
> index 0000000000..b4d8e22449
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_decode.c
> @@ -0,0 +1,1659 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "x86_decode.h"
> +#include "string.h"
> +#include "vmx.h"
> +#include "x86_gen.h"
> +#include "x86_mmu.h"
> +#include "x86_descr.h"
> +
> +#define OPCODE_ESCAPE 0xf
> +
> +static void decode_invalid(CPUState *cpu, struct x86_decode *decode)
> +{
> + printf("%llx: failed to decode instruction ", cpu->hvf_x86->fetch_rip - decode->len);
> + for (int i = 0; i < decode->opcode_len; i++)
> + printf("%x ", decode->opcode[i]);
> + printf("\n");
> + VM_PANIC("decoder failed\n");
> +}
> +
> +uint64_t sign(uint64_t val, int size)
> +{
> + switch (size) {
> + case 1:
> + val = (int8_t)val;
> + break;
> + case 2:
> + val = (int16_t)val;
> + break;
> + case 4:
> + val = (int32_t)val;
> + break;
> + case 8:
> + val = (int64_t)val;
> + break;
> + default:
> + VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
> + break;
> + }
> + return val;
> +}
> +
> +static inline uint64_t decode_bytes(CPUState *cpu, struct x86_decode *decode, int size)
> +{
> + addr_t val = 0;
> +
> + switch (size) {
> + case 1:
> + case 2:
> + case 4:
> + case 8:
> + break;
> + default:
> + VM_PANIC_EX("%s invalid size %d\n", __FUNCTION__, size);
> + break;
> + }
> + addr_t va = linear_rip(cpu, RIP(cpu)) + decode->len;
> + vmx_read_mem(cpu, &val, va, size);
> + decode->len += size;
> +
> + return val;
> +}
> +
> +static inline uint8_t decode_byte(CPUState *cpu, struct x86_decode *decode)
> +{
> + return (uint8_t)decode_bytes(cpu, decode, 1);
> +}
> +
> +static inline uint16_t decode_word(CPUState *cpu, struct x86_decode *decode)
> +{
> + return (uint16_t)decode_bytes(cpu, decode, 2);
> +}
> +
> +static inline uint32_t decode_dword(CPUState *cpu, struct x86_decode *decode)
> +{
> + return (uint32_t)decode_bytes(cpu, decode, 4);
> +}
> +
> +static inline uint64_t decode_qword(CPUState *cpu, struct x86_decode *decode)
> +{
> + return decode_bytes(cpu, decode, 8);
> +}
> +
> +static void decode_modrm_rm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_RM;
> +}
> +
> +static void decode_modrm_reg(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_REG;
> + op->reg = decode->modrm.reg;
> + op->ptr = get_reg_ref(cpu, op->reg, decode->rex.r, decode->operand_size);
> +}
> +
> +static void decode_rax(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_REG;
> + op->reg = REG_RAX;
> + op->ptr = get_reg_ref(cpu, op->reg, 0, decode->operand_size);
> +}
> +
> +static inline void decode_immediate(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *var, int size)
> +{
> + var->type = X86_VAR_IMMEDIATE;
> + var->size = size;
> + switch (size) {
> + case 1:
> + var->val = decode_byte(cpu, decode);
> + break;
> + case 2:
> + var->val = decode_word(cpu, decode);
> + break;
> + case 4:
> + var->val = decode_dword(cpu, decode);
> + break;
> + case 8:
> + var->val = decode_qword(cpu, decode);
> + break;
> + default:
> + VM_PANIC_EX("bad size %d\n", size);
> + }
> +}
> +
> +static void decode_imm8(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + decode_immediate(cpu, decode, op, 1);
> + op->type = X86_VAR_IMMEDIATE;
> +}
> +
> +static void decode_imm8_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + decode_immediate(cpu, decode, op, 1);
> + op->val = sign(op->val, 1);
> + op->type = X86_VAR_IMMEDIATE;
> +}
> +
> +static void decode_imm16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + decode_immediate(cpu, decode, op, 2);
> + op->type = X86_VAR_IMMEDIATE;
> +}
> +
> +
> +static void decode_imm(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + if (8 == decode->operand_size) {
> + decode_immediate(cpu, decode, op, 4);
> + op->val = sign(op->val, decode->operand_size);
> + } else {
> + decode_immediate(cpu, decode, op, decode->operand_size);
> + }
> + op->type = X86_VAR_IMMEDIATE;
> +}
> +
> +static void decode_imm_signed(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + decode_immediate(cpu, decode, op, decode->operand_size);
> + op->val = sign(op->val, decode->operand_size);
> + op->type = X86_VAR_IMMEDIATE;
> +}
> +
> +static void decode_imm_1(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_IMMEDIATE;
> + op->val = 1;
> +}
> +
> +static void decode_imm_0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_IMMEDIATE;
> + op->val = 0;
> +}
> +
> +
> +static void decode_pushseg(CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
> +
> + decode->op[0].type = X86_VAR_REG;
> + switch (op) {
> + case 0xe:
> + decode->op[0].reg = REG_SEG_CS;
> + break;
> + case 0x16:
> + decode->op[0].reg = REG_SEG_SS;
> + break;
> + case 0x1e:
> + decode->op[0].reg = REG_SEG_DS;
> + break;
> + case 0x06:
> + decode->op[0].reg = REG_SEG_ES;
> + break;
> + case 0xa0:
> + decode->op[0].reg = REG_SEG_FS;
> + break;
> + case 0xa8:
> + decode->op[0].reg = REG_SEG_GS;
> + break;
> + }
> +}
> +
> +static void decode_popseg(CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t op = (decode->opcode_len > 1) ? decode->opcode[1] : decode->opcode[0];
> +
> + decode->op[0].type = X86_VAR_REG;
> + switch (op) {
> + case 0xf:
> + decode->op[0].reg = REG_SEG_CS;
> + break;
> + case 0x17:
> + decode->op[0].reg = REG_SEG_SS;
> + break;
> + case 0x1f:
> + decode->op[0].reg = REG_SEG_DS;
> + break;
> + case 0x07:
> + decode->op[0].reg = REG_SEG_ES;
> + break;
> + case 0xa1:
> + decode->op[0].reg = REG_SEG_FS;
> + break;
> + case 0xa9:
> + decode->op[0].reg = REG_SEG_GS;
> + break;
> + }
> +}
> +
> +static void decode_incgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0x40;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> +}
> +
> +static void decode_decgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0x48;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> +}
> +
> +static void decode_incgroup2(CPUState *cpu, struct x86_decode *decode)
> +{
> + if (!decode->modrm.reg)
> + decode->cmd = X86_DECODE_CMD_INC;
> + else if (1 == decode->modrm.reg)
> + decode->cmd = X86_DECODE_CMD_DEC;
> +}
> +
> +static void decode_pushgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0x50;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> +}
> +
> +static void decode_popgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0x58;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> +}
> +
> +static void decode_jxx(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->displacement = decode_bytes(cpu, decode, decode->operand_size);
> + decode->displacement_size = decode->operand_size;
> +}
> +
> +static void decode_farjmp(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_IMMEDIATE;
> + decode->op[0].val = decode_bytes(cpu, decode, decode->operand_size);
> + decode->displacement = decode_word(cpu, decode);
> +}
> +
> +static void decode_addgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_ADD,
> + X86_DECODE_CMD_OR,
> + X86_DECODE_CMD_ADC,
> + X86_DECODE_CMD_SBB,
> + X86_DECODE_CMD_AND,
> + X86_DECODE_CMD_SUB,
> + X86_DECODE_CMD_XOR,
> + X86_DECODE_CMD_CMP
> + };
> + decode->cmd = group[decode->modrm.reg];
> +}
> +
> +static void decode_rotgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_ROL,
> + X86_DECODE_CMD_ROR,
> + X86_DECODE_CMD_RCL,
> + X86_DECODE_CMD_RCR,
> + X86_DECODE_CMD_SHL,
> + X86_DECODE_CMD_SHR,
> + X86_DECODE_CMD_SHL,
> + X86_DECODE_CMD_SAR
> + };
> + decode->cmd = group[decode->modrm.reg];
> +}
> +
> +static void decode_f7group(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_TST,
> + X86_DECODE_CMD_TST,
> + X86_DECODE_CMD_NOT,
> + X86_DECODE_CMD_NEG,
> + X86_DECODE_CMD_MUL,
> + X86_DECODE_CMD_IMUL_1,
> + X86_DECODE_CMD_DIV,
> + X86_DECODE_CMD_IDIV
> + };
> + decode->cmd = group[decode->modrm.reg];
> + decode_modrm_rm(cpu, decode, &decode->op[0]);
> +
> + switch (decode->modrm.reg) {
> + case 0:
> + case 1:
> + decode_imm(cpu, decode, &decode->op[1]);
> + break;
> + case 2:
> + break;
> + case 3:
> + decode->op[1].type = X86_VAR_IMMEDIATE;
> + decode->op[1].val = 0;
> + break;
> + default:
> + break;
> + }
> +}
> +
> +static void decode_xchgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0x90;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> +}
> +
> +static void decode_movgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0xb8;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> + decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
> +}
> +
> +static void fetch_moffs(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_OFFSET;
> + op->ptr = decode_bytes(cpu, decode, decode->addressing_size);
> +}
> +
> +static void decode_movgroup8(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[0] - 0xb0;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> + decode_immediate(cpu, decode, &decode->op[1], decode->operand_size);
> +}
> +
> +static void decode_rcx(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X86_VAR_REG;
> + op->reg = REG_RCX;
> + op->ptr = get_reg_ref(cpu, op->reg, decode->rex.b, decode->operand_size);
> +}
> +
> +struct decode_tbl {
> + uint8_t opcode;
> + enum x86_decode_cmd cmd;
> + uint8_t operand_size;
> + bool is_modrm;
> + void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
> + void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
> + void (*decode_op3)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op3);
> + void (*decode_op4)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op4);
> + void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
> + addr_t flags_mask;
> +};
> +
> +struct decode_x87_tbl {
> + uint8_t opcode;
> + uint8_t modrm_reg;
> + uint8_t modrm_mod;
> + enum x86_decode_cmd cmd;
> + uint8_t operand_size;
> + bool rev;
> + bool pop;
> + void (*decode_op1)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op1);
> + void (*decode_op2)(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op2);
> + void (*decode_postfix)(CPUState *cpu, struct x86_decode *decode);
> + addr_t flags_mask;
> +};
> +
> +struct decode_tbl invl_inst = {0x0, 0, 0, false, NULL, NULL, NULL, NULL, decode_invalid};
> +
> +struct decode_tbl _decode_tbl1[255];
> +struct decode_tbl _decode_tbl2[255];
> +struct decode_x87_tbl _decode_tbl3[255];
> +
> +static void decode_x87_ins(CPUState *cpu, struct x86_decode *decode)
> +{
> + struct decode_x87_tbl *decoder;
> +
> + decode->is_fpu = true;
> + int mode = decode->modrm.mod == 3 ? 1 : 0;
> + int index = ((decode->opcode[0] & 0xf) << 4) | (mode << 3) | decode->modrm.reg;
> +
> + decoder = &_decode_tbl3[index];
> +
> + decode->cmd = decoder->cmd;
> + if (decoder->operand_size)
> + decode->operand_size = decoder->operand_size;
> + decode->flags_mask = decoder->flags_mask;
> + decode->fpop_stack = decoder->pop;
> + decode->frev = decoder->rev;
> +
> + if (decoder->decode_op1)
> + decoder->decode_op1(cpu, decode, &decode->op[0]);
> + if (decoder->decode_op2)
> + decoder->decode_op2(cpu, decode, &decode->op[1]);
> + if (decoder->decode_postfix)
> + decoder->decode_postfix(cpu, decode);
> +
> + VM_PANIC_ON_EX(!decode->cmd, "x87 opcode %x %x (%x %x) not decoded\n", decode->opcode[0], decode->modrm.modrm, decoder->modrm_reg, decoder->modrm_mod);
> +}
> +
> +static void decode_ffgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_INC,
> + X86_DECODE_CMD_DEC,
> + X86_DECODE_CMD_CALL_NEAR_ABS_INDIRECT,
> + X86_DECODE_CMD_CALL_FAR_ABS_INDIRECT,
> + X86_DECODE_CMD_JMP_NEAR_ABS_INDIRECT,
> + X86_DECODE_CMD_JMP_FAR_ABS_INDIRECT,
> + X86_DECODE_CMD_PUSH,
> + X86_DECODE_CMD_INVL,
> + X86_DECODE_CMD_INVL
> + };
> + decode->cmd = group[decode->modrm.reg];
> + if (decode->modrm.reg > 2)
> + decode->flags_mask = 0;
> +}
> +
> +static void decode_sldtgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_SLDT,
> + X86_DECODE_CMD_STR,
> + X86_DECODE_CMD_LLDT,
> + X86_DECODE_CMD_LTR,
> + X86_DECODE_CMD_VERR,
> + X86_DECODE_CMD_VERW,
> + X86_DECODE_CMD_INVL,
> + X86_DECODE_CMD_INVL
> + };
> + decode->cmd = group[decode->modrm.reg];
> + printf("%llx: decode_sldtgroup: %d\n", cpu->hvf_x86->fetch_rip, decode->modrm.reg);
> +}
> +
> +static void decode_lidtgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_SGDT,
> + X86_DECODE_CMD_SIDT,
> + X86_DECODE_CMD_LGDT,
> + X86_DECODE_CMD_LIDT,
> + X86_DECODE_CMD_SMSW,
> + X86_DECODE_CMD_LMSW,
> + X86_DECODE_CMD_LMSW,
> + X86_DECODE_CMD_INVLPG
> + };
> + decode->cmd = group[decode->modrm.reg];
> + if (0xf9 == decode->modrm.modrm) {
> + decode->opcode[decode->len++] = decode->modrm.modrm;
> + decode->cmd = X86_DECODE_CMD_RDTSCP;
> + }
> +}
> +
> +static void decode_btgroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + enum x86_decode_cmd group[] = {
> + X86_DECODE_CMD_INVL,
> + X86_DECODE_CMD_INVL,
> + X86_DECODE_CMD_INVL,
> + X86_DECODE_CMD_INVL,
> + X86_DECODE_CMD_BT,
> + X86_DECODE_CMD_BTS,
> + X86_DECODE_CMD_BTR,
> + X86_DECODE_CMD_BTC
> + };
> + decode->cmd = group[decode->modrm.reg];
> +}
> +
> +static void decode_x87_general(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->is_fpu = true;
> +}
> +
> +static void decode_x87_modrm_floatp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X87_VAR_FLOATP;
> +}
> +
> +static void decode_x87_modrm_intp(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X87_VAR_INTP;
> +}
> +
> +static void decode_x87_modrm_bytep(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X87_VAR_BYTEP;
> +}
> +
> +static void decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X87_VAR_REG;
> + op->reg = 0;
> +}
> +
> +static void decode_decode_x87_modrm_st0(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + op->type = X87_VAR_REG;
> + op->reg = decode->modrm.modrm & 7;
> +}
> +
> +
> +static void decode_aegroup(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->is_fpu = true;
> + switch (decode->modrm.reg) {
> + case 0:
> + decode->cmd = X86_DECODE_CMD_FXSAVE;
> + decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
> + break;
> + case 1:
> + decode_x87_modrm_bytep(cpu, decode, &decode->op[0]);
> + decode->cmd = X86_DECODE_CMD_FXRSTOR;
> + break;
> + case 5:
> + if (decode->modrm.modrm == 0xe8) {
> + decode->cmd = X86_DECODE_CMD_LFENCE;
> + } else {
> + VM_PANIC("xrstor");
> + }
> + break;
> + case 6:
> + VM_PANIC_ON(decode->modrm.modrm != 0xf0);
> + decode->cmd = X86_DECODE_CMD_MFENCE;
> + break;
> + case 7:
> + if (decode->modrm.modrm == 0xf8) {
> + decode->cmd = X86_DECODE_CMD_SFENCE;
> + } else {
> + decode->cmd = X86_DECODE_CMD_CLFLUSH;
> + }
> + break;
> + default:
> + VM_PANIC_ON_EX(1, "0xae: reg %d\n", decode->modrm.reg);
> + break;
> + }
> +}
> +
> +static void decode_bswap(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = decode->opcode[1] - 0xc8;
> + decode->op[0].ptr = get_reg_ref(cpu, decode->op[0].reg, decode->rex.b, decode->operand_size);
> +}
> +
> +static void decode_d9_4(CPUState *cpu, struct x86_decode *decode)
> +{
> + switch(decode->modrm.modrm) {
> + case 0xe0:
> + // FCHS
> + decode->cmd = X86_DECODE_CMD_FCHS;
> + break;
> + case 0xe1:
> + decode->cmd = X86_DECODE_CMD_FABS;
> + break;
> + case 0xe4:
> + VM_PANIC_ON_EX(1, "FTST");
> + break;
> + case 0xe5:
> + // FXAM
> + decode->cmd = X86_DECODE_CMD_FXAM;
> + break;
> + default:
> + VM_PANIC_ON_EX(1, "FLDENV");
> + break;
> + }
> +}
> +
> +static void decode_db_4(CPUState *cpu, struct x86_decode *decode)
> +{
> + switch (decode->modrm.modrm) {
> + case 0xe0:
> + VM_PANIC_ON_EX(1, "unhandled FNENI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
> + break;
> + case 0xe1:
> + VM_PANIC_ON_EX(1, "unhandled FNDISI: %x %x\n", decode->opcode[0], decode->modrm.modrm);
> + break;
> + case 0xe2:
> + VM_PANIC_ON_EX(1, "unhandled FCLEX: %x %x\n", decode->opcode[0], decode->modrm.modrm);
> + break;
> + case 0xe3:
> + decode->cmd = X86_DECODE_CMD_FNINIT;
> + break;
> + case 0xe4:
> + decode->cmd = X86_DECODE_CMD_FNSETPM;
> + break;
> + default:
> + VM_PANIC_ON_EX(1, "unhandled fpu opcode: %x %x\n", decode->opcode[0], decode->modrm.modrm);
> + break;
> + }
> +}
> +
> +
> +#define RFLAGS_MASK_NONE 0
> +#define RFLAGS_MASK_OSZAPC (RFLAGS_OF | RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
> +#define RFLAGS_MASK_LAHF (RFLAGS_SF | RFLAGS_ZF | RFLAGS_AF | RFLAGS_PF | RFLAGS_CF)
> +#define RFLAGS_MASK_CF (RFLAGS_CF)
> +#define RFLAGS_MASK_IF (RFLAGS_IF)
> +#define RFLAGS_MASK_TF (RFLAGS_TF)
> +#define RFLAGS_MASK_DF (RFLAGS_DF)
> +#define RFLAGS_MASK_ZF (RFLAGS_ZF)
> +
> +struct decode_tbl _1op_inst[] =
> +{
> + {0x0, X86_DECODE_CMD_ADD, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x1, X86_DECODE_CMD_ADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x2, X86_DECODE_CMD_ADD, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x3, X86_DECODE_CMD_ADD, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x4, X86_DECODE_CMD_ADD, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x5, X86_DECODE_CMD_ADD, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x6, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
> + {0x7, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
> + {0x8, X86_DECODE_CMD_OR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x9, X86_DECODE_CMD_OR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xa, X86_DECODE_CMD_OR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xb, X86_DECODE_CMD_OR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xc, X86_DECODE_CMD_OR, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xd, X86_DECODE_CMD_OR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xe, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
> + {0xf, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
> +
> + {0x10, X86_DECODE_CMD_ADC, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x11, X86_DECODE_CMD_ADC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x12, X86_DECODE_CMD_ADC, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x13, X86_DECODE_CMD_ADC, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x14, X86_DECODE_CMD_ADC, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x15, X86_DECODE_CMD_ADC, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0x16, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
> + {0x17, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
> +
> + {0x18, X86_DECODE_CMD_SBB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x19, X86_DECODE_CMD_SBB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x1a, X86_DECODE_CMD_SBB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x1b, X86_DECODE_CMD_SBB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x1c, X86_DECODE_CMD_SBB, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x1d, X86_DECODE_CMD_SBB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0x1e, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
> + {0x1f, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
> +
> + {0x20, X86_DECODE_CMD_AND, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x21, X86_DECODE_CMD_AND, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x22, X86_DECODE_CMD_AND, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x23, X86_DECODE_CMD_AND, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x24, X86_DECODE_CMD_AND, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x25, X86_DECODE_CMD_AND, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x28, X86_DECODE_CMD_SUB, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x29, X86_DECODE_CMD_SUB, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x2a, X86_DECODE_CMD_SUB, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x2b, X86_DECODE_CMD_SUB, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x2c, X86_DECODE_CMD_SUB, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x2d, X86_DECODE_CMD_SUB, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x2f, X86_DECODE_CMD_DAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x30, X86_DECODE_CMD_XOR, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x31, X86_DECODE_CMD_XOR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x32, X86_DECODE_CMD_XOR, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x33, X86_DECODE_CMD_XOR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x34, X86_DECODE_CMD_XOR, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x35, X86_DECODE_CMD_XOR, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0x38, X86_DECODE_CMD_CMP, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x39, X86_DECODE_CMD_CMP, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x3a, X86_DECODE_CMD_CMP, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x3b, X86_DECODE_CMD_CMP, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x3c, X86_DECODE_CMD_CMP, 1, false, decode_rax, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x3d, X86_DECODE_CMD_CMP, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0x3f, X86_DECODE_CMD_AAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0x40, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x41, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x42, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x43, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x44, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x45, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x46, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> + {0x47, X86_DECODE_CMD_INC, 0, false, NULL, NULL, NULL, NULL, decode_incgroup, RFLAGS_MASK_OSZAPC},
> +
> + {0x48, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x49, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x4a, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x4b, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x4c, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x4d, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x4e, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> + {0x4f, X86_DECODE_CMD_DEC, 0, false, NULL, NULL, NULL, NULL, decode_decgroup, RFLAGS_MASK_OSZAPC},
> +
> + {0x50, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x51, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x52, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x53, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x54, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x55, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x56, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> + {0x57, X86_DECODE_CMD_PUSH, 0, false, NULL, NULL, NULL, NULL, decode_pushgroup, RFLAGS_MASK_NONE},
> +
> + {0x58, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x59, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x5a, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x5b, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x5c, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x5d, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x5e, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> + {0x5f, X86_DECODE_CMD_POP, 0, false, NULL, NULL, NULL, NULL, decode_popgroup, RFLAGS_MASK_NONE},
> +
> + {0x60, X86_DECODE_CMD_PUSHA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x61, X86_DECODE_CMD_POPA, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0x68, X86_DECODE_CMD_PUSH, 0, false, decode_imm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x6a, X86_DECODE_CMD_PUSH, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x69, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x6b, X86_DECODE_CMD_IMUL_3, 0, true, decode_modrm_reg, decode_modrm_rm, decode_imm8_signed, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0x6c, X86_DECODE_CMD_INS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x6d, X86_DECODE_CMD_INS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x6e, X86_DECODE_CMD_OUTS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x6f, X86_DECODE_CMD_OUTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0x70, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x71, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x72, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x73, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x74, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x75, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x76, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x77, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x78, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x79, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x7a, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x7b, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x7c, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x7d, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x7e, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x7f, X86_DECODE_CMD_JXX, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> +
> + {0x80, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
> + {0x81, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
> + {0x82, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
> + {0x83, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8_signed, NULL, NULL, decode_addgroup, RFLAGS_MASK_OSZAPC},
> + {0x84, X86_DECODE_CMD_TST, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x85, X86_DECODE_CMD_TST, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0x86, X86_DECODE_CMD_XCHG, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x87, X86_DECODE_CMD_XCHG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x88, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x89, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x8a, X86_DECODE_CMD_MOV, 1, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x8b, X86_DECODE_CMD_MOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x8c, X86_DECODE_CMD_MOV_FROM_SEG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x8d, X86_DECODE_CMD_LEA, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x8e, X86_DECODE_CMD_MOV_TO_SEG, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x8f, X86_DECODE_CMD_POP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0x90, X86_DECODE_CMD_NOP, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x91, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> + {0x92, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> + {0x93, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> + {0x94, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> + {0x95, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> + {0x96, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> + {0x97, X86_DECODE_CMD_XCHG, 0, false, NULL, decode_rax, NULL, NULL, decode_xchgroup, RFLAGS_MASK_NONE},
> +
> + {0x98, X86_DECODE_CMD_CBW, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x99, X86_DECODE_CMD_CWD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0x9a, X86_DECODE_CMD_CALL_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
> +
> + {0x9c, X86_DECODE_CMD_PUSHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + //{0x9d, X86_DECODE_CMD_POPF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_POPF},
> + {0x9e, X86_DECODE_CMD_SAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9f, X86_DECODE_CMD_LAHF, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_LAHF},
> +
> + {0xa0, X86_DECODE_CMD_MOV, 1, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa1, X86_DECODE_CMD_MOV, 0, false, decode_rax, fetch_moffs, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa2, X86_DECODE_CMD_MOV, 1, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa3, X86_DECODE_CMD_MOV, 0, false, fetch_moffs, decode_rax, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xa4, X86_DECODE_CMD_MOVS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa5, X86_DECODE_CMD_MOVS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa6, X86_DECODE_CMD_CMPS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xa7, X86_DECODE_CMD_CMPS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xaa, X86_DECODE_CMD_STOS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xab, X86_DECODE_CMD_STOS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xac, X86_DECODE_CMD_LODS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xad, X86_DECODE_CMD_LODS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xae, X86_DECODE_CMD_SCAS, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xaf, X86_DECODE_CMD_SCAS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xa8, X86_DECODE_CMD_TST, 1, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xa9, X86_DECODE_CMD_TST, 0, false, decode_rax, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xb0, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb1, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb2, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb3, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb4, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb5, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb6, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> + {0xb7, X86_DECODE_CMD_MOV, 1, false, NULL, NULL, NULL, NULL, decode_movgroup8, RFLAGS_MASK_NONE},
> +
> + {0xb8, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xb9, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xba, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xbb, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xbc, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xbd, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xbe, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> + {0xbf, X86_DECODE_CMD_MOV, 0, false, NULL, NULL, NULL, NULL, decode_movgroup, RFLAGS_MASK_NONE},
> +
> + {0xc0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
> + {0xc1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
> +
> + {0xc2, X86_DECODE_RET_NEAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xc3, X86_DECODE_RET_NEAR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xc4, X86_DECODE_CMD_LES, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xc5, X86_DECODE_CMD_LDS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xc6, X86_DECODE_CMD_MOV, 1, true, decode_modrm_rm, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xc7, X86_DECODE_CMD_MOV, 0, true, decode_modrm_rm, decode_imm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xc8, X86_DECODE_CMD_ENTER, 0, false, decode_imm16, decode_imm8, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xc9, X86_DECODE_CMD_LEAVE, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xca, X86_DECODE_RET_FAR, 0, false, decode_imm16, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xcb, X86_DECODE_RET_FAR, 0, false, decode_imm_0, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xcd, X86_DECODE_CMD_INT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + //{0xcf, X86_DECODE_CMD_IRET, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IRET},
> +
> + {0xd0, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
> + {0xd1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm_1, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
> + {0xd2, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
> + {0xd3, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_rcx, NULL, NULL, decode_rotgroup, RFLAGS_MASK_OSZAPC},
> +
> + {0xd4, X86_DECODE_CMD_AAM, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xd5, X86_DECODE_CMD_AAD, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xd7, X86_DECODE_CMD_XLAT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xd8, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xd9, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xda, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xdb, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xdc, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xdd, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xde, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> + {0xdf, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_x87_ins, RFLAGS_MASK_NONE},
> +
> + {0xe0, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe1, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe2, X86_DECODE_CMD_LOOP, 0, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xe3, X86_DECODE_CMD_JCXZ, 1, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> +
> + {0xe4, X86_DECODE_CMD_IN, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe5, X86_DECODE_CMD_IN, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe6, X86_DECODE_CMD_OUT, 1, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe7, X86_DECODE_CMD_OUT, 0, false, decode_imm8, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe8, X86_DECODE_CMD_CALL_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xe9, X86_DECODE_CMD_JMP_NEAR, 0, false, decode_imm_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xea, X86_DECODE_CMD_JMP_FAR, 0, false, NULL, NULL, NULL, NULL, decode_farjmp, RFLAGS_MASK_NONE},
> + {0xeb, X86_DECODE_CMD_JMP_NEAR, 1, false, decode_imm8_signed, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xec, X86_DECODE_CMD_IN, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xed, X86_DECODE_CMD_IN, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xee, X86_DECODE_CMD_OUT, 1, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xef, X86_DECODE_CMD_OUT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xf4, X86_DECODE_CMD_HLT, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xf5, X86_DECODE_CMD_CMC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
> +
> + {0xf6, X86_DECODE_CMD_INVL, 1, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
> + {0xf7, X86_DECODE_CMD_INVL, 0, true, NULL, NULL, NULL, NULL, decode_f7group, RFLAGS_MASK_OSZAPC},
> +
> + {0xf8, X86_DECODE_CMD_CLC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
> + {0xf9, X86_DECODE_CMD_STC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_CF},
> +
> + {0xfa, X86_DECODE_CMD_CLI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
> + {0xfb, X86_DECODE_CMD_STI, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_IF},
> + {0xfc, X86_DECODE_CMD_CLD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
> + {0xfd, X86_DECODE_CMD_STD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_DF},
> + {0xfe, X86_DECODE_CMD_INVL, 1, true, decode_modrm_rm, NULL, NULL, NULL, decode_incgroup2, RFLAGS_MASK_OSZAPC},
> + {0xff, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_ffgroup, RFLAGS_MASK_OSZAPC},
> +};
> +
> +struct decode_tbl _2op_inst[] =
> +{
> + {0x0, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_sldtgroup, RFLAGS_MASK_NONE},
> + {0x1, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_lidtgroup, RFLAGS_MASK_NONE},
> + {0x6, X86_DECODE_CMD_CLTS, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_TF},
> + {0x9, X86_DECODE_CMD_WBINVD, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x18, X86_DECODE_CMD_PREFETCH, 0, true, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
> + {0x1f, X86_DECODE_CMD_NOP, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x20, X86_DECODE_CMD_MOV_FROM_CR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x21, X86_DECODE_CMD_MOV_FROM_DR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x22, X86_DECODE_CMD_MOV_TO_CR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x23, X86_DECODE_CMD_MOV_TO_DR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x30, X86_DECODE_CMD_WRMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x31, X86_DECODE_CMD_RDTSC, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x32, X86_DECODE_CMD_RDMSR, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x40, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x41, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x42, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x43, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x44, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x45, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x46, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x47, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x48, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x49, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x4a, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x4b, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x4c, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x4d, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x4e, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x4f, X86_DECODE_CMD_CMOV, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x77, X86_DECODE_CMD_EMMS, 0, false, NULL, NULL, NULL, NULL, decode_x87_general, RFLAGS_MASK_NONE},
> + {0x82, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x83, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x84, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x85, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x86, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x87, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x88, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x89, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x8a, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x8b, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x8c, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x8d, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x8e, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x8f, X86_DECODE_CMD_JXX, 0, false, NULL, NULL, NULL, NULL, decode_jxx, RFLAGS_MASK_NONE},
> + {0x90, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x91, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x92, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x93, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x94, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x95, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x96, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x97, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x98, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x99, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9a, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9b, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9c, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9d, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9e, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0x9f, X86_DECODE_CMD_SETXX, 1, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xb0, X86_DECODE_CMD_CMPXCHG, 1, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xb1, X86_DECODE_CMD_CMPXCHG, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xb6, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xb7, X86_DECODE_CMD_MOVZX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xb8, X86_DECODE_CMD_POPCNT, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xbe, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xbf, X86_DECODE_CMD_MOVSX, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa0, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
> + {0xa1, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
> + {0xa2, X86_DECODE_CMD_CPUID, 0, false, NULL, NULL, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xa3, X86_DECODE_CMD_BT, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
> + {0xa4, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xa5, X86_DECODE_CMD_SHLD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xa8, X86_DECODE_CMD_PUSH_SEG, 0, false, false, NULL, NULL, NULL, decode_pushseg, RFLAGS_MASK_NONE},
> + {0xa9, X86_DECODE_CMD_POP_SEG, 0, false, false, NULL, NULL, NULL, decode_popseg, RFLAGS_MASK_NONE},
> + {0xab, X86_DECODE_CMD_BTS, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_CF},
> + {0xac, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_imm8, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xad, X86_DECODE_CMD_SHRD, 0, true, decode_modrm_rm, decode_modrm_reg, decode_rcx, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xae, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, NULL, NULL, NULL, decode_aegroup, RFLAGS_MASK_NONE},
> +
> + {0xaf, X86_DECODE_CMD_IMUL_2, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xb2, X86_DECODE_CMD_LSS, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xb3, X86_DECODE_CMD_BTR, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xba, X86_DECODE_CMD_INVL, 0, true, decode_modrm_rm, decode_imm8, NULL, NULL, decode_btgroup, RFLAGS_MASK_OSZAPC},
> + {0xbb, X86_DECODE_CMD_BTC, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xbc, X86_DECODE_CMD_BSF, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> + {0xbd, X86_DECODE_CMD_BSR, 0, true, decode_modrm_reg, decode_modrm_rm, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xc1, X86_DECODE_CMD_XADD, 0, true, decode_modrm_rm, decode_modrm_reg, NULL, NULL, NULL, RFLAGS_MASK_OSZAPC},
> +
> + {0xc7, X86_DECODE_CMD_CMPXCHG8B, 0, true, decode_modrm_rm, NULL, NULL, NULL, NULL, RFLAGS_MASK_ZF},
> +
> + {0xc8, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xc9, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xca, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xcb, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xcc, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xcd, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xce, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> + {0xcf, X86_DECODE_CMD_BSWAP, 0, false, NULL, NULL, NULL, NULL, decode_bswap, RFLAGS_MASK_NONE},
> +};
> +
> +struct decode_x87_tbl invl_inst_x87 = {0x0, 0, 0, 0, 0, false, false, NULL, NULL, decode_invalid, 0};
> +
> +struct decode_x87_tbl _x87_inst[] =
> +{
> + {0xd8, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 4, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 5, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 6, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0,decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 7, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd8, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> +
> + {0xd9, 0, 3, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 1, 0, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 2, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 3, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, decode_x87_modrm_st0, NULL, decode_d9_4, RFLAGS_MASK_NONE},
> + {0xd9, 4, 0, X86_DECODE_CMD_INVL, 4, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 5, 3, X86_DECODE_CMD_FLDxx, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 5, 0, X86_DECODE_CMD_FLDCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> + //
> + {0xd9, 7, 3, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xd9, 7, 0, X86_DECODE_CMD_FNSTCW, 2, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xda, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xda, 0, 0, X86_DECODE_CMD_FADD, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xda, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xda, 1, 0, X86_DECODE_CMD_FMUL, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xda, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xda, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xda, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xda, 4, 0, X86_DECODE_CMD_FSUB, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xda, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xda, 5, 0, X86_DECODE_CMD_FSUB, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xda, 6, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xda, 6, 0, X86_DECODE_CMD_FDIV, 4, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xda, 7, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xda, 7, 0, X86_DECODE_CMD_FDIV, 4, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> +
> + {0xdb, 0, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 0, 0, X86_DECODE_CMD_FLD, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 1, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 2, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 2, 0, X86_DECODE_CMD_FST, 4, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 3, 3, X86_DECODE_CMD_FCMOV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 3, 0, X86_DECODE_CMD_FST, 4, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 4, 3, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, decode_db_4, RFLAGS_MASK_NONE},
> + {0xdb, 4, 0, X86_DECODE_CMD_INVL, 10, false, false, NULL, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 5, 0, X86_DECODE_CMD_FLD, 10, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdb, 7, 0, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xdc, 0, 3, X86_DECODE_CMD_FADD, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 0, 0, X86_DECODE_CMD_FADD, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 1, 3, X86_DECODE_CMD_FMUL, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 1, 0, X86_DECODE_CMD_FMUL, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 4, 3, X86_DECODE_CMD_FSUB, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 4, 0, X86_DECODE_CMD_FSUB, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 5, 3, X86_DECODE_CMD_FSUB, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 5, 0, X86_DECODE_CMD_FSUB, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 6, 3, X86_DECODE_CMD_FDIV, 10, true, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 6, 0, X86_DECODE_CMD_FDIV, 8, false, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 7, 3, X86_DECODE_CMD_FDIV, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdc, 7, 0, X86_DECODE_CMD_FDIV, 8, true, false, decode_x87_modrm_st0, decode_x87_modrm_floatp, NULL, RFLAGS_MASK_NONE},
> +
> + {0xdd, 0, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 2, 3, X86_DECODE_CMD_FST, 10, false, false, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 2, 0, X86_DECODE_CMD_FST, 8, false, false, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 3, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_floatp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 4, 3, X86_DECODE_CMD_FUCOM, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 4, 0, X86_DECODE_CMD_FRSTOR, 8, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 5, 3, X86_DECODE_CMD_FUCOM, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 7, 0, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdd, 7, 3, X86_DECODE_CMD_FNSTSW, 0, false, false, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> +
> + {0xde, 0, 3, X86_DECODE_CMD_FADD, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xde, 0, 0, X86_DECODE_CMD_FADD, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xde, 1, 3, X86_DECODE_CMD_FMUL, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xde, 1, 0, X86_DECODE_CMD_FMUL, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xde, 4, 3, X86_DECODE_CMD_FSUB, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xde, 4, 0, X86_DECODE_CMD_FSUB, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xde, 5, 3, X86_DECODE_CMD_FSUB, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xde, 5, 0, X86_DECODE_CMD_FSUB, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xde, 6, 3, X86_DECODE_CMD_FDIV, 10, true, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xde, 6, 0, X86_DECODE_CMD_FDIV, 2, false, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> + {0xde, 7, 3, X86_DECODE_CMD_FDIV, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xde, 7, 0, X86_DECODE_CMD_FDIV, 2, true, false, decode_x87_modrm_st0, decode_x87_modrm_intp, NULL, RFLAGS_MASK_NONE},
> +
> + {0xdf, 0, 0, X86_DECODE_CMD_FLD, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 1, 3, X86_DECODE_CMD_FXCH, 10, false, false, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 2, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 2, 0, X86_DECODE_CMD_FST, 2, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 3, 3, X86_DECODE_CMD_FST, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 3, 0, X86_DECODE_CMD_FST, 2, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 4, 3, X86_DECODE_CMD_FNSTSW, 2, false, true, decode_x87_modrm_bytep, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 5, 3, X86_DECODE_CMD_FUCOMI, 10, false, true, decode_x87_modrm_st0, decode_x87_modrm_st0, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 5, 0, X86_DECODE_CMD_FLD, 8, false, false, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> + {0xdf, 7, 0, X86_DECODE_CMD_FST, 8, false, true, decode_x87_modrm_intp, NULL, NULL, RFLAGS_MASK_NONE},
> +};
> +
> +void calc_modrm_operand16(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + addr_t ptr = 0;
> + x86_reg_segment seg = REG_SEG_DS;
> +
> + if (!decode->modrm.mod && 6 == decode->modrm.rm) {
> + op->ptr = (uint16_t)decode->displacement;
> + goto calc_addr;
> + }
> +
> + if (decode->displacement_size)
> + ptr = sign(decode->displacement, decode->displacement_size);
> +
> + switch (decode->modrm.rm) {
> + case 0:
> + ptr += BX(cpu) + SI(cpu);
> + break;
> + case 1:
> + ptr += BX(cpu) + DI(cpu);
> + break;
> + case 2:
> + ptr += BP(cpu) + SI(cpu);
> + seg = REG_SEG_SS;
> + break;
> + case 3:
> + ptr += BP(cpu) + DI(cpu);
> + seg = REG_SEG_SS;
> + break;
> + case 4:
> + ptr += SI(cpu);
> + break;
> + case 5:
> + ptr += DI(cpu);
> + break;
> + case 6:
> + ptr += BP(cpu);
> + seg = REG_SEG_SS;
> + break;
> + case 7:
> + ptr += BX(cpu);
> + break;
> + }
> +calc_addr:
> + if (X86_DECODE_CMD_LEA == decode->cmd)
> + op->ptr = (uint16_t)ptr;
> + else
> + op->ptr = decode_linear_addr(cpu, decode, (uint16_t)ptr, seg);
> +}
> +
> +addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size)
> +{
> + addr_t ptr = 0;
> + int which = 0;
> +
> + if (is_extended)
> + reg |= REG_R8;
> +
> +
> + switch (size) {
> + case 1:
> + if (is_extended || reg < 4) {
> + which = 1;
> + ptr = (addr_t)&RL(cpu, reg);
> + } else {
> + which = 2;
> + ptr = (addr_t)&RH(cpu, reg - 4);
> + }
> + break;
> + default:
> + which = 3;
> + ptr = (addr_t)&RRX(cpu, reg);
> + break;
> + }
> + return ptr;
> +}
> +
> +addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size)
> +{
> + addr_t val = 0;
> + memcpy(&val, (void*)get_reg_ref(cpu, reg, is_extended, size), size);
> + return val;
> +}
> +
> +static addr_t get_sib_val(CPUState *cpu, struct x86_decode *decode, x86_reg_segment *sel)
> +{
> + addr_t base = 0;
> + addr_t scaled_index = 0;
> + int addr_size = decode->addressing_size;
> + int base_reg = decode->sib.base;
> + int index_reg = decode->sib.index;
> +
> + *sel = REG_SEG_DS;
> +
> + if (decode->modrm.mod || base_reg != REG_RBP) {
> + if (decode->rex.b)
> + base_reg |= REG_R8;
> + if (REG_RSP == base_reg || REG_RBP == base_reg)
> + *sel = REG_SEG_SS;
> + base = get_reg_val(cpu, decode->sib.base, decode->rex.b, addr_size);
> + }
> +
> + if (decode->rex.x)
> + index_reg |= REG_R8;
> +
> + if (index_reg != REG_RSP)
> + scaled_index = get_reg_val(cpu, index_reg, decode->rex.x, addr_size) << decode->sib.scale;
> + return base + scaled_index;
> +}
> +
> +void calc_modrm_operand32(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + x86_reg_segment seg = REG_SEG_DS;
> + addr_t ptr = 0;
> + int addr_size = decode->addressing_size;
> +
> + if (decode->displacement_size)
> + ptr = sign(decode->displacement, decode->displacement_size);
> +
> + if (4 == decode->modrm.rm) {
> + ptr += get_sib_val(cpu, decode, &seg);
> + }
> + else if (!decode->modrm.mod && 5 == decode->modrm.rm) {
> + if (x86_is_long_mode(cpu))
> + ptr += RIP(cpu) + decode->len;
> + else
> + ptr = decode->displacement;
> + }
> + else {
> + if (REG_RBP == decode->modrm.rm || REG_RSP == decode->modrm.rm)
> + seg = REG_SEG_SS;
> + ptr += get_reg_val(cpu, decode->modrm.rm, decode->rex.b, addr_size);
> + }
> +
> + if (X86_DECODE_CMD_LEA == decode->cmd)
> + op->ptr = (uint32_t)ptr;
> + else
> + op->ptr = decode_linear_addr(cpu, decode, (uint32_t)ptr, seg);
> +}
> +
> +void calc_modrm_operand64(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + x86_reg_segment seg = REG_SEG_DS;
> + int32_t offset = 0;
> + int mod = decode->modrm.mod;
> + int rm = decode->modrm.rm;
> + addr_t ptr;
> + int src = decode->modrm.rm;
> +
> + if (decode->displacement_size)
> + offset = sign(decode->displacement, decode->displacement_size);
> +
> + if (4 == rm)
> + ptr = get_sib_val(cpu, decode, &seg) + offset;
> + else if (0 == mod && 5 == rm)
> + ptr = RIP(cpu) + decode->len + (int32_t) offset;
> + else
> + ptr = get_reg_val(cpu, src, decode->rex.b, 8) + (int64_t) offset;
> +
> + if (X86_DECODE_CMD_LEA == decode->cmd)
> + op->ptr = ptr;
> + else
> + op->ptr = decode_linear_addr(cpu, decode, ptr, seg);
> +}
> +
> +
> +void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op)
> +{
> + if (3 == decode->modrm.mod) {
> + op->reg = decode->modrm.reg;
> + op->type = X86_VAR_REG;
> + op->ptr = get_reg_ref(cpu, decode->modrm.rm, decode->rex.b, decode->operand_size);
> + return;
> + }
> +
> + switch (decode->addressing_size) {
> + case 2:
> + calc_modrm_operand16(cpu, decode, op);
> + break;
> + case 4:
> + calc_modrm_operand32(cpu, decode, op);
> + break;
> + case 8:
> + calc_modrm_operand64(cpu, decode, op);
> + break;
> + default:
> + VM_PANIC_EX("unsupported address size %d\n", decode->addressing_size);
> + break;
> + }
> +}
> +
> +static void decode_prefix(CPUState *cpu, struct x86_decode *decode)
> +{
> + while (1) {
> + uint8_t byte = decode_byte(cpu, decode);
> + switch (byte) {
> + case PREFIX_LOCK:
> + decode->lock = byte;
> + break;
> + case PREFIX_REPN:
> + case PREFIX_REP:
> + decode->rep = byte;
> + break;
> + case PREFIX_CS_SEG_OVEERIDE:
> + case PREFIX_SS_SEG_OVEERIDE:
> + case PREFIX_DS_SEG_OVEERIDE:
> + case PREFIX_ES_SEG_OVEERIDE:
> + case PREFIX_FS_SEG_OVEERIDE:
> + case PREFIX_GS_SEG_OVEERIDE:
> + decode->segment_override = byte;
> + break;
> + case PREFIX_OP_SIZE_OVERRIDE:
> + decode->op_size_override = byte;
> + break;
> + case PREFIX_ADDR_SIZE_OVERRIDE:
> + decode->addr_size_override = byte;
> + break;
> + case PREFIX_REX ... (PREFIX_REX + 0xf):
> + if (x86_is_long_mode(cpu)) {
> + decode->rex.rex = byte;
> + break;
> + }
> + // fall through when not in long mode
> + default:
> + decode->len--;
> + return;
> + }
> + }
> +}
> +
> +void set_addressing_size(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->addressing_size = -1;
> + if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
> + if (decode->addr_size_override)
> + decode->addressing_size = 4;
> + else
> + decode->addressing_size = 2;
> + }
> + else if (!x86_is_long_mode(cpu)) {
> + // protected
> + struct vmx_segment cs;
> + vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
> + // check db
> + if ((cs.ar >> 14) & 1) {
> + if (decode->addr_size_override)
> + decode->addressing_size = 2;
> + else
> + decode->addressing_size = 4;
> + } else {
> + if (decode->addr_size_override)
> + decode->addressing_size = 4;
> + else
> + decode->addressing_size = 2;
> + }
> + } else {
> + // long
> + if (decode->addr_size_override)
> + decode->addressing_size = 4;
> + else
> + decode->addressing_size = 8;
> + }
> +}
> +
> +void set_operand_size(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->operand_size = -1;
> + if (x86_is_real(cpu) || x86_is_v8086(cpu)) {
> + if (decode->op_size_override)
> + decode->operand_size = 4;
> + else
> + decode->operand_size = 2;
> + }
> + else if (!x86_is_long_mode(cpu)) {
> + // protected
> + struct vmx_segment cs;
> + vmx_read_segment_descriptor(cpu, &cs, REG_SEG_CS);
> + // check db
> + if ((cs.ar >> 14) & 1) {
> + if (decode->op_size_override)
> + decode->operand_size = 2;
> + else
> + decode->operand_size = 4;
> + } else {
> + if (decode->op_size_override)
> + decode->operand_size = 4;
> + else
> + decode->operand_size = 2;
> + }
> + } else {
> + // long
> + if (decode->op_size_override)
> + decode->operand_size = 2;
> + else
> + decode->operand_size = 4;
> +
> + if (decode->rex.w)
> + decode->operand_size = 8;
> + }
> +}
> +
> +static void decode_sib(CPUState *cpu, struct x86_decode *decode)
> +{
> + if ((decode->modrm.mod != 3) && (4 == decode->modrm.rm) && (decode->addressing_size != 2)) {
> + decode->sib.sib = decode_byte(cpu, decode);
> + decode->sib_present = true;
> + }
> +}
> +
> +/* 16 bit modrm
> + * mod R/M
> + * 00 [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] [disp16] [BX]
> + * 01 [BX+SI+disp8] [BX+DI+disp8] [BP+SI+disp8] [BP+DI+disp8] [SI+disp8] [DI+disp8] [BP+disp8] [BX+disp8]
> + * 10 [BX+SI+disp16] [BX+DI+disp16] [BP+SI+disp16] [BP+DI+disp16] [SI+disp16] [DI+disp16] [BP+disp16] [BX+disp16]
> + * 11 - - - - - - - -
> + */
> +int disp16_tbl[4][8] =
> + {{0, 0, 0, 0, 0, 0, 2, 0},
> + {1, 1, 1, 1, 1, 1, 1, 1},
> + {2, 2, 2, 2, 2, 2, 2, 2},
> + {0, 0, 0, 0, 0, 0, 0, 0}};
> +
> +/*
> + 32/64-bit modrm
> + Mod
> + 00 [r/m] [r/m] [r/m] [r/m] [SIB] [RIP/EIP1,2+disp32] [r/m] [r/m]
> + 01 [r/m+disp8] [r/m+disp8] [r/m+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8] [SIB+disp8] [r/m+disp8]
> + 10 [r/m+disp32] [r/m+disp32] [r/m+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32] [SIB+disp32] [r/m+disp32]
> + 11 - - - - - - - -
> + */
> +int disp32_tbl[4][8] =
> + {{0, 0, 0, 0, -1, 4, 0, 0},
> + {1, 1, 1, 1, 1, 1, 1, 1},
> + {4, 4, 4, 4, 4, 4, 4, 4},
> + {0, 0, 0, 0, 0, 0, 0, 0}};
> +
> +static inline void decode_displacement(CPUState *cpu, struct x86_decode *decode)
> +{
> + int addressing_size = decode->addressing_size;
> + int mod = decode->modrm.mod;
> + int rm = decode->modrm.rm;
> +
> + decode->displacement_size = 0;
> + switch (addressing_size) {
> + case 2:
> + decode->displacement_size = disp16_tbl[mod][rm];
> + if (decode->displacement_size)
> + decode->displacement = (uint16_t)decode_bytes(cpu, decode, decode->displacement_size);
> + break;
> + case 4:
> + case 8:
> + if (-1 == disp32_tbl[mod][rm]) {
> + if (5 == decode->sib.base)
> + decode->displacement_size = 4;
> + }
> + else
> + decode->displacement_size = disp32_tbl[mod][rm];
> +
> + if (decode->displacement_size)
> + decode->displacement = (uint32_t)decode_bytes(cpu, decode, decode->displacement_size);
> + break;
> + }
> +}
> +
> +static inline void decode_modrm(CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->modrm.modrm = decode_byte(cpu, decode);
> + decode->is_modrm = true;
> +
> + decode_sib(cpu, decode);
> + decode_displacement(cpu, decode);
> +}
> +
> +static inline void decode_opcode_general(CPUState *cpu, struct x86_decode *decode, uint8_t opcode, struct decode_tbl *inst_decoder)
> +{
> + decode->cmd = inst_decoder->cmd;
> + if (inst_decoder->operand_size)
> + decode->operand_size = inst_decoder->operand_size;
> + decode->flags_mask = inst_decoder->flags_mask;
> +
> + if (inst_decoder->is_modrm)
> + decode_modrm(cpu, decode);
> + if (inst_decoder->decode_op1)
> + inst_decoder->decode_op1(cpu, decode, &decode->op[0]);
> + if (inst_decoder->decode_op2)
> + inst_decoder->decode_op2(cpu, decode, &decode->op[1]);
> + if (inst_decoder->decode_op3)
> + inst_decoder->decode_op3(cpu, decode, &decode->op[2]);
> + if (inst_decoder->decode_op4)
> + inst_decoder->decode_op4(cpu, decode, &decode->op[3]);
> + if (inst_decoder->decode_postfix)
> + inst_decoder->decode_postfix(cpu, decode);
> +}
> +
> +static inline void decode_opcode_1(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
> +{
> + struct decode_tbl *inst_decoder = &_decode_tbl1[opcode];
> + decode_opcode_general(cpu, decode, opcode, inst_decoder);
> +}
> +
> +
> +static inline void decode_opcode_2(CPUState *cpu, struct x86_decode *decode, uint8_t opcode)
> +{
> + struct decode_tbl *inst_decoder = &_decode_tbl2[opcode];
> + decode_opcode_general(cpu, decode, opcode, inst_decoder);
> +}
> +
> +static void decode_opcodes(CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t opcode;
> +
> + opcode = decode_byte(cpu, decode);
> + decode->opcode[decode->opcode_len++] = opcode;
> + if (opcode != OPCODE_ESCAPE) {
> + decode_opcode_1(cpu, decode, opcode);
> + } else {
> + opcode = decode_byte(cpu, decode);
> + decode->opcode[decode->opcode_len++] = opcode;
> + decode_opcode_2(cpu, decode, opcode);
> + }
> +}
> +
> +uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode)
> +{
> + ZERO_INIT(*decode);
> +
> + decode_prefix(cpu, decode);
> + set_addressing_size(cpu, decode);
> + set_operand_size(cpu, decode);
> +
> + decode_opcodes(cpu, decode);
> +
> + return decode->len;
> +}
> +
> +void init_decoder(CPUState *cpu)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
> + memcpy(_decode_tbl1, &invl_inst, sizeof(invl_inst));
> + for (i = 0; i < ARRAY_SIZE(_decode_tbl2); i++)
> + memcpy(_decode_tbl2, &invl_inst, sizeof(invl_inst));
> + for (i = 0; i < ARRAY_SIZE(_decode_tbl3); i++)
> + memcpy(_decode_tbl3, &invl_inst, sizeof(invl_inst_x87));
> +
> + for (i = 0; i < ARRAY_SIZE(_1op_inst); i++) {
> + _decode_tbl1[_1op_inst[i].opcode] = _1op_inst[i];
> + }
> + for (i = 0; i < ARRAY_SIZE(_2op_inst); i++) {
> + _decode_tbl2[_2op_inst[i].opcode] = _2op_inst[i];
> + }
> + for (i = 0; i < ARRAY_SIZE(_x87_inst); i++) {
> + int index = ((_x87_inst[i].opcode & 0xf) << 4) | ((_x87_inst[i].modrm_mod & 1) << 3) | _x87_inst[i].modrm_reg;
> + _decode_tbl3[index] = _x87_inst[i];
> + }
> +}
> +
> +
> +const char *decode_cmd_to_string(enum x86_decode_cmd cmd)
> +{
> + static const char *cmds[] = {"INVL", "PUSH", "PUSH_SEG", "POP", "POP_SEG", "MOV", "MOVSX", "MOVZX", "CALL_NEAR",
> + "CALL_NEAR_ABS_INDIRECT", "CALL_FAR_ABS_INDIRECT", "CMD_CALL_FAR", "RET_NEAR", "RET_FAR", "ADD", "OR",
> + "ADC", "SBB", "AND", "SUB", "XOR", "CMP", "INC", "DEC", "TST", "NOT", "NEG", "JMP_NEAR", "JMP_NEAR_ABS_INDIRECT",
> + "JMP_FAR", "JMP_FAR_ABS_INDIRECT", "LEA", "JXX",
> + "JCXZ", "SETXX", "MOV_TO_SEG", "MOV_FROM_SEG", "CLI", "STI", "CLD", "STD", "STC",
> + "CLC", "OUT", "IN", "INS", "OUTS", "LIDT", "SIDT", "LGDT", "SGDT", "SMSW", "LMSW", "RDTSCP", "INVLPG", "MOV_TO_CR",
> + "MOV_FROM_CR", "MOV_TO_DR", "MOV_FROM_DR", "PUSHF", "POPF", "CPUID", "ROL", "ROR", "RCL", "RCR", "SHL", "SAL",
> + "SHR","SHRD", "SHLD", "SAR", "DIV", "IDIV", "MUL", "IMUL_3", "IMUL_2", "IMUL_1", "MOVS", "CMPS", "SCAS",
> + "LODS", "STOS", "BSWAP", "XCHG", "RDTSC", "RDMSR", "WRMSR", "ENTER", "LEAVE", "BT", "BTS", "BTC", "BTR", "BSF",
> + "BSR", "IRET", "INT", "POPA", "PUSHA", "CWD", "CBW", "DAS", "AAD", "AAM", "AAS", "LOOP", "SLDT", "STR", "LLDT",
> + "LTR", "VERR", "VERW", "SAHF", "LAHF", "WBINVD", "LDS", "LSS", "LES", "LGS", "LFS", "CMC", "XLAT", "NOP", "CMOV",
> + "CLTS", "XADD", "HLT", "CMPXCHG8B", "CMPXCHG", "POPCNT",
> + "FNINIT", "FLD", "FLDxx", "FNSTCW", "FNSTSW", "FNSETPM", "FSAVE", "FRSTOR", "FXSAVE", "FXRSTOR", "FDIV", "FMUL",
> + "FSUB", "FADD", "EMMS", "MFENCE", "SFENCE", "LFENCE", "PREFETCH", "FST", "FABS", "FUCOM", "FUCOMI", "FLDCW",
> + "FXCH", "FCHS", "FCMOV", "FRNDINT", "FXAM", "LAST"};
> + return cmds[cmd];
> +}
> +
> +addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg)
> +{
> + switch (decode->segment_override) {
> + case PREFIX_CS_SEG_OVEERIDE:
> + seg = REG_SEG_CS;
> + break;
> + case PREFIX_SS_SEG_OVEERIDE:
> + seg = REG_SEG_SS;
> + break;
> + case PREFIX_DS_SEG_OVEERIDE:
> + seg = REG_SEG_DS;
> + break;
> + case PREFIX_ES_SEG_OVEERIDE:
> + seg = REG_SEG_ES;
> + break;
> + case PREFIX_FS_SEG_OVEERIDE:
> + seg = REG_SEG_FS;
> + break;
> + case PREFIX_GS_SEG_OVEERIDE:
> + seg = REG_SEG_GS;
> + break;
> + default:
> + break;
> + }
> + return linear_addr_size(cpu, addr, decode->addressing_size, seg);
> +}
> diff --git a/target/i386/hvf-utils/x86_decode.h b/target/i386/hvf-utils/x86_decode.h
> new file mode 100644
> index 0000000000..3a22d7d1a5
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_decode.h
> @@ -0,0 +1,314 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#pragma once
> +
> +#include <sys/types.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <stdarg.h>
> +#include "qemu-common.h"
> +#include "x86.h"
> +
> +typedef enum x86_prefix {
> + // group 1
> + PREFIX_LOCK = 0xf0,
> + PREFIX_REPN = 0xf2,
> + PREFIX_REP = 0xf3,
> + // group 2
> + PREFIX_CS_SEG_OVEERIDE = 0x2e,
> + PREFIX_SS_SEG_OVEERIDE = 0x36,
> + PREFIX_DS_SEG_OVEERIDE = 0x3e,
> + PREFIX_ES_SEG_OVEERIDE = 0x26,
> + PREFIX_FS_SEG_OVEERIDE = 0x64,
> + PREFIX_GS_SEG_OVEERIDE = 0x65,
> + // group 3
> + PREFIX_OP_SIZE_OVERRIDE = 0x66,
> + // group 4
> + PREFIX_ADDR_SIZE_OVERRIDE = 0x67,
> +
> + PREFIX_REX = 0x40,
> +} x86_prefix;
> +
> +enum x86_decode_cmd {
> + X86_DECODE_CMD_INVL = 0,
> +
> + X86_DECODE_CMD_PUSH,
> + X86_DECODE_CMD_PUSH_SEG,
> + X86_DECODE_CMD_POP,
> + X86_DECODE_CMD_POP_SEG,
> + X86_DECODE_CMD_MOV,
> + X86_DECODE_CMD_MOVSX,
> + X86_DECODE_CMD_MOVZX,
> + X86_DECODE_CMD_CALL_NEAR,
> + X86_DECODE_CMD_CALL_NEAR_ABS_INDIRECT,
> + X86_DECODE_CMD_CALL_FAR_ABS_INDIRECT,
> + X86_DECODE_CMD_CALL_FAR,
> + X86_DECODE_RET_NEAR,
> + X86_DECODE_RET_FAR,
> + X86_DECODE_CMD_ADD,
> + X86_DECODE_CMD_OR,
> + X86_DECODE_CMD_ADC,
> + X86_DECODE_CMD_SBB,
> + X86_DECODE_CMD_AND,
> + X86_DECODE_CMD_SUB,
> + X86_DECODE_CMD_XOR,
> + X86_DECODE_CMD_CMP,
> + X86_DECODE_CMD_INC,
> + X86_DECODE_CMD_DEC,
> + X86_DECODE_CMD_TST,
> + X86_DECODE_CMD_NOT,
> + X86_DECODE_CMD_NEG,
> + X86_DECODE_CMD_JMP_NEAR,
> + X86_DECODE_CMD_JMP_NEAR_ABS_INDIRECT,
> + X86_DECODE_CMD_JMP_FAR,
> + X86_DECODE_CMD_JMP_FAR_ABS_INDIRECT,
> + X86_DECODE_CMD_LEA,
> + X86_DECODE_CMD_JXX,
> + X86_DECODE_CMD_JCXZ,
> + X86_DECODE_CMD_SETXX,
> + X86_DECODE_CMD_MOV_TO_SEG,
> + X86_DECODE_CMD_MOV_FROM_SEG,
> + X86_DECODE_CMD_CLI,
> + X86_DECODE_CMD_STI,
> + X86_DECODE_CMD_CLD,
> + X86_DECODE_CMD_STD,
> + X86_DECODE_CMD_STC,
> + X86_DECODE_CMD_CLC,
> + X86_DECODE_CMD_OUT,
> + X86_DECODE_CMD_IN,
> + X86_DECODE_CMD_INS,
> + X86_DECODE_CMD_OUTS,
> + X86_DECODE_CMD_LIDT,
> + X86_DECODE_CMD_SIDT,
> + X86_DECODE_CMD_LGDT,
> + X86_DECODE_CMD_SGDT,
> + X86_DECODE_CMD_SMSW,
> + X86_DECODE_CMD_LMSW,
> + X86_DECODE_CMD_RDTSCP,
> + X86_DECODE_CMD_INVLPG,
> + X86_DECODE_CMD_MOV_TO_CR,
> + X86_DECODE_CMD_MOV_FROM_CR,
> + X86_DECODE_CMD_MOV_TO_DR,
> + X86_DECODE_CMD_MOV_FROM_DR,
> + X86_DECODE_CMD_PUSHF,
> + X86_DECODE_CMD_POPF,
> + X86_DECODE_CMD_CPUID,
> + X86_DECODE_CMD_ROL,
> + X86_DECODE_CMD_ROR,
> + X86_DECODE_CMD_RCL,
> + X86_DECODE_CMD_RCR,
> + X86_DECODE_CMD_SHL,
> + X86_DECODE_CMD_SAL,
> + X86_DECODE_CMD_SHR,
> + X86_DECODE_CMD_SHRD,
> + X86_DECODE_CMD_SHLD,
> + X86_DECODE_CMD_SAR,
> + X86_DECODE_CMD_DIV,
> + X86_DECODE_CMD_IDIV,
> + X86_DECODE_CMD_MUL,
> + X86_DECODE_CMD_IMUL_3,
> + X86_DECODE_CMD_IMUL_2,
> + X86_DECODE_CMD_IMUL_1,
> + X86_DECODE_CMD_MOVS,
> + X86_DECODE_CMD_CMPS,
> + X86_DECODE_CMD_SCAS,
> + X86_DECODE_CMD_LODS,
> + X86_DECODE_CMD_STOS,
> + X86_DECODE_CMD_BSWAP,
> + X86_DECODE_CMD_XCHG,
> + X86_DECODE_CMD_RDTSC,
> + X86_DECODE_CMD_RDMSR,
> + X86_DECODE_CMD_WRMSR,
> + X86_DECODE_CMD_ENTER,
> + X86_DECODE_CMD_LEAVE,
> + X86_DECODE_CMD_BT,
> + X86_DECODE_CMD_BTS,
> + X86_DECODE_CMD_BTC,
> + X86_DECODE_CMD_BTR,
> + X86_DECODE_CMD_BSF,
> + X86_DECODE_CMD_BSR,
> + X86_DECODE_CMD_IRET,
> + X86_DECODE_CMD_INT,
> + X86_DECODE_CMD_POPA,
> + X86_DECODE_CMD_PUSHA,
> + X86_DECODE_CMD_CWD,
> + X86_DECODE_CMD_CBW,
> + X86_DECODE_CMD_DAS,
> + X86_DECODE_CMD_AAD,
> + X86_DECODE_CMD_AAM,
> + X86_DECODE_CMD_AAS,
> + X86_DECODE_CMD_LOOP,
> + X86_DECODE_CMD_SLDT,
> + X86_DECODE_CMD_STR,
> + X86_DECODE_CMD_LLDT,
> + X86_DECODE_CMD_LTR,
> + X86_DECODE_CMD_VERR,
> + X86_DECODE_CMD_VERW,
> + X86_DECODE_CMD_SAHF,
> + X86_DECODE_CMD_LAHF,
> + X86_DECODE_CMD_WBINVD,
> + X86_DECODE_CMD_LDS,
> + X86_DECODE_CMD_LSS,
> + X86_DECODE_CMD_LES,
> + X86_DECODE_XMD_LGS,
> + X86_DECODE_CMD_LFS,
> + X86_DECODE_CMD_CMC,
> + X86_DECODE_CMD_XLAT,
> + X86_DECODE_CMD_NOP,
> + X86_DECODE_CMD_CMOV,
> + X86_DECODE_CMD_CLTS,
> + X86_DECODE_CMD_XADD,
> + X86_DECODE_CMD_HLT,
> + X86_DECODE_CMD_CMPXCHG8B,
> + X86_DECODE_CMD_CMPXCHG,
> + X86_DECODE_CMD_POPCNT,
> +
> + X86_DECODE_CMD_FNINIT,
> + X86_DECODE_CMD_FLD,
> + X86_DECODE_CMD_FLDxx,
> + X86_DECODE_CMD_FNSTCW,
> + X86_DECODE_CMD_FNSTSW,
> + X86_DECODE_CMD_FNSETPM,
> + X86_DECODE_CMD_FSAVE,
> + X86_DECODE_CMD_FRSTOR,
> + X86_DECODE_CMD_FXSAVE,
> + X86_DECODE_CMD_FXRSTOR,
> + X86_DECODE_CMD_FDIV,
> + X86_DECODE_CMD_FMUL,
> + X86_DECODE_CMD_FSUB,
> + X86_DECODE_CMD_FADD,
> + X86_DECODE_CMD_EMMS,
> + X86_DECODE_CMD_MFENCE,
> + X86_DECODE_CMD_SFENCE,
> + X86_DECODE_CMD_LFENCE,
> + X86_DECODE_CMD_PREFETCH,
> + X86_DECODE_CMD_CLFLUSH,
> + X86_DECODE_CMD_FST,
> + X86_DECODE_CMD_FABS,
> + X86_DECODE_CMD_FUCOM,
> + X86_DECODE_CMD_FUCOMI,
> + X86_DECODE_CMD_FLDCW,
> + X86_DECODE_CMD_FXCH,
> + X86_DECODE_CMD_FCHS,
> + X86_DECODE_CMD_FCMOV,
> + X86_DECODE_CMD_FRNDINT,
> + X86_DECODE_CMD_FXAM,
> +
> + X86_DECODE_CMD_LAST,
> +};
> +
> +const char *decode_cmd_to_string(enum x86_decode_cmd cmd);
> +
> +typedef struct x86_modrm {
> + union {
> + uint8_t modrm;
> + struct {
> + uint8_t rm:3;
> + uint8_t reg:3;
> + uint8_t mod:2;
> + };
> + };
> +} __attribute__ ((__packed__)) x86_modrm;
> +
> +typedef struct x86_sib {
> + union {
> + uint8_t sib;
> + struct {
> + uint8_t base:3;
> + uint8_t index:3;
> + uint8_t scale:2;
> + };
> + };
> +} __attribute__ ((__packed__)) x86_sib;
> +
> +typedef struct x86_rex {
> + union {
> + uint8_t rex;
> + struct {
> + uint8_t b:1;
> + uint8_t x:1;
> + uint8_t r:1;
> + uint8_t w:1;
> + uint8_t unused:4;
> + };
> + };
> +} __attribute__ ((__packed__)) x86_rex;
> +
> +typedef enum x86_var_type {
> + X86_VAR_IMMEDIATE,
> + X86_VAR_OFFSET,
> + X86_VAR_REG,
> + X86_VAR_RM,
> +
> + // for floating point computations
> + X87_VAR_REG,
> + X87_VAR_FLOATP,
> + X87_VAR_INTP,
> + X87_VAR_BYTEP,
> +} x86_var_type;
> +
> +typedef struct x86_decode_op {
> + enum x86_var_type type;
> + int size;
> +
> + int reg;
> + addr_t val;
> +
> + addr_t ptr;
> +} x86_decode_op;
> +
> +typedef struct x86_decode {
> + int len;
> + uint8_t opcode[4];
> + uint8_t opcode_len;
> + enum x86_decode_cmd cmd;
> + int addressing_size;
> + int operand_size;
> + int lock;
> + int rep;
> + int op_size_override;
> + int addr_size_override;
> + int segment_override;
> + int control_change_inst;
> + bool fwait;
> + bool fpop_stack;
> + bool frev;
> +
> + uint32_t displacement;
> + uint8_t displacement_size;
> + struct x86_rex rex;
> + bool is_modrm;
> + bool sib_present;
> + struct x86_sib sib;
> + struct x86_modrm modrm;
> + struct x86_decode_op op[4];
> + bool is_fpu;
> + addr_t flags_mask;
> +
> +} x86_decode;
> +
> +uint64_t sign(uint64_t val, int size);
> +
> +uint32_t decode_instruction(CPUState *cpu, struct x86_decode *decode);
> +
> +addr_t get_reg_ref(CPUState *cpu, int reg, int is_extended, int size);
> +addr_t get_reg_val(CPUState *cpu, int reg, int is_extended, int size);
> +void calc_modrm_operand(CPUState *cpu, struct x86_decode *decode, struct x86_decode_op *op);
> +addr_t decode_linear_addr(struct CPUState *cpu, struct x86_decode *decode, addr_t addr, x86_reg_segment seg);
> +
> +void init_decoder(CPUState* cpu);
> diff --git a/target/i386/hvf-utils/x86_descr.c b/target/i386/hvf-utils/x86_descr.c
> new file mode 100644
> index 0000000000..c3b089aaa8
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_descr.c
> @@ -0,0 +1,124 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "vmx.h"
> +#include "x86_descr.h"
> +
> +#define VMX_SEGMENT_FIELD(seg) \
> + [REG_SEG_##seg] = { \
> + .selector = VMCS_GUEST_##seg##_SELECTOR, \
> + .base = VMCS_GUEST_##seg##_BASE, \
> + .limit = VMCS_GUEST_##seg##_LIMIT, \
> + .ar_bytes = VMCS_GUEST_##seg##_ACCESS_RIGHTS, \
> +}
> +
> +static const struct vmx_segment_field {
> + int selector;
> + int base;
> + int limit;
> + int ar_bytes;
> +} vmx_segment_fields[] = {
> + VMX_SEGMENT_FIELD(ES),
> + VMX_SEGMENT_FIELD(CS),
> + VMX_SEGMENT_FIELD(SS),
> + VMX_SEGMENT_FIELD(DS),
> + VMX_SEGMENT_FIELD(FS),
> + VMX_SEGMENT_FIELD(GS),
> + VMX_SEGMENT_FIELD(LDTR),
> + VMX_SEGMENT_FIELD(TR),
> +};
> +
> +uint32_t vmx_read_segment_limit(CPUState *cpu, x86_reg_segment seg)
> +{
> + return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit);
> +}
> +
> +uint32_t vmx_read_segment_ar(CPUState *cpu, x86_reg_segment seg)
> +{
> + return (uint32_t)rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes);
> +}
> +
> +uint64_t vmx_read_segment_base(CPUState *cpu, x86_reg_segment seg)
> +{
> + return rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base);
> +}
> +
> +x68_segment_selector vmx_read_segment_selector(CPUState *cpu, x86_reg_segment seg)
> +{
> + x68_segment_selector sel;
> + sel.sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector);
> + return sel;
> +}
> +
> +void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg)
> +{
> + wvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector, selector.sel);
> +}
> +
> +void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg)
> +{
> + desc->sel = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].selector);
> + desc->base = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].base);
> + desc->limit = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].limit);
> + desc->ar = rvmcs(cpu->hvf_fd, vmx_segment_fields[seg].ar_bytes);
> +}
> +
> +void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg)
> +{
> + const struct vmx_segment_field *sf = &vmx_segment_fields[seg];
> +
> + wvmcs(cpu->hvf_fd, sf->base, desc->base);
> + wvmcs(cpu->hvf_fd, sf->limit, desc->limit);
> + wvmcs(cpu->hvf_fd, sf->selector, desc->sel);
> + wvmcs(cpu->hvf_fd, sf->ar_bytes, desc->ar);
> +}
> +
> +void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc)
> +{
> + vmx_desc->sel = selector.sel;
> + vmx_desc->base = x86_segment_base(desc);
> + vmx_desc->limit = x86_segment_limit(desc);
> +
> + vmx_desc->ar = (selector.sel ? 0 : 1) << 16 |
> + desc->g << 15 |
> + desc->db << 14 |
> + desc->l << 13 |
> + desc->avl << 12 |
> + desc->p << 7 |
> + desc->dpl << 5 |
> + desc->s << 4 |
> + desc->type;
> +}
> +
> +void vmx_segment_to_x86_descriptor(struct CPUState *cpu, struct vmx_segment *vmx_desc, struct x86_segment_descriptor *desc)
> +{
> + x86_set_segment_limit(desc, vmx_desc->limit);
> + x86_set_segment_base(desc, vmx_desc->base);
> +
> + desc->type = vmx_desc->ar & 15;
> + desc->s = (vmx_desc->ar >> 4) & 1;
> + desc->dpl = (vmx_desc->ar >> 5) & 3;
> + desc->p = (vmx_desc->ar >> 7) & 1;
> + desc->avl = (vmx_desc->ar >> 12) & 1;
> + desc->l = (vmx_desc->ar >> 13) & 1;
> + desc->db = (vmx_desc->ar >> 14) & 1;
> + desc->g = (vmx_desc->ar >> 15) & 1;
> +}
> +
> diff --git a/target/i386/hvf-utils/x86_descr.h b/target/i386/hvf-utils/x86_descr.h
> new file mode 100644
> index 0000000000..78fb1bc420
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_descr.h
> @@ -0,0 +1,40 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#pragma once
> +
> +#include "x86.h"
> +
> +typedef struct vmx_segment {
> + uint16_t sel;
> + uint64_t base;
> + uint64_t limit;
> + uint64_t ar;
> +} vmx_segment;
> +
> +// deal with vmstate descriptors
> +void vmx_read_segment_descriptor(struct CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
> +void vmx_write_segment_descriptor(CPUState *cpu, struct vmx_segment *desc, x86_reg_segment seg);
> +
> +x68_segment_selector vmx_read_segment_selector(struct CPUState *cpu, x86_reg_segment seg);
> +void vmx_write_segment_selector(struct CPUState *cpu, x68_segment_selector selector, x86_reg_segment seg);
> +
> +uint64_t vmx_read_segment_base(struct CPUState *cpu, x86_reg_segment seg);
> +void vmx_write_segment_base(struct CPUState *cpu, x86_reg_segment seg, uint64_t base);
> +
> +void x86_segment_descriptor_to_vmx(struct CPUState *cpu, x68_segment_selector selector, struct x86_segment_descriptor *desc, struct vmx_segment *vmx_desc);
> diff --git a/target/i386/hvf-utils/x86_emu.c b/target/i386/hvf-utils/x86_emu.c
> new file mode 100644
> index 0000000000..8b5efc76f0
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_emu.c
> @@ -0,0 +1,1466 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +/////////////////////////////////////////////////////////////////////////
> +//
> +// Copyright (C) 2001-2012 The Bochs Project
> +//
> +// This library is free software; you can redistribute it and/or
> +// modify it under the terms of the GNU Lesser General Public
> +// License as published by the Free Software Foundation; either
> +// version 2 of the License, or (at your option) any later version.
> +//
> +// This library is distributed in the hope that it will be useful,
> +// but WITHOUT ANY WARRANTY; without even the implied warranty of
> +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +// Lesser General Public License for more details.
> +//
> +// You should have received a copy of the GNU Lesser General Public
> +// License along with this library; if not, write to the Free Software
> +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
> +/////////////////////////////////////////////////////////////////////////
> +
> +#include "qemu/osdep.h"
> +
> +#include "qemu-common.h"
> +#include "x86_decode.h"
> +#include "x86.h"
> +#include "x86_emu.h"
> +#include "x86_mmu.h"
> +#include "vmcs.h"
> +#include "vmx.h"
> +
> +static void print_debug(struct CPUState *cpu);
> +void hvf_handle_io(struct CPUState *cpu, uint16_t port, void *data, int direction, int size, uint32_t count);
> +
> +#define EXEC_2OP_LOGIC_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
> +{ \
> + fetch_operands(cpu, decode, 2, true, true, false); \
> + switch (decode->operand_size) { \
> + case 1: \
> + { \
> + uint8_t v1 = (uint8_t)decode->op[0].val; \
> + uint8_t v2 = (uint8_t)decode->op[1].val; \
> + uint8_t diff = v1 cmd v2; \
> + if (save_res) \
> + write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
> + FLAGS_FUNC##_8(diff); \
> + break; \
> + } \
> + case 2: \
> + { \
> + uint16_t v1 = (uint16_t)decode->op[0].val; \
> + uint16_t v2 = (uint16_t)decode->op[1].val; \
> + uint16_t diff = v1 cmd v2; \
> + if (save_res) \
> + write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
> + FLAGS_FUNC##_16(diff); \
> + break; \
> + } \
> + case 4: \
> + { \
> + uint32_t v1 = (uint32_t)decode->op[0].val; \
> + uint32_t v2 = (uint32_t)decode->op[1].val; \
> + uint32_t diff = v1 cmd v2; \
> + if (save_res) \
> + write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
> + FLAGS_FUNC##_32(diff); \
> + break; \
> + } \
> + default: \
> + VM_PANIC("bad size\n"); \
> + } \
> +} \
> +
> +
> +#define EXEC_2OP_ARITH_CMD(cpu, decode, cmd, FLAGS_FUNC, save_res) \
> +{ \
> + fetch_operands(cpu, decode, 2, true, true, false); \
> + switch (decode->operand_size) { \
> + case 1: \
> + { \
> + uint8_t v1 = (uint8_t)decode->op[0].val; \
> + uint8_t v2 = (uint8_t)decode->op[1].val; \
> + uint8_t diff = v1 cmd v2; \
> + if (save_res) \
> + write_val_ext(cpu, decode->op[0].ptr, diff, 1); \
> + FLAGS_FUNC##_8(v1, v2, diff); \
> + break; \
> + } \
> + case 2: \
> + { \
> + uint16_t v1 = (uint16_t)decode->op[0].val; \
> + uint16_t v2 = (uint16_t)decode->op[1].val; \
> + uint16_t diff = v1 cmd v2; \
> + if (save_res) \
> + write_val_ext(cpu, decode->op[0].ptr, diff, 2); \
> + FLAGS_FUNC##_16(v1, v2, diff); \
> + break; \
> + } \
> + case 4: \
> + { \
> + uint32_t v1 = (uint32_t)decode->op[0].val; \
> + uint32_t v2 = (uint32_t)decode->op[1].val; \
> + uint32_t diff = v1 cmd v2; \
> + if (save_res) \
> + write_val_ext(cpu, decode->op[0].ptr, diff, 4); \
> + FLAGS_FUNC##_32(v1, v2, diff); \
> + break; \
> + } \
> + default: \
> + VM_PANIC("bad size\n"); \
> + } \
> +}
> +
> +addr_t read_reg(struct CPUState* cpu, int reg, int size)
> +{
> + switch (size) {
> + case 1:
> + return cpu->hvf_x86->regs[reg].lx;
> + case 2:
> + return cpu->hvf_x86->regs[reg].rx;
> + case 4:
> + return cpu->hvf_x86->regs[reg].erx;
> + case 8:
> + return cpu->hvf_x86->regs[reg].rrx;
> + default:
> + VM_PANIC_ON("read_reg size");
> + }
> + return 0;
> +}
> +
> +void write_reg(struct CPUState* cpu, int reg, addr_t val, int size)
> +{
> + switch (size) {
> + case 1:
> + cpu->hvf_x86->regs[reg].lx = val;
> + break;
> + case 2:
> + cpu->hvf_x86->regs[reg].rx = val;
> + break;
> + case 4:
> + cpu->hvf_x86->regs[reg].rrx = (uint32_t)val;
> + break;
> + case 8:
> + cpu->hvf_x86->regs[reg].rrx = val;
> + break;
> + default:
> + VM_PANIC_ON("write_reg size");
> + }
> +}
> +
> +addr_t read_val_from_reg(addr_t reg_ptr, int size)
> +{
> + addr_t val;
> +
> + switch (size) {
> + case 1:
> + val = *(uint8_t*)reg_ptr;
> + break;
> + case 2:
> + val = *(uint16_t*)reg_ptr;
> + break;
> + case 4:
> + val = *(uint32_t*)reg_ptr;
> + break;
> + case 8:
> + val = *(uint64_t*)reg_ptr;
> + break;
> + default:
> + VM_PANIC_ON_EX(1, "read_val: Unknown size %d\n", size);
> + break;
> + }
> + return val;
> +}
> +
> +void write_val_to_reg(addr_t reg_ptr, addr_t val, int size)
> +{
> + switch (size) {
> + case 1:
> + *(uint8_t*)reg_ptr = val;
> + break;
> + case 2:
> + *(uint16_t*)reg_ptr = val;
> + break;
> + case 4:
> + *(uint64_t*)reg_ptr = (uint32_t)val;
> + break;
> + case 8:
> + *(uint64_t*)reg_ptr = val;
> + break;
> + default:
> + VM_PANIC("write_val: Unknown size\n");
> + break;
> + }
> +}
> +
> +static bool is_host_reg(struct CPUState* cpu, addr_t ptr) {
> + return (ptr > (addr_t)cpu && ptr < (addr_t)cpu + sizeof(struct CPUState)) ||
> + (ptr > (addr_t)cpu->hvf_x86 && ptr < (addr_t)(cpu->hvf_x86 + sizeof(struct hvf_x86_state)));
> +}
> +
> +void write_val_ext(struct CPUState* cpu, addr_t ptr, addr_t val, int size)
> +{
> + if (is_host_reg(cpu, ptr)) {
> + write_val_to_reg(ptr, val, size);
> + return;
> + }
> + vmx_write_mem(cpu, ptr, &val, size);
> +}
> +
> +uint8_t *read_mmio(struct CPUState* cpu, addr_t ptr, int bytes)
> +{
> + vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, ptr, bytes);
> + return cpu->hvf_x86->mmio_buf;
> +}
> +
> +addr_t read_val_ext(struct CPUState* cpu, addr_t ptr, int size)
> +{
> + addr_t val;
> + uint8_t *mmio_ptr;
> +
> + if (is_host_reg(cpu, ptr)) {
> + return read_val_from_reg(ptr, size);
> + }
> +
> + mmio_ptr = read_mmio(cpu, ptr, size);
> + switch (size) {
> + case 1:
> + val = *(uint8_t*)mmio_ptr;
> + break;
> + case 2:
> + val = *(uint16_t*)mmio_ptr;
> + break;
> + case 4:
> + val = *(uint32_t*)mmio_ptr;
> + break;
> + case 8:
> + val = *(uint64_t*)mmio_ptr;
> + break;
> + default:
> + VM_PANIC("bad size\n");
> + break;
> + }
> + return val;
> +}
> +
> +static void fetch_operands(struct CPUState *cpu, struct x86_decode *decode, int n, bool val_op0, bool val_op1, bool val_op2)
> +{
> + int i;
> + bool calc_val[3] = {val_op0, val_op1, val_op2};
> +
> + for (i = 0; i < n; i++) {
> + switch (decode->op[i].type) {
> + case X86_VAR_IMMEDIATE:
> + break;
> + case X86_VAR_REG:
> + VM_PANIC_ON(!decode->op[i].ptr);
> + if (calc_val[i])
> + decode->op[i].val = read_val_from_reg(decode->op[i].ptr, decode->operand_size);
> + break;
> + case X86_VAR_RM:
> + calc_modrm_operand(cpu, decode, &decode->op[i]);
> + if (calc_val[i])
> + decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
> + break;
> + case X86_VAR_OFFSET:
> + decode->op[i].ptr = decode_linear_addr(cpu, decode, decode->op[i].ptr, REG_SEG_DS);
> + if (calc_val[i])
> + decode->op[i].val = read_val_ext(cpu, decode->op[i].ptr, decode->operand_size);
> + break;
> + default:
> + break;
> + }
> + }
> +}
> +
> +static void exec_mov(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + fetch_operands(cpu, decode, 2, false, true, false);
> + write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_add(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_or(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_LOGIC_CMD(cpu, decode, |, SET_FLAGS_OSZAPC_LOGIC, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_adc(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_ARITH_CMD(cpu, decode, +get_CF(cpu)+, SET_FLAGS_OSZAPC_ADD, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_sbb(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_ARITH_CMD(cpu, decode, -get_CF(cpu)-, SET_FLAGS_OSZAPC_SUB, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_and(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_LOGIC_CMD(cpu, decode, &, SET_FLAGS_OSZAPC_LOGIC, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_sub(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_xor(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_LOGIC_CMD(cpu, decode, ^, SET_FLAGS_OSZAPC_LOGIC, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_neg(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + //EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
> + int32_t val;
> + fetch_operands(cpu, decode, 2, true, true, false);
> +
> + val = 0 - sign(decode->op[1].val, decode->operand_size);
> + write_val_ext(cpu, decode->op[1].ptr, val, decode->operand_size);
> +
> + if (4 == decode->operand_size) {
> + SET_FLAGS_OSZAPC_SUB_32(0, 0 - val, val);
> + }
> + else if (2 == decode->operand_size) {
> + SET_FLAGS_OSZAPC_SUB_16(0, 0 - val, val);
> + }
> + else if (1 == decode->operand_size) {
> + SET_FLAGS_OSZAPC_SUB_8(0, 0 - val, val);
> + } else {
> + VM_PANIC("bad op size\n");
> + }
> +
> + //lflags_to_rflags(cpu);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_cmp(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_inc(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[1].type = X86_VAR_IMMEDIATE;
> + decode->op[1].val = 0;
> +
> + EXEC_2OP_ARITH_CMD(cpu, decode, +1+, SET_FLAGS_OSZAP_ADD, true);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_dec(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[1].type = X86_VAR_IMMEDIATE;
> + decode->op[1].val = 0;
> +
> + EXEC_2OP_ARITH_CMD(cpu, decode, -1-, SET_FLAGS_OSZAP_SUB, true);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_tst(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_LOGIC_CMD(cpu, decode, &, SET_FLAGS_OSZAPC_LOGIC, false);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_not(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + fetch_operands(cpu, decode, 1, true, false, false);
> +
> + write_val_ext(cpu, decode->op[0].ptr, ~decode->op[0].val, decode->operand_size);
> + RIP(cpu) += decode->len;
> +}
> +
> +void exec_movzx(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + int src_op_size;
> + int op_size = decode->operand_size;
> +
> + fetch_operands(cpu, decode, 1, false, false, false);
> +
> + if (0xb6 == decode->opcode[1])
> + src_op_size = 1;
> + else
> + src_op_size = 2;
> + decode->operand_size = src_op_size;
> + calc_modrm_operand(cpu, decode, &decode->op[1]);
> + decode->op[1].val = read_val_ext(cpu, decode->op[1].ptr, src_op_size);
> + write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_out(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + switch (decode->opcode[0]) {
> + case 0xe6:
> + hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 1, 1, 1);
> + break;
> + case 0xe7:
> + hvf_handle_io(cpu, decode->op[0].val, &RAX(cpu), 1, decode->operand_size, 1);
> + break;
> + case 0xee:
> + hvf_handle_io(cpu, DX(cpu), &AL(cpu), 1, 1, 1);
> + break;
> + case 0xef:
> + hvf_handle_io(cpu, DX(cpu), &RAX(cpu), 1, decode->operand_size, 1);
> + break;
> + default:
> + VM_PANIC("Bad out opcode\n");
> + break;
> + }
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_in(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t val = 0;
> + switch (decode->opcode[0]) {
> + case 0xe4:
> + hvf_handle_io(cpu, decode->op[0].val, &AL(cpu), 0, 1, 1);
> + break;
> + case 0xe5:
> + hvf_handle_io(cpu, decode->op[0].val, &val, 0, decode->operand_size, 1);
> + if (decode->operand_size == 2)
> + AX(cpu) = val;
> + else
> + RAX(cpu) = (uint32_t)val;
> + break;
> + case 0xec:
> + hvf_handle_io(cpu, DX(cpu), &AL(cpu), 0, 1, 1);
> + break;
> + case 0xed:
> + hvf_handle_io(cpu, DX(cpu), &val, 0, decode->operand_size, 1);
> + if (decode->operand_size == 2)
> + AX(cpu) = val;
> + else
> + RAX(cpu) = (uint32_t)val;
> +
> + break;
> + default:
> + VM_PANIC("Bad in opcode\n");
> + break;
> + }
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static inline void string_increment_reg(struct CPUState * cpu, int reg, struct x86_decode *decode)
> +{
> + addr_t val = read_reg(cpu, reg, decode->addressing_size);
> + if (cpu->hvf_x86->rflags.df)
> + val -= decode->operand_size;
> + else
> + val += decode->operand_size;
> + write_reg(cpu, reg, val, decode->addressing_size);
> +}
> +
> +static inline void string_rep(struct CPUState * cpu, struct x86_decode *decode, void (*func)(struct CPUState *cpu, struct x86_decode *ins), int rep)
> +{
> + addr_t rcx = read_reg(cpu, REG_RCX, decode->addressing_size);
> + while (rcx--) {
> + func(cpu, decode);
> + write_reg(cpu, REG_RCX, rcx, decode->addressing_size);
> + if ((PREFIX_REP == rep) && !get_ZF(cpu))
> + break;
> + if ((PREFIX_REPN == rep) && get_ZF(cpu))
> + break;
> + }
> +}
> +
> +static void exec_ins_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
> +
> + hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 0, decode->operand_size, 1);
> + vmx_write_mem(cpu, addr, cpu->hvf_x86->mmio_buf, decode->operand_size);
> +
> + string_increment_reg(cpu, REG_RDI, decode);
> +}
> +
> +static void exec_ins(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + if (decode->rep)
> + string_rep(cpu, decode, exec_ins_single, 0);
> + else
> + exec_ins_single(cpu, decode);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_outs_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
> +
> + vmx_read_mem(cpu, cpu->hvf_x86->mmio_buf, addr, decode->operand_size);
> + hvf_handle_io(cpu, DX(cpu), cpu->hvf_x86->mmio_buf, 1, decode->operand_size, 1);
> +
> + string_increment_reg(cpu, REG_RSI, decode);
> +}
> +
> +static void exec_outs(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + if (decode->rep)
> + string_rep(cpu, decode, exec_outs_single, 0);
> + else
> + exec_outs_single(cpu, decode);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_movs_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t src_addr;
> + addr_t dst_addr;
> + addr_t val;
> +
> + src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
> + dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
> +
> + val = read_val_ext(cpu, src_addr, decode->operand_size);
> + write_val_ext(cpu, dst_addr, val, decode->operand_size);
> +
> + string_increment_reg(cpu, REG_RSI, decode);
> + string_increment_reg(cpu, REG_RDI, decode);
> +}
> +
> +static void exec_movs(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + if (decode->rep) {
> + string_rep(cpu, decode, exec_movs_single, 0);
> + }
> + else
> + exec_movs_single(cpu, decode);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_cmps_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t src_addr;
> + addr_t dst_addr;
> +
> + src_addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
> + dst_addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
> +
> + decode->op[0].type = X86_VAR_IMMEDIATE;
> + decode->op[0].val = read_val_ext(cpu, src_addr, decode->operand_size);
> + decode->op[1].type = X86_VAR_IMMEDIATE;
> + decode->op[1].val = read_val_ext(cpu, dst_addr, decode->operand_size);
> +
> + EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
> +
> + string_increment_reg(cpu, REG_RSI, decode);
> + string_increment_reg(cpu, REG_RDI, decode);
> +}
> +
> +static void exec_cmps(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + if (decode->rep) {
> + string_rep(cpu, decode, exec_cmps_single, decode->rep);
> + }
> + else
> + exec_cmps_single(cpu, decode);
> + RIP(cpu) += decode->len;
> +}
> +
> +
> +static void exec_stos_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t addr;
> + addr_t val;
> +
> + addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
> + val = read_reg(cpu, REG_RAX, decode->operand_size);
> + vmx_write_mem(cpu, addr, &val, decode->operand_size);
> +
> + string_increment_reg(cpu, REG_RDI, decode);
> +}
> +
> +
> +static void exec_stos(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + if (decode->rep) {
> + string_rep(cpu, decode, exec_stos_single, 0);
> + }
> + else
> + exec_stos_single(cpu, decode);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_scas_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t addr;
> +
> + addr = linear_addr_size(cpu, RDI(cpu), decode->addressing_size, REG_SEG_ES);
> + decode->op[1].type = X86_VAR_IMMEDIATE;
> + vmx_read_mem(cpu, &decode->op[1].val, addr, decode->operand_size);
> +
> + EXEC_2OP_ARITH_CMD(cpu, decode, -, SET_FLAGS_OSZAPC_SUB, false);
> + string_increment_reg(cpu, REG_RDI, decode);
> +}
> +
> +static void exec_scas(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + decode->op[0].type = X86_VAR_REG;
> + decode->op[0].reg = REG_RAX;
> + if (decode->rep) {
> + string_rep(cpu, decode, exec_scas_single, decode->rep);
> + }
> + else
> + exec_scas_single(cpu, decode);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_lods_single(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + addr_t addr;
> + addr_t val = 0;
> +
> + addr = decode_linear_addr(cpu, decode, RSI(cpu), REG_SEG_DS);
> + vmx_read_mem(cpu, &val, addr, decode->operand_size);
> + write_reg(cpu, REG_RAX, val, decode->operand_size);
> +
> + string_increment_reg(cpu, REG_RSI, decode);
> +}
> +
> +static void exec_lods(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + if (decode->rep) {
> + string_rep(cpu, decode, exec_lods_single, 0);
> + }
> + else
> + exec_lods_single(cpu, decode);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +#define MSR_IA32_UCODE_REV 0x00000017
> +
> +void simulate_rdmsr(struct CPUState *cpu)
> +{
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + CPUX86State *env = &x86_cpu->env;
> + uint32_t msr = ECX(cpu);
> + uint64_t val = 0;
> +
> + switch (msr) {
> + case MSR_IA32_TSC:
> + val = rdtscp() + rvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET);
> + break;
> + case MSR_IA32_APICBASE:
> + val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
> + break;
> + case MSR_IA32_UCODE_REV:
> + val = (0x100000000ULL << 32) | 0x100000000ULL;
> + break;
> + case MSR_EFER:
> + val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
> + break;
> + case MSR_FSBASE:
> + val = rvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE);
> + break;
> + case MSR_GSBASE:
> + val = rvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE);
> + break;
> + case MSR_KERNELGSBASE:
> + val = rvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE);
> + break;
> + case MSR_STAR:
> + abort();
> + break;
> + case MSR_LSTAR:
> + abort();
> + break;
> + case MSR_CSTAR:
> + abort();
> + break;
> + case MSR_IA32_MISC_ENABLE:
> + val = env->msr_ia32_misc_enable;
> + break;
> + case MSR_MTRRphysBase(0):
> + case MSR_MTRRphysBase(1):
> + case MSR_MTRRphysBase(2):
> + case MSR_MTRRphysBase(3):
> + case MSR_MTRRphysBase(4):
> + case MSR_MTRRphysBase(5):
> + case MSR_MTRRphysBase(6):
> + case MSR_MTRRphysBase(7):
> + val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base;
> + break;
> + case MSR_MTRRphysMask(0):
> + case MSR_MTRRphysMask(1):
> + case MSR_MTRRphysMask(2):
> + case MSR_MTRRphysMask(3):
> + case MSR_MTRRphysMask(4):
> + case MSR_MTRRphysMask(5):
> + case MSR_MTRRphysMask(6):
> + case MSR_MTRRphysMask(7):
> + val = env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask;
> + break;
> + case MSR_MTRRfix64K_00000:
> + val = env->mtrr_fixed[0];
> + break;
> + case MSR_MTRRfix16K_80000:
> + case MSR_MTRRfix16K_A0000:
> + val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1];
> + break;
> + case MSR_MTRRfix4K_C0000:
> + case MSR_MTRRfix4K_C8000:
> + case MSR_MTRRfix4K_D0000:
> + case MSR_MTRRfix4K_D8000:
> + case MSR_MTRRfix4K_E0000:
> + case MSR_MTRRfix4K_E8000:
> + case MSR_MTRRfix4K_F0000:
> + case MSR_MTRRfix4K_F8000:
> + val = env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3];
> + break;
> + case MSR_MTRRdefType:
> + val = env->mtrr_deftype;
> + break;
> + default:
> + // fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr);
> + val = 0;
> + break;
> + }
> +
> + RAX(cpu) = (uint32_t)val;
> + RDX(cpu) = (uint32_t)(val >> 32);
> +}
> +
> +static void exec_rdmsr(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + simulate_rdmsr(cpu);
> + RIP(cpu) += decode->len;
> +}
> +
> +void simulate_wrmsr(struct CPUState *cpu)
> +{
> + X86CPU *x86_cpu = X86_CPU(cpu);
> + CPUX86State *env = &x86_cpu->env;
> + uint32_t msr = ECX(cpu);
> + uint64_t data = ((uint64_t)EDX(cpu) << 32) | EAX(cpu);
> +
> + switch (msr) {
> + case MSR_IA32_TSC:
> + // if (!osx_is_sierra())
> + // wvmcs(cpu->hvf_fd, VMCS_TSC_OFFSET, data - rdtscp());
> + //hv_vm_sync_tsc(data);
> + break;
> + case MSR_IA32_APICBASE:
> + cpu_set_apic_base(X86_CPU(cpu)->apic_state, data);
> + break;
> + case MSR_FSBASE:
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_FS_BASE, data);
> + break;
> + case MSR_GSBASE:
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_GS_BASE, data);
> + break;
> + case MSR_KERNELGSBASE:
> + wvmcs(cpu->hvf_fd, VMCS_HOST_FS_BASE, data);
> + break;
> + case MSR_STAR:
> + abort();
> + break;
> + case MSR_LSTAR:
> + abort();
> + break;
> + case MSR_CSTAR:
> + abort();
> + break;
> + case MSR_EFER:
> + cpu->hvf_x86->efer.efer = data;
> + //printf("new efer %llx\n", EFER(cpu));
> + wvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER, data);
> + if (data & EFER_NXE)
> + hv_vcpu_invalidate_tlb(cpu->hvf_fd);
> + break;
> + case MSR_MTRRphysBase(0):
> + case MSR_MTRRphysBase(1):
> + case MSR_MTRRphysBase(2):
> + case MSR_MTRRphysBase(3):
> + case MSR_MTRRphysBase(4):
> + case MSR_MTRRphysBase(5):
> + case MSR_MTRRphysBase(6):
> + case MSR_MTRRphysBase(7):
> + env->mtrr_var[(ECX(cpu) - MSR_MTRRphysBase(0)) / 2].base = data;
> + break;
> + case MSR_MTRRphysMask(0):
> + case MSR_MTRRphysMask(1):
> + case MSR_MTRRphysMask(2):
> + case MSR_MTRRphysMask(3):
> + case MSR_MTRRphysMask(4):
> + case MSR_MTRRphysMask(5):
> + case MSR_MTRRphysMask(6):
> + case MSR_MTRRphysMask(7):
> + env->mtrr_var[(ECX(cpu) - MSR_MTRRphysMask(0)) / 2].mask = data;
> + break;
> + case MSR_MTRRfix64K_00000:
> + env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix64K_00000] = data;
> + break;
> + case MSR_MTRRfix16K_80000:
> + case MSR_MTRRfix16K_A0000:
> + env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix16K_80000 + 1] = data;
> + break;
> + case MSR_MTRRfix4K_C0000:
> + case MSR_MTRRfix4K_C8000:
> + case MSR_MTRRfix4K_D0000:
> + case MSR_MTRRfix4K_D8000:
> + case MSR_MTRRfix4K_E0000:
> + case MSR_MTRRfix4K_E8000:
> + case MSR_MTRRfix4K_F0000:
> + case MSR_MTRRfix4K_F8000:
> + env->mtrr_fixed[ECX(cpu) - MSR_MTRRfix4K_C0000 + 3] = data;
> + break;
> + case MSR_MTRRdefType:
> + env->mtrr_deftype = data;
> + break;
> + default:
> + break;
> + }
> +
> + /* Related to support known hypervisor interface */
> + // if (g_hypervisor_iface)
> + // g_hypervisor_iface->wrmsr_handler(cpu, msr, data);
> +
> + //printf("write msr %llx\n", RCX(cpu));
> +}
> +
> +static void exec_wrmsr(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + simulate_wrmsr(cpu);
> + RIP(cpu) += decode->len;
> +}
> +
> +/*
> + * flag:
> + * 0 - bt, 1 - btc, 2 - bts, 3 - btr
> + */
> +static void do_bt(struct CPUState *cpu, struct x86_decode *decode, int flag)
> +{
> + int32_t displacement;
> + uint8_t index;
> + bool cf;
> + int mask = (4 == decode->operand_size) ? 0x1f : 0xf;
> +
> + VM_PANIC_ON(decode->rex.rex);
> +
> + fetch_operands(cpu, decode, 2, false, true, false);
> + index = decode->op[1].val & mask;
> +
> + if (decode->op[0].type != X86_VAR_REG) {
> + if (4 == decode->operand_size) {
> + displacement = ((int32_t) (decode->op[1].val & 0xffffffe0)) / 32;
> + decode->op[0].ptr += 4 * displacement;
> + } else if (2 == decode->operand_size) {
> + displacement = ((int16_t) (decode->op[1].val & 0xfff0)) / 16;
> + decode->op[0].ptr += 2 * displacement;
> + } else {
> + VM_PANIC("bt 64bit\n");
> + }
> + }
> + decode->op[0].val = read_val_ext(cpu, decode->op[0].ptr, decode->operand_size);
> + cf = (decode->op[0].val >> index) & 0x01;
> +
> + switch (flag) {
> + case 0:
> + set_CF(cpu, cf);
> + return;
> + case 1:
> + decode->op[0].val ^= (1u << index);
> + break;
> + case 2:
> + decode->op[0].val |= (1u << index);
> + break;
> + case 3:
> + decode->op[0].val &= ~(1u << index);
> + break;
> + }
> + write_val_ext(cpu, decode->op[0].ptr, decode->op[0].val, decode->operand_size);
> + set_CF(cpu, cf);
> +}
> +
> +static void exec_bt(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + do_bt(cpu, decode, 0);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_btc(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + do_bt(cpu, decode, 1);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_btr(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + do_bt(cpu, decode, 3);
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_bts(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + do_bt(cpu, decode, 2);
> + RIP(cpu) += decode->len;
> +}
> +
> +void exec_shl(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t count;
> + int of = 0, cf = 0;
> +
> + fetch_operands(cpu, decode, 2, true, true, false);
> +
> + count = decode->op[1].val;
> + count &= 0x1f; // count is masked to 5 bits
> + if (!count)
> + goto exit;
> +
> + switch (decode->operand_size) {
> + case 1:
> + {
> + uint8_t res = 0;
> + if (count <= 8) {
> + res = (decode->op[0].val << count);
> + cf = (decode->op[0].val >> (8 - count)) & 0x1;
> + of = cf ^ (res >> 7);
> + }
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 1);
> + SET_FLAGS_OSZAPC_LOGIC_8(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + case 2:
> + {
> + uint16_t res = 0;
> +
> + /* from bochs */
> + if (count <= 16) {
> + res = (decode->op[0].val << count);
> + cf = (decode->op[0].val >> (16 - count)) & 0x1;
> + of = cf ^ (res >> 15); // of = cf ^ result15
> + }
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 2);
> + SET_FLAGS_OSZAPC_LOGIC_16(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + case 4:
> + {
> + uint32_t res = decode->op[0].val << count;
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 4);
> + SET_FLAGS_OSZAPC_LOGIC_32(res);
> + cf = (decode->op[0].val >> (32 - count)) & 0x1;
> + of = cf ^ (res >> 31); // of = cf ^ result31
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + default:
> + abort();
> + }
> +
> +exit:
> + //lflags_to_rflags(cpu);
> + RIP(cpu) += decode->len;
> +}
> +
> +void exec_movsx(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + int src_op_size;
> + int op_size = decode->operand_size;
> +
> + fetch_operands(cpu, decode, 2, false, false, false);
> +
> + if (0xbe == decode->opcode[1])
> + src_op_size = 1;
> + else
> + src_op_size = 2;
> +
> + decode->operand_size = src_op_size;
> + calc_modrm_operand(cpu, decode, &decode->op[1]);
> + decode->op[1].val = sign(read_val_ext(cpu, decode->op[1].ptr, src_op_size), src_op_size);
> +
> + write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, op_size);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +void exec_ror(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t count;
> +
> + fetch_operands(cpu, decode, 2, true, true, false);
> + count = decode->op[1].val;
> +
> + switch (decode->operand_size) {
> + case 1:
> + {
> + uint32_t bit6, bit7;
> + uint8_t res;
> +
> + if ((count & 0x07) == 0) {
> + if (count & 0x18) {
> + bit6 = ((uint8_t)decode->op[0].val >> 6) & 1;
> + bit7 = ((uint8_t)decode->op[0].val >> 7) & 1;
> + SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
> + }
> + } else {
> + count &= 0x7; /* use only bottom 3 bits */
> + res = ((uint8_t)decode->op[0].val >> count) | ((uint8_t)decode->op[0].val << (8 - count));
> + write_val_ext(cpu, decode->op[0].ptr, res, 1);
> + bit6 = (res >> 6) & 1;
> + bit7 = (res >> 7) & 1;
> + /* set eflags: ROR count affects the following flags: C, O */
> + SET_FLAGS_OxxxxC(cpu, bit6 ^ bit7, bit7);
> + }
> + break;
> + }
> + case 2:
> + {
> + uint32_t bit14, bit15;
> + uint16_t res;
> +
> + if ((count & 0x0f) == 0) {
> + if (count & 0x10) {
> + bit14 = ((uint16_t)decode->op[0].val >> 14) & 1;
> + bit15 = ((uint16_t)decode->op[0].val >> 15) & 1;
> + // of = result14 ^ result15
> + SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
> + }
> + } else {
> + count &= 0x0f; // use only 4 LSB's
> + res = ((uint16_t)decode->op[0].val >> count) | ((uint16_t)decode->op[0].val << (16 - count));
> + write_val_ext(cpu, decode->op[0].ptr, res, 2);
> +
> + bit14 = (res >> 14) & 1;
> + bit15 = (res >> 15) & 1;
> + // of = result14 ^ result15
> + SET_FLAGS_OxxxxC(cpu, bit14 ^ bit15, bit15);
> + }
> + break;
> + }
> + case 4:
> + {
> + uint32_t bit31, bit30;
> + uint32_t res;
> +
> + count &= 0x1f;
> + if (count) {
> + res = ((uint32_t)decode->op[0].val >> count) | ((uint32_t)decode->op[0].val << (32 - count));
> + write_val_ext(cpu, decode->op[0].ptr, res, 4);
> +
> + bit31 = (res >> 31) & 1;
> + bit30 = (res >> 30) & 1;
> + // of = result30 ^ result31
> + SET_FLAGS_OxxxxC(cpu, bit30 ^ bit31, bit31);
> + }
> + break;
> + }
> + }
> + RIP(cpu) += decode->len;
> +}
> +
> +void exec_rol(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t count;
> +
> + fetch_operands(cpu, decode, 2, true, true, false);
> + count = decode->op[1].val;
> +
> + switch (decode->operand_size) {
> + case 1:
> + {
> + uint32_t bit0, bit7;
> + uint8_t res;
> +
> + if ((count & 0x07) == 0) {
> + if (count & 0x18) {
> + bit0 = ((uint8_t)decode->op[0].val & 1);
> + bit7 = ((uint8_t)decode->op[0].val >> 7);
> + SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
> + }
> + } else {
> + count &= 0x7; // use only lowest 3 bits
> + res = ((uint8_t)decode->op[0].val << count) | ((uint8_t)decode->op[0].val >> (8 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 1);
> + /* set eflags:
> + * ROL count affects the following flags: C, O
> + */
> + bit0 = (res & 1);
> + bit7 = (res >> 7);
> + SET_FLAGS_OxxxxC(cpu, bit0 ^ bit7, bit0);
> + }
> + break;
> + }
> + case 2:
> + {
> + uint32_t bit0, bit15;
> + uint16_t res;
> +
> + if ((count & 0x0f) == 0) {
> + if (count & 0x10) {
> + bit0 = ((uint16_t)decode->op[0].val & 0x1);
> + bit15 = ((uint16_t)decode->op[0].val >> 15);
> + // of = cf ^ result15
> + SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
> + }
> + } else {
> + count &= 0x0f; // only use bottom 4 bits
> + res = ((uint16_t)decode->op[0].val << count) | ((uint16_t)decode->op[0].val >> (16 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 2);
> + bit0 = (res & 0x1);
> + bit15 = (res >> 15);
> + // of = cf ^ result15
> + SET_FLAGS_OxxxxC(cpu, bit0 ^ bit15, bit0);
> + }
> + break;
> + }
> + case 4:
> + {
> + uint32_t bit0, bit31;
> + uint32_t res;
> +
> + count &= 0x1f;
> + if (count) {
> + res = ((uint32_t)decode->op[0].val << count) | ((uint32_t)decode->op[0].val >> (32 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 4);
> + bit0 = (res & 0x1);
> + bit31 = (res >> 31);
> + // of = cf ^ result31
> + SET_FLAGS_OxxxxC(cpu, bit0 ^ bit31, bit0);
> + }
> + break;
> + }
> + }
> + RIP(cpu) += decode->len;
> +}
> +
> +
> +void exec_rcl(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t count;
> + int of = 0, cf = 0;
> +
> + fetch_operands(cpu, decode, 2, true, true, false);
> + count = decode->op[1].val & 0x1f;
> +
> + switch(decode->operand_size) {
> + case 1:
> + {
> + uint8_t op1_8 = decode->op[0].val;
> + uint8_t res;
> + count %= 9;
> + if (!count)
> + break;
> +
> + if (1 == count)
> + res = (op1_8 << 1) | get_CF(cpu);
> + else
> + res = (op1_8 << count) | (get_CF(cpu) << (count - 1)) | (op1_8 >> (9 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 1);
> +
> + cf = (op1_8 >> (8 - count)) & 0x01;
> + of = cf ^ (res >> 7); // of = cf ^ result7
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + case 2:
> + {
> + uint16_t res;
> + uint16_t op1_16 = decode->op[0].val;
> +
> + count %= 17;
> + if (!count)
> + break;
> +
> + if (1 == count)
> + res = (op1_16 << 1) | get_CF(cpu);
> + else if (count == 16)
> + res = (get_CF(cpu) << 15) | (op1_16 >> 1);
> + else // 2..15
> + res = (op1_16 << count) | (get_CF(cpu) << (count - 1)) | (op1_16 >> (17 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 2);
> +
> + cf = (op1_16 >> (16 - count)) & 0x1;
> + of = cf ^ (res >> 15); // of = cf ^ result15
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + case 4:
> + {
> + uint32_t res;
> + uint32_t op1_32 = decode->op[0].val;
> +
> + if (!count)
> + break;
> +
> + if (1 == count)
> + res = (op1_32 << 1) | get_CF(cpu);
> + else
> + res = (op1_32 << count) | (get_CF(cpu) << (count - 1)) | (op1_32 >> (33 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 4);
> +
> + cf = (op1_32 >> (32 - count)) & 0x1;
> + of = cf ^ (res >> 31); // of = cf ^ result31
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + }
> + RIP(cpu) += decode->len;
> +}
> +
> +void exec_rcr(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + uint8_t count;
> + int of = 0, cf = 0;
> +
> + fetch_operands(cpu, decode, 2, true, true, false);
> + count = decode->op[1].val & 0x1f;
> +
> + switch(decode->operand_size) {
> + case 1:
> + {
> + uint8_t op1_8 = decode->op[0].val;
> + uint8_t res;
> +
> + count %= 9;
> + if (!count)
> + break;
> + res = (op1_8 >> count) | (get_CF(cpu) << (8 - count)) | (op1_8 << (9 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 1);
> +
> + cf = (op1_8 >> (count - 1)) & 0x1;
> + of = (((res << 1) ^ res) >> 7) & 0x1; // of = result6 ^ result7
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + case 2:
> + {
> + uint16_t op1_16 = decode->op[0].val;
> + uint16_t res;
> +
> + count %= 17;
> + if (!count)
> + break;
> + res = (op1_16 >> count) | (get_CF(cpu) << (16 - count)) | (op1_16 << (17 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 2);
> +
> + cf = (op1_16 >> (count - 1)) & 0x1;
> + of = ((uint16_t)((res << 1) ^ res) >> 15) & 0x1; // of = result15 ^ result14
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + case 4:
> + {
> + uint32_t res;
> + uint32_t op1_32 = decode->op[0].val;
> +
> + if (!count)
> + break;
> +
> + if (1 == count)
> + res = (op1_32 >> 1) | (get_CF(cpu) << 31);
> + else
> + res = (op1_32 >> count) | (get_CF(cpu) << (32 - count)) | (op1_32 << (33 - count));
> +
> + write_val_ext(cpu, decode->op[0].ptr, res, 4);
> +
> + cf = (op1_32 >> (count - 1)) & 0x1;
> + of = ((res << 1) ^ res) >> 31; // of = result30 ^ result31
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> + break;
> + }
> + }
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_xchg(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + fetch_operands(cpu, decode, 2, true, true, false);
> +
> + write_val_ext(cpu, decode->op[0].ptr, decode->op[1].val, decode->operand_size);
> + write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static void exec_xadd(struct CPUState *cpu, struct x86_decode *decode)
> +{
> + EXEC_2OP_ARITH_CMD(cpu, decode, +, SET_FLAGS_OSZAPC_ADD, true);
> + write_val_ext(cpu, decode->op[1].ptr, decode->op[0].val, decode->operand_size);
> +
> + RIP(cpu) += decode->len;
> +}
> +
> +static struct cmd_handler {
> + enum x86_decode_cmd cmd;
> + void (*handler)(struct CPUState *cpu, struct x86_decode *ins);
> +} handlers[] = {
> + {X86_DECODE_CMD_INVL, NULL,},
> + {X86_DECODE_CMD_MOV, exec_mov},
> + {X86_DECODE_CMD_ADD, exec_add},
> + {X86_DECODE_CMD_OR, exec_or},
> + {X86_DECODE_CMD_ADC, exec_adc},
> + {X86_DECODE_CMD_SBB, exec_sbb},
> + {X86_DECODE_CMD_AND, exec_and},
> + {X86_DECODE_CMD_SUB, exec_sub},
> + {X86_DECODE_CMD_NEG, exec_neg},
> + {X86_DECODE_CMD_XOR, exec_xor},
> + {X86_DECODE_CMD_CMP, exec_cmp},
> + {X86_DECODE_CMD_INC, exec_inc},
> + {X86_DECODE_CMD_DEC, exec_dec},
> + {X86_DECODE_CMD_TST, exec_tst},
> + {X86_DECODE_CMD_NOT, exec_not},
> + {X86_DECODE_CMD_MOVZX, exec_movzx},
> + {X86_DECODE_CMD_OUT, exec_out},
> + {X86_DECODE_CMD_IN, exec_in},
> + {X86_DECODE_CMD_INS, exec_ins},
> + {X86_DECODE_CMD_OUTS, exec_outs},
> + {X86_DECODE_CMD_RDMSR, exec_rdmsr},
> + {X86_DECODE_CMD_WRMSR, exec_wrmsr},
> + {X86_DECODE_CMD_BT, exec_bt},
> + {X86_DECODE_CMD_BTR, exec_btr},
> + {X86_DECODE_CMD_BTC, exec_btc},
> + {X86_DECODE_CMD_BTS, exec_bts},
> + {X86_DECODE_CMD_SHL, exec_shl},
> + {X86_DECODE_CMD_ROL, exec_rol},
> + {X86_DECODE_CMD_ROR, exec_ror},
> + {X86_DECODE_CMD_RCR, exec_rcr},
> + {X86_DECODE_CMD_RCL, exec_rcl},
> + /*{X86_DECODE_CMD_CPUID, exec_cpuid},*/
> + {X86_DECODE_CMD_MOVS, exec_movs},
> + {X86_DECODE_CMD_CMPS, exec_cmps},
> + {X86_DECODE_CMD_STOS, exec_stos},
> + {X86_DECODE_CMD_SCAS, exec_scas},
> + {X86_DECODE_CMD_LODS, exec_lods},
> + {X86_DECODE_CMD_MOVSX, exec_movsx},
> + {X86_DECODE_CMD_XCHG, exec_xchg},
> + {X86_DECODE_CMD_XADD, exec_xadd},
> +};
> +
> +static struct cmd_handler _cmd_handler[X86_DECODE_CMD_LAST];
> +
> +static void init_cmd_handler(CPUState *cpu)
> +{
> + int i;
> + for (i = 0; i < ARRAY_SIZE(handlers); i++)
> + _cmd_handler[handlers[i].cmd] = handlers[i];
> +}
> +
> +static void print_debug(struct CPUState *cpu)
> +{
> + printf("%llx: eax %llx ebx %llx ecx %llx edx %llx esi %llx edi %llx ebp %llx esp %llx flags %llx\n", RIP(cpu), RAX(cpu), RBX(cpu), RCX(cpu), RDX(cpu), RSI(cpu), RDI(cpu), RBP(cpu), RSP(cpu), EFLAGS(cpu));
> +}
> +
> +void load_regs(struct CPUState *cpu)
> +{
> + int i = 0;
> + RRX(cpu, REG_RAX) = rreg(cpu->hvf_fd, HV_X86_RAX);
> + RRX(cpu, REG_RBX) = rreg(cpu->hvf_fd, HV_X86_RBX);
> + RRX(cpu, REG_RCX) = rreg(cpu->hvf_fd, HV_X86_RCX);
> + RRX(cpu, REG_RDX) = rreg(cpu->hvf_fd, HV_X86_RDX);
> + RRX(cpu, REG_RSI) = rreg(cpu->hvf_fd, HV_X86_RSI);
> + RRX(cpu, REG_RDI) = rreg(cpu->hvf_fd, HV_X86_RDI);
> + RRX(cpu, REG_RSP) = rreg(cpu->hvf_fd, HV_X86_RSP);
> + RRX(cpu, REG_RBP) = rreg(cpu->hvf_fd, HV_X86_RBP);
> + for (i = 8; i < 16; i++)
> + RRX(cpu, i) = rreg(cpu->hvf_fd, HV_X86_RAX + i);
> +
> + RFLAGS(cpu) = rreg(cpu->hvf_fd, HV_X86_RFLAGS);
> + rflags_to_lflags(cpu);
> + RIP(cpu) = rreg(cpu->hvf_fd, HV_X86_RIP);
> +
> + //print_debug(cpu);
> +}
> +
> +void store_regs(struct CPUState *cpu)
> +{
> + int i = 0;
> + wreg(cpu->hvf_fd, HV_X86_RAX, RAX(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RBX, RBX(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RCX, RCX(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RDX, RDX(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RSI, RSI(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RDI, RDI(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RBP, RBP(cpu));
> + wreg(cpu->hvf_fd, HV_X86_RSP, RSP(cpu));
> + for (i = 8; i < 16; i++)
> + wreg(cpu->hvf_fd, HV_X86_RAX + i, RRX(cpu, i));
> +
> + lflags_to_rflags(cpu);
> + wreg(cpu->hvf_fd, HV_X86_RFLAGS, RFLAGS(cpu));
> + macvm_set_rip(cpu, RIP(cpu));
> +
> + //print_debug(cpu);
> +}
> +
> +bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins)
> +{
> + //if (hvf_vcpu_id(cpu))
> + //printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), RIP(cpu), decode_cmd_to_string(ins->cmd));
> +
> + if (0 && ins->is_fpu) {
> + VM_PANIC("emulate fpu\n");
> + } else {
> + if (!_cmd_handler[ins->cmd].handler) {
> + printf("Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0],
> + ins->opcode_len > 1 ? ins->opcode[1] : 0);
> + RIP(cpu) += ins->len;
> + return true;
> + }
> +
> + VM_PANIC_ON_EX(!_cmd_handler[ins->cmd].handler, "Unimplemented handler (%llx) for %d (%x %x) \n", RIP(cpu), ins->cmd, ins->opcode[0], ins->opcode_len > 1 ? ins->opcode[1] : 0);
> + _cmd_handler[ins->cmd].handler(cpu, ins);
> + }
> + return true;
> +}
> +
> +void init_emu(struct CPUState *cpu)
> +{
> + init_cmd_handler(cpu);
> +}
> diff --git a/target/i386/hvf-utils/x86_emu.h b/target/i386/hvf-utils/x86_emu.h
> new file mode 100644
> index 0000000000..c56b2798fa
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_emu.h
> @@ -0,0 +1,16 @@
> +#ifndef __X86_EMU_H__
> +#define __X86_EMU_H__
> +
> +#include "x86.h"
> +#include "x86_decode.h"
> +
> +void init_emu(struct CPUState *cpu);
> +bool exec_instruction(struct CPUState *cpu, struct x86_decode *ins);
> +
> +void load_regs(struct CPUState *cpu);
> +void store_regs(struct CPUState *cpu);
> +
> +void simulate_rdmsr(struct CPUState *cpu);
> +void simulate_wrmsr(struct CPUState *cpu);
> +
> +#endif
> diff --git a/target/i386/hvf-utils/x86_flags.c b/target/i386/hvf-utils/x86_flags.c
> new file mode 100644
> index 0000000000..ca876d03dd
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_flags.c
> @@ -0,0 +1,317 @@
> +/////////////////////////////////////////////////////////////////////////
> +//
> +// Copyright (C) 2001-2012 The Bochs Project
> +// Copyright (C) 2017 Google Inc.
> +//
> +// This library is free software; you can redistribute it and/or
> +// modify it under the terms of the GNU Lesser General Public
> +// License as published by the Free Software Foundation; either
> +// version 2 of the License, or (at your option) any later version.
> +//
> +// This library is distributed in the hope that it will be useful,
> +// but WITHOUT ANY WARRANTY; without even the implied warranty of
> +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +// Lesser General Public License for more details.
> +//
> +// You should have received a copy of the GNU Lesser General Public
> +// License along with this library; if not, write to the Free Software
> +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
> +/////////////////////////////////////////////////////////////////////////
> +/*
> + * flags functions
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +
> +#include "cpu.h"
> +#include "x86_flags.h"
> +#include "x86.h"
> +
> +void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf)
> +{
> + uint32_t temp_po = new_of ^ new_cf;
> + cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PO | LF_MASK_CF);
> + cpu->hvf_x86->lflags.auxbits |= (temp_po << LF_BIT_PO) | (new_cf << LF_BIT_CF);
> +}
> +
> +void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
> +{
> + SET_FLAGS_OSZAPC_SUB_32(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
> +{
> + SET_FLAGS_OSZAPC_SUB_16(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
> +{
> + SET_FLAGS_OSZAPC_SUB_8(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
> +{
> + SET_FLAGS_OSZAPC_ADD_32(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
> +{
> + SET_FLAGS_OSZAPC_ADD_16(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
> +{
> + SET_FLAGS_OSZAPC_ADD_8(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
> +{
> + SET_FLAGS_OSZAP_SUB_32(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
> +{
> + SET_FLAGS_OSZAP_SUB_16(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
> +{
> + SET_FLAGS_OSZAP_SUB_8(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff)
> +{
> + SET_FLAGS_OSZAP_ADD_32(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff)
> +{
> + SET_FLAGS_OSZAP_ADD_16(v1, v2, diff);
> +}
> +
> +void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff)
> +{
> + SET_FLAGS_OSZAP_ADD_8(v1, v2, diff);
> +}
> +
> +
> +void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff)
> +{
> + SET_FLAGS_OSZAPC_LOGIC_32(diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff)
> +{
> + SET_FLAGS_OSZAPC_LOGIC_16(diff);
> +}
> +
> +void SET_FLAGS_OSZAPC_LOGIC8(struct CPUState *cpu, uint8_t diff)
> +{
> + SET_FLAGS_OSZAPC_LOGIC_8(diff);
> +}
> +
> +void SET_FLAGS_SHR32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
> +{
> + int cf = (v >> (count - 1)) & 0x1;
> + int of = (((res << 1) ^ res) >> 31);
> +
> + SET_FLAGS_OSZAPC_LOGIC_32(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> +}
> +
> +void SET_FLAGS_SHR16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
> +{
> + int cf = (v >> (count - 1)) & 0x1;
> + int of = (((res << 1) ^ res) >> 15);
> +
> + SET_FLAGS_OSZAPC_LOGIC_16(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> +}
> +
> +void SET_FLAGS_SHR8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
> +{
> + int cf = (v >> (count - 1)) & 0x1;
> + int of = (((res << 1) ^ res) >> 7);
> +
> + SET_FLAGS_OSZAPC_LOGIC_8(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> +}
> +
> +void SET_FLAGS_SAR32(struct CPUState *cpu, int32_t v, int count, uint32_t res)
> +{
> + int cf = (v >> (count - 1)) & 0x1;
> +
> + SET_FLAGS_OSZAPC_LOGIC_32(res);
> + SET_FLAGS_OxxxxC(cpu, 0, cf);
> +}
> +
> +void SET_FLAGS_SAR16(struct CPUState *cpu, int16_t v, int count, uint16_t res)
> +{
> + int cf = (v >> (count - 1)) & 0x1;
> +
> + SET_FLAGS_OSZAPC_LOGIC_16(res);
> + SET_FLAGS_OxxxxC(cpu, 0, cf);
> +}
> +
> +void SET_FLAGS_SAR8(struct CPUState *cpu, int8_t v, int count, uint8_t res)
> +{
> + int cf = (v >> (count - 1)) & 0x1;
> +
> + SET_FLAGS_OSZAPC_LOGIC_8(res);
> + SET_FLAGS_OxxxxC(cpu, 0, cf);
> +}
> +
> +
> +void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res)
> +{
> + int of, cf;
> +
> + cf = (v >> (32 - count)) & 0x1;
> + of = cf ^ (res >> 31);
> +
> + SET_FLAGS_OSZAPC_LOGIC_32(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> +}
> +
> +void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res)
> +{
> + int of = 0, cf = 0;
> +
> + if (count <= 16) {
> + cf = (v >> (16 - count)) & 0x1;
> + of = cf ^ (res >> 15);
> + }
> +
> + SET_FLAGS_OSZAPC_LOGIC_16(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> +}
> +
> +void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res)
> +{
> + int of = 0, cf = 0;
> +
> + if (count <= 8) {
> + cf = (v >> (8 - count)) & 0x1;
> + of = cf ^ (res >> 7);
> + }
> +
> + SET_FLAGS_OSZAPC_LOGIC_8(res);
> + SET_FLAGS_OxxxxC(cpu, of, cf);
> +}
> +
> +bool get_PF(struct CPUState *cpu)
> +{
> + uint32_t temp = (255 & cpu->hvf_x86->lflags.result);
> + temp = temp ^ (255 & (cpu->hvf_x86->lflags.auxbits >> LF_BIT_PDB));
> + temp = (temp ^ (temp >> 4)) & 0x0F;
> + return (0x9669U >> temp) & 1;
> +}
> +
> +void set_PF(struct CPUState *cpu, bool val)
> +{
> + uint32_t temp = (255 & cpu->hvf_x86->lflags.result) ^ (!val);
> + cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_PDB);
> + cpu->hvf_x86->lflags.auxbits |= (temp << LF_BIT_PDB);
> +}
> +
> +bool _get_OF(struct CPUState *cpu)
> +{
> + return ((cpu->hvf_x86->lflags.auxbits + (1U << LF_BIT_PO)) >> LF_BIT_CF) & 1;
> +}
> +
> +bool get_OF(struct CPUState *cpu)
> +{
> + return _get_OF(cpu);
> +}
> +
> +bool _get_CF(struct CPUState *cpu)
> +{
> + return (cpu->hvf_x86->lflags.auxbits >> LF_BIT_CF) & 1;
> +}
> +
> +bool get_CF(struct CPUState *cpu)
> +{
> + return _get_CF(cpu);
> +}
> +
> +void set_OF(struct CPUState *cpu, bool val)
> +{
> + SET_FLAGS_OxxxxC(cpu, val, _get_CF(cpu));
> +}
> +
> +void set_CF(struct CPUState *cpu, bool val)
> +{
> + SET_FLAGS_OxxxxC(cpu, _get_OF(cpu), (val));
> +}
> +
> +bool get_AF(struct CPUState *cpu)
> +{
> + return (cpu->hvf_x86->lflags.auxbits >> LF_BIT_AF) & 1;
> +}
> +
> +void set_AF(struct CPUState *cpu, bool val)
> +{
> + cpu->hvf_x86->lflags.auxbits &= ~(LF_MASK_AF);
> + cpu->hvf_x86->lflags.auxbits |= (val) << LF_BIT_AF;
> +}
> +
> +bool get_ZF(struct CPUState *cpu)
> +{
> + return !cpu->hvf_x86->lflags.result;
> +}
> +
> +void set_ZF(struct CPUState *cpu, bool val)
> +{
> + if (val) {
> + cpu->hvf_x86->lflags.auxbits ^= (((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) & 1) << LF_BIT_SD);
> + // merge the parity bits into the Parity Delta Byte
> + uint32_t temp_pdb = (255 & cpu->hvf_x86->lflags.result);
> + cpu->hvf_x86->lflags.auxbits ^= (temp_pdb << LF_BIT_PDB);
> + // now zero the .result value
> + cpu->hvf_x86->lflags.result = 0;
> + } else
> + cpu->hvf_x86->lflags.result |= (1 << 8);
> +}
> +
> +bool get_SF(struct CPUState *cpu)
> +{
> + return ((cpu->hvf_x86->lflags.result >> LF_SIGN_BIT) ^ (cpu->hvf_x86->lflags.auxbits >> LF_BIT_SD)) & 1;
> +}
> +
> +void set_SF(struct CPUState *cpu, bool val)
> +{
> + bool temp_sf = get_SF(cpu);
> + cpu->hvf_x86->lflags.auxbits ^= (temp_sf ^ val) << LF_BIT_SD;
> +}
> +
> +void set_OSZAPC(struct CPUState *cpu, uint32_t flags32)
> +{
> + set_OF(cpu, cpu->hvf_x86->rflags.of);
> + set_SF(cpu, cpu->hvf_x86->rflags.sf);
> + set_ZF(cpu, cpu->hvf_x86->rflags.zf);
> + set_AF(cpu, cpu->hvf_x86->rflags.af);
> + set_PF(cpu, cpu->hvf_x86->rflags.pf);
> + set_CF(cpu, cpu->hvf_x86->rflags.cf);
> +}
> +
> +void lflags_to_rflags(struct CPUState *cpu)
> +{
> + cpu->hvf_x86->rflags.cf = get_CF(cpu);
> + cpu->hvf_x86->rflags.pf = get_PF(cpu);
> + cpu->hvf_x86->rflags.af = get_AF(cpu);
> + cpu->hvf_x86->rflags.zf = get_ZF(cpu);
> + cpu->hvf_x86->rflags.sf = get_SF(cpu);
> + cpu->hvf_x86->rflags.of = get_OF(cpu);
> +}
> +
> +void rflags_to_lflags(struct CPUState *cpu)
> +{
> + cpu->hvf_x86->lflags.auxbits = cpu->hvf_x86->lflags.result = 0;
> + set_OF(cpu, cpu->hvf_x86->rflags.of);
> + set_SF(cpu, cpu->hvf_x86->rflags.sf);
> + set_ZF(cpu, cpu->hvf_x86->rflags.zf);
> + set_AF(cpu, cpu->hvf_x86->rflags.af);
> + set_PF(cpu, cpu->hvf_x86->rflags.pf);
> + set_CF(cpu, cpu->hvf_x86->rflags.cf);
> +}
> diff --git a/target/i386/hvf-utils/x86_flags.h b/target/i386/hvf-utils/x86_flags.h
> new file mode 100644
> index 0000000000..f963f8ad1b
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_flags.h
> @@ -0,0 +1,218 @@
> +/////////////////////////////////////////////////////////////////////////
> +//
> +// Copyright (C) 2001-2012 The Bochs Project
> +// Copyright (C) 2017 Google Inc.
> +//
> +// This library is free software; you can redistribute it and/or
> +// modify it under the terms of the GNU Lesser General Public
> +// License as published by the Free Software Foundation; either
> +// version 2 of the License, or (at your option) any later version.
> +//
> +// This library is distributed in the hope that it will be useful,
> +// but WITHOUT ANY WARRANTY; without even the implied warranty of
> +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> +// Lesser General Public License for more details.
> +//
> +// You should have received a copy of the GNU Lesser General Public
> +// License along with this library; if not, write to the Free Software
> +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
> +/////////////////////////////////////////////////////////////////////////
> +/*
> + * x86 eflags functions
> + */
> +#ifndef __X86_FLAGS_H__
> +#define __X86_FLAGS_H__
> +
> +#include "x86_gen.h"
> +
> +/* this is basically bocsh code */
> +
> +typedef struct lazy_flags {
> + addr_t result;
> + addr_t auxbits;
> +} lazy_flags;
> +
> +#define LF_SIGN_BIT 31
> +
> +#define LF_BIT_SD (0) /* lazy Sign Flag Delta */
> +#define LF_BIT_AF (3) /* lazy Adjust flag */
> +#define LF_BIT_PDB (8) /* lazy Parity Delta Byte (8 bits) */
> +#define LF_BIT_CF (31) /* lazy Carry Flag */
> +#define LF_BIT_PO (30) /* lazy Partial Overflow = CF ^ OF */
> +
> +#define LF_MASK_SD (0x01 << LF_BIT_SD)
> +#define LF_MASK_AF (0x01 << LF_BIT_AF)
> +#define LF_MASK_PDB (0xFF << LF_BIT_PDB)
> +#define LF_MASK_CF (0x01 << LF_BIT_CF)
> +#define LF_MASK_PO (0x01 << LF_BIT_PO)
> +
> +#define ADD_COUT_VEC(op1, op2, result) \
> + (((op1) & (op2)) | (((op1) | (op2)) & (~(result))))
> +
> +#define SUB_COUT_VEC(op1, op2, result) \
> + (((~(op1)) & (op2)) | (((~(op1)) ^ (op2)) & (result)))
> +
> +#define GET_ADD_OVERFLOW(op1, op2, result, mask) \
> + ((((op1) ^ (result)) & ((op2) ^ (result))) & (mask))
> +
> +// *******************
> +// OSZAPC
> +// *******************
> +
> +/* size, carries, result */
> +#define SET_FLAGS_OSZAPC_SIZE(size, lf_carries, lf_result) { \
> + addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
> + (((lf_carries) >> (size - 2)) << LF_BIT_PO); \
> + cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
> + if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
> + else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
> + else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
> + else VM_PANIC("unimplemented"); \
> + cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)temp; \
> +}
> +
> +/* carries, result */
> +#define SET_FLAGS_OSZAPC_8(carries, result) \
> + SET_FLAGS_OSZAPC_SIZE(8, carries, result)
> +#define SET_FLAGS_OSZAPC_16(carries, result) \
> + SET_FLAGS_OSZAPC_SIZE(16, carries, result)
> +#define SET_FLAGS_OSZAPC_32(carries, result) \
> + SET_FLAGS_OSZAPC_SIZE(32, carries, result)
> +
> +/* result */
> +#define SET_FLAGS_OSZAPC_LOGIC_8(result_8) \
> + SET_FLAGS_OSZAPC_8(0, (result_8))
> +#define SET_FLAGS_OSZAPC_LOGIC_16(result_16) \
> + SET_FLAGS_OSZAPC_16(0, (result_16))
> +#define SET_FLAGS_OSZAPC_LOGIC_32(result_32) \
> + SET_FLAGS_OSZAPC_32(0, (result_32))
> +#define SET_FLAGS_OSZAPC_LOGIC_SIZE(size, result) { \
> + if (32 == size) {SET_FLAGS_OSZAPC_LOGIC_32(result);} \
> + else if (16 == size) {SET_FLAGS_OSZAPC_LOGIC_16(result);} \
> + else if (8 == size) {SET_FLAGS_OSZAPC_LOGIC_8(result);} \
> + else VM_PANIC("unimplemented"); \
> +}
> +
> +/* op1, op2, result */
> +#define SET_FLAGS_OSZAPC_ADD_8(op1_8, op2_8, sum_8) \
> + SET_FLAGS_OSZAPC_8(ADD_COUT_VEC((op1_8), (op2_8), (sum_8)), (sum_8))
> +#define SET_FLAGS_OSZAPC_ADD_16(op1_16, op2_16, sum_16) \
> + SET_FLAGS_OSZAPC_16(ADD_COUT_VEC((op1_16), (op2_16), (sum_16)), (sum_16))
> +#define SET_FLAGS_OSZAPC_ADD_32(op1_32, op2_32, sum_32) \
> + SET_FLAGS_OSZAPC_32(ADD_COUT_VEC((op1_32), (op2_32), (sum_32)), (sum_32))
> +
> +/* op1, op2, result */
> +#define SET_FLAGS_OSZAPC_SUB_8(op1_8, op2_8, diff_8) \
> + SET_FLAGS_OSZAPC_8(SUB_COUT_VEC((op1_8), (op2_8), (diff_8)), (diff_8))
> +#define SET_FLAGS_OSZAPC_SUB_16(op1_16, op2_16, diff_16) \
> + SET_FLAGS_OSZAPC_16(SUB_COUT_VEC((op1_16), (op2_16), (diff_16)), (diff_16))
> +#define SET_FLAGS_OSZAPC_SUB_32(op1_32, op2_32, diff_32) \
> + SET_FLAGS_OSZAPC_32(SUB_COUT_VEC((op1_32), (op2_32), (diff_32)), (diff_32))
> +
> +// *******************
> +// OSZAP
> +// *******************
> +/* size, carries, result */
> +#define SET_FLAGS_OSZAP_SIZE(size, lf_carries, lf_result) { \
> + addr_t temp = ((lf_carries) & (LF_MASK_AF)) | \
> + (((lf_carries) >> (size - 2)) << LF_BIT_PO); \
> + if ((size) == 32) temp = ((lf_carries) & ~(LF_MASK_PDB | LF_MASK_SD)); \
> + else if ((size) == 16) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 16); \
> + else if ((size) == 8) temp = ((lf_carries) & (LF_MASK_AF)) | ((lf_carries) << 24); \
> + else VM_PANIC("unimplemented"); \
> + cpu->hvf_x86->lflags.result = (addr_t)(int##size##_t)(lf_result); \
> + addr_t delta_c = (cpu->hvf_x86->lflags.auxbits ^ temp) & LF_MASK_CF; \
> + delta_c ^= (delta_c >> 1); \
> + cpu->hvf_x86->lflags.auxbits = (addr_t)(uint32_t)(temp ^ delta_c); \
> +}
> +
> +/* carries, result */
> +#define SET_FLAGS_OSZAP_8(carries, result) \
> + SET_FLAGS_OSZAP_SIZE(8, carries, result)
> +#define SET_FLAGS_OSZAP_16(carries, result) \
> + SET_FLAGS_OSZAP_SIZE(16, carries, result)
> +#define SET_FLAGS_OSZAP_32(carries, result) \
> + SET_FLAGS_OSZAP_SIZE(32, carries, result)
> +
> +/* op1, op2, result */
> +#define SET_FLAGS_OSZAP_ADD_8(op1_8, op2_8, sum_8) \
> + SET_FLAGS_OSZAP_8(ADD_COUT_VEC((op1_8), (op2_8), (sum_8)), (sum_8))
> +#define SET_FLAGS_OSZAP_ADD_16(op1_16, op2_16, sum_16) \
> + SET_FLAGS_OSZAP_16(ADD_COUT_VEC((op1_16), (op2_16), (sum_16)), (sum_16))
> +#define SET_FLAGS_OSZAP_ADD_32(op1_32, op2_32, sum_32) \
> + SET_FLAGS_OSZAP_32(ADD_COUT_VEC((op1_32), (op2_32), (sum_32)), (sum_32))
> +
> +/* op1, op2, result */
> +#define SET_FLAGS_OSZAP_SUB_8(op1_8, op2_8, diff_8) \
> + SET_FLAGS_OSZAP_8(SUB_COUT_VEC((op1_8), (op2_8), (diff_8)), (diff_8))
> +#define SET_FLAGS_OSZAP_SUB_16(op1_16, op2_16, diff_16) \
> + SET_FLAGS_OSZAP_16(SUB_COUT_VEC((op1_16), (op2_16), (diff_16)), (diff_16))
> +#define SET_FLAGS_OSZAP_SUB_32(op1_32, op2_32, diff_32) \
> + SET_FLAGS_OSZAP_32(SUB_COUT_VEC((op1_32), (op2_32), (diff_32)), (diff_32))
> +
> +// *******************
> +// OSZAxC
> +// *******************
> +/* size, carries, result */
> +#define SET_FLAGS_OSZAxC_LOGIC_SIZE(size, lf_result) { \
> + bool saved_PF = getB_PF(); \
> + SET_FLAGS_OSZAPC_SIZE(size, (int##size##_t)(0), lf_result); \
> + set_PF(saved_PF); \
> +}
> +
> +/* result */
> +#define SET_FLAGS_OSZAxC_LOGIC_32(result_32) \
> + SET_FLAGS_OSZAxC_LOGIC_SIZE(32, (result_32))
> +
> +void lflags_to_rflags(struct CPUState *cpu);
> +void rflags_to_lflags(struct CPUState *cpu);
> +
> +bool get_PF(struct CPUState *cpu);
> +void set_PF(struct CPUState *cpu, bool val);
> +bool get_CF(struct CPUState *cpu);
> +void set_CF(struct CPUState *cpu, bool val);
> +bool get_AF(struct CPUState *cpu);
> +void set_AF(struct CPUState *cpu, bool val);
> +bool get_ZF(struct CPUState *cpu);
> +void set_ZF(struct CPUState *cpu, bool val);
> +bool get_SF(struct CPUState *cpu);
> +void set_SF(struct CPUState *cpu, bool val);
> +bool get_OF(struct CPUState *cpu);
> +void set_OF(struct CPUState *cpu, bool val);
> +void set_OSZAPC(struct CPUState *cpu, uint32_t flags32);
> +
> +void SET_FLAGS_OxxxxC(struct CPUState *cpu, uint32_t new_of, uint32_t new_cf);
> +
> +void SET_FLAGS_OSZAPC_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
> +void SET_FLAGS_OSZAPC_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
> +void SET_FLAGS_OSZAPC_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
> +
> +void SET_FLAGS_OSZAPC_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
> +void SET_FLAGS_OSZAPC_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
> +void SET_FLAGS_OSZAPC_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
> +
> +void SET_FLAGS_OSZAP_SUB32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
> +void SET_FLAGS_OSZAP_SUB16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
> +void SET_FLAGS_OSZAP_SUB8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
> +
> +void SET_FLAGS_OSZAP_ADD32(struct CPUState *cpu, uint32_t v1, uint32_t v2, uint32_t diff);
> +void SET_FLAGS_OSZAP_ADD16(struct CPUState *cpu, uint16_t v1, uint16_t v2, uint16_t diff);
> +void SET_FLAGS_OSZAP_ADD8(struct CPUState *cpu, uint8_t v1, uint8_t v2, uint8_t diff);
> +
> +void SET_FLAGS_OSZAPC_LOGIC32(struct CPUState *cpu, uint32_t diff);
> +void SET_FLAGS_OSZAPC_LOGIC16(struct CPUState *cpu, uint16_t diff);
> +void SET_FLAGS_OSZAPC_LOGIC8(struct CPUState *cpu, uint8_t diff);
> +
> +void SET_FLAGS_SHR32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
> +void SET_FLAGS_SHR16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
> +void SET_FLAGS_SHR8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
> +
> +void SET_FLAGS_SAR32(struct CPUState *cpu, int32_t v, int count, uint32_t res);
> +void SET_FLAGS_SAR16(struct CPUState *cpu, int16_t v, int count, uint16_t res);
> +void SET_FLAGS_SAR8(struct CPUState *cpu, int8_t v, int count, uint8_t res);
> +
> +void SET_FLAGS_SHL32(struct CPUState *cpu, uint32_t v, int count, uint32_t res);
> +void SET_FLAGS_SHL16(struct CPUState *cpu, uint16_t v, int count, uint16_t res);
> +void SET_FLAGS_SHL8(struct CPUState *cpu, uint8_t v, int count, uint8_t res);
> +
> +#endif /* __X86_FLAGS_H__ */
> diff --git a/target/i386/hvf-utils/x86_gen.h b/target/i386/hvf-utils/x86_gen.h
> new file mode 100644
> index 0000000000..770ee80100
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_gen.h
> @@ -0,0 +1,36 @@
> +#ifndef __X86_GEN_H__
> +#define __X86_GEN_H__
> +
> +#include <stdlib.h>
> +#include <stdio.h>
> +#include "qemu-common.h"
> +
> +typedef uint64_t addr_t;
> +
> +#define VM_PANIC(x) {\
> + printf("%s\n", x); \
> + abort(); \
> +}
> +
> +#define VM_PANIC_ON(x) {\
> + if (x) { \
> + printf("%s\n", #x); \
> + abort(); \
> + } \
> +}
> +
> +#define VM_PANIC_EX(...) {\
> + printf(__VA_ARGS__); \
> + abort(); \
> +}
> +
> +#define VM_PANIC_ON_EX(x, ...) {\
> + if (x) { \
> + printf(__VA_ARGS__); \
> + abort(); \
> + } \
> +}
> +
> +#define ZERO_INIT(obj) memset((void *) &obj, 0, sizeof(obj))
> +
> +#endif
> diff --git a/target/i386/hvf-utils/x86_mmu.c b/target/i386/hvf-utils/x86_mmu.c
> new file mode 100644
> index 0000000000..00fae735be
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_mmu.c
> @@ -0,0 +1,254 @@
> +/*
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#include "qemu/osdep.h"
> +
> +#include "qemu-common.h"
> +#include "x86.h"
> +#include "x86_mmu.h"
> +#include "string.h"
> +#include "vmcs.h"
> +#include "vmx.h"
> +
> +#include "memory.h"
> +#include "exec/address-spaces.h"
> +
> +#define pte_present(pte) (pte & PT_PRESENT)
> +#define pte_write_access(pte) (pte & PT_WRITE)
> +#define pte_user_access(pte) (pte & PT_USER)
> +#define pte_exec_access(pte) (!(pte & PT_NX))
> +
> +#define pte_large_page(pte) (pte & PT_PS)
> +#define pte_global_access(pte) (pte & PT_GLOBAL)
> +
> +#define PAE_CR3_MASK (~0x1fllu)
> +#define LEGACY_CR3_MASK (0xffffffff)
> +
> +#define LEGACY_PTE_PAGE_MASK (0xffffffffllu << 12)
> +#define PAE_PTE_PAGE_MASK ((-1llu << 12) & ((1llu << 52) - 1))
> +#define PAE_PTE_LARGE_PAGE_MASK ((-1llu << (21)) & ((1llu << 52) - 1))
> +
> +struct gpt_translation {
> + addr_t gva;
> + addr_t gpa;
> + int err_code;
> + uint64_t pte[5];
> + bool write_access;
> + bool user_access;
> + bool exec_access;
> +};
> +
> +static int gpt_top_level(struct CPUState *cpu, bool pae)
> +{
> + if (!pae)
> + return 2;
> + if (x86_is_long_mode(cpu))
> + return 4;
> +
> + return 3;
> +}
> +
> +static inline int gpt_entry(addr_t addr, int level, bool pae)
> +{
> + int level_shift = pae ? 9 : 10;
> + return (addr >> (level_shift * (level - 1) + 12)) & ((1 << level_shift) - 1);
> +}
> +
> +static inline int pte_size(bool pae)
> +{
> + return pae ? 8 : 4;
> +}
> +
> +
> +static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool pae)
> +{
> + int index;
> + uint64_t pte = 0;
> + addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
> + addr_t gpa = pt->pte[level] & page_mask;
> +
> + if (level == 3 && !x86_is_long_mode(cpu))
> + gpa = pt->pte[level];
> +
> + index = gpt_entry(pt->gva, level, pae);
> + address_space_rw(&address_space_memory, gpa + index * pte_size(pae), MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0);
> +
> + pt->pte[level - 1] = pte;
> +
> + return true;
> +}
> +
> +/* test page table entry */
> +static bool test_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, int level, bool *is_large, bool pae)
> +{
> + uint64_t pte = pt->pte[level];
> +
> + if (pt->write_access)
> + pt->err_code |= MMU_PAGE_WT;
> + if (pt->user_access)
> + pt->err_code |= MMU_PAGE_US;
> + if (pt->exec_access)
> + pt->err_code |= MMU_PAGE_NX;
> +
> + if (!pte_present(pte)) {
> + addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
> + return false;
> + }
> +
> + if (pae && !x86_is_long_mode(cpu) && 2 == level)
> + goto exit;
> +
> + if (1 == level && pte_large_page(pte)) {
> + pt->err_code |= MMU_PAGE_PT;
> + *is_large = true;
> + }
> + if (!level)
> + pt->err_code |= MMU_PAGE_PT;
> +
> + addr_t cr0 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR0);
> + /* check protection */
> + if (cr0 & CR0_WP) {
> + if (pt->write_access && !pte_write_access(pte)) {
> + return false;
> + }
> + }
> +
> + if (pt->user_access && !pte_user_access(pte)) {
> + return false;
> + }
> +
> + if (pae && pt->exec_access && !pte_exec_access(pte)) {
> + return false;
> + }
> +
> +exit:
> + /* TODO: check reserved bits */
> + return true;
> +}
> +
> +static inline uint64_t pse_pte_to_page(uint64_t pte)
> +{
> + return ((pte & 0x1fe000) << 19) | (pte & 0xffc00000);
> +}
> +
> +static inline uint64_t large_page_gpa(struct gpt_translation *pt, bool pae)
> +{
> + VM_PANIC_ON(!pte_large_page(pt->pte[1]))
> + /* 2Mb large page */
> + if (pae)
> + return (pt->pte[1] & PAE_PTE_LARGE_PAGE_MASK) | (pt->gva & 0x1fffff);
> +
> + /* 4Mb large page */
> + return pse_pte_to_page(pt->pte[1]) | (pt->gva & 0x3fffff);
> +}
> +
> +
> +
> +static bool walk_gpt(struct CPUState *cpu, addr_t addr, int err_code, struct gpt_translation* pt, bool pae)
> +{
> + int top_level, level;
> + bool is_large = false;
> + addr_t cr3 = rvmcs(cpu->hvf_fd, VMCS_GUEST_CR3);
> + addr_t page_mask = pae ? PAE_PTE_PAGE_MASK : LEGACY_PTE_PAGE_MASK;
> +
> + memset(pt, 0, sizeof(*pt));
> + top_level = gpt_top_level(cpu, pae);
> +
> + pt->pte[top_level] = pae ? (cr3 & PAE_CR3_MASK) : (cr3 & LEGACY_CR3_MASK);
> + pt->gva = addr;
> + pt->user_access = (err_code & MMU_PAGE_US);
> + pt->write_access = (err_code & MMU_PAGE_WT);
> + pt->exec_access = (err_code & MMU_PAGE_NX);
> +
> + for (level = top_level; level > 0; level--) {
> + get_pt_entry(cpu, pt, level, pae);
> +
> + if (!test_pt_entry(cpu, pt, level - 1, &is_large, pae)) {
> + return false;
> + }
> +
> + if (is_large)
> + break;
> + }
> +
> + if (!is_large)
> + pt->gpa = (pt->pte[0] & page_mask) | (pt->gva & 0xfff);
> + else
> + pt->gpa = large_page_gpa(pt, pae);
> +
> + return true;
> +}
> +
> +
> +bool mmu_gva_to_gpa(struct CPUState *cpu, addr_t gva, addr_t *gpa)
> +{
> + bool res;
> + struct gpt_translation pt;
> + int err_code = 0;
> +
> + if (!x86_is_paging_mode(cpu)) {
> + *gpa = gva;
> + return true;
> + }
> +
> + res = walk_gpt(cpu, gva, err_code, &pt, x86_is_pae_enabled(cpu));
> + if (res) {
> + *gpa = pt.gpa;
> + return true;
> + }
> +
> + return false;
> +}
> +
> +void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes)
> +{
> + addr_t gpa;
> +
> + while (bytes > 0) {
> + // copy page
> + int copy = MIN(bytes, 0x1000 - (gva & 0xfff));
> +
> + if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
> + VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
> + } else {
> + address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 1);
> + }
> +
> + bytes -= copy;
> + gva += copy;
> + data += copy;
> + }
> +}
> +
> +void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes)
> +{
> + addr_t gpa;
> +
> + while (bytes > 0) {
> + // copy page
> + int copy = MIN(bytes, 0x1000 - (gva & 0xfff));
> +
> + if (!mmu_gva_to_gpa(cpu, gva, &gpa)) {
> + VM_PANIC_ON_EX(1, "%s: mmu_gva_to_gpa %llx failed\n", __FUNCTION__, gva);
> + }
> + address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, data, copy, 0);
> +
> + bytes -= copy;
> + gva += copy;
> + data += copy;
> + }
> +}
> diff --git a/target/i386/hvf-utils/x86_mmu.h b/target/i386/hvf-utils/x86_mmu.h
> new file mode 100644
> index 0000000000..c31bf28982
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86_mmu.h
> @@ -0,0 +1,28 @@
> +#ifndef __X86_MMU_H__
> +#define __X86_MMU_H__
> +
> +#include "x86_gen.h"
> +
> +#define PT_PRESENT (1 << 0)
> +#define PT_WRITE (1 << 1)
> +#define PT_USER (1 << 2)
> +#define PT_WT (1 << 3)
> +#define PT_CD (1 << 4)
> +#define PT_ACCESSED (1 << 5)
> +#define PT_DIRTY (1 << 6)
> +#define PT_PS (1 << 7)
> +#define PT_GLOBAL (1 << 8)
> +#define PT_NX (1llu << 63)
> +
> +// error codes
> +#define MMU_PAGE_PT (1 << 0)
> +#define MMU_PAGE_WT (1 << 1)
> +#define MMU_PAGE_US (1 << 2)
> +#define MMU_PAGE_NX (1 << 3)
> +
> +bool mmu_gva_to_gpa(struct CPUState *cpu, addr_t gva, addr_t *gpa);
> +
> +void vmx_write_mem(struct CPUState* cpu, addr_t gva, void *data, int bytes);
> +void vmx_read_mem(struct CPUState* cpu, void *data, addr_t gva, int bytes);
> +
> +#endif /* __X86_MMU_H__ */
> diff --git a/target/i386/hvf-utils/x86hvf.c b/target/i386/hvf-utils/x86hvf.c
> new file mode 100644
> index 0000000000..d5668df37f
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86hvf.c
> @@ -0,0 +1,501 @@
> +/*
> + * Copyright (c) 2003-2008 Fabrice Bellard
> + * Copyright (C) 2016 Veertu Inc,
> + * Copyright (C) 2017 Google Inc,
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +
> +#include "x86hvf.h"
> +#include "vmx.h"
> +#include "vmcs.h"
> +#include "cpu.h"
> +#include "x86_descr.h"
> +#include "x86_decode.h"
> +
> +#include "hw/i386/apic_internal.h"
> +
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <Hypervisor/hv.h>
> +#include <Hypervisor/hv_vmx.h>
> +#include <stdint.h>
> +
> +void hvf_cpu_synchronize_state(struct CPUState* cpu_state);
> +
> +void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr)
> +{
> + vmx_seg->sel = qseg->selector;
> + vmx_seg->base = qseg->base;
> + vmx_seg->limit = qseg->limit;
> +
> + if (!qseg->selector && !x86_is_real(cpu) && !is_tr) {
> + // the TR register is usable after processor reset despite having a null selector
> + vmx_seg->ar = 1 << 16;
> + return;
> + }
> + vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf;
> + vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15;
> + vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14;
> + vmx_seg->ar |= ((qseg->flags >> DESC_L_SHIFT) & 1) << 13;
> + vmx_seg->ar |= ((qseg->flags >> DESC_AVL_SHIFT) & 1) << 12;
> + vmx_seg->ar |= ((qseg->flags >> DESC_P_SHIFT) & 1) << 7;
> + vmx_seg->ar |= ((qseg->flags >> DESC_DPL_SHIFT) & 3) << 5;
> + vmx_seg->ar |= ((qseg->flags >> DESC_S_SHIFT) & 1) << 4;
> +}
> +
> +void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg)
> +{
> + qseg->limit = vmx_seg->limit;
> + qseg->base = vmx_seg->base;
> + qseg->selector = vmx_seg->sel;
> + qseg->flags = ((vmx_seg->ar & 0xf) << DESC_TYPE_SHIFT) |
> + (((vmx_seg->ar >> 4) & 1) << DESC_S_SHIFT) |
> + (((vmx_seg->ar >> 5) & 3) << DESC_DPL_SHIFT) |
> + (((vmx_seg->ar >> 7) & 1) << DESC_P_SHIFT) |
> + (((vmx_seg->ar >> 12) & 1) << DESC_AVL_SHIFT) |
> + (((vmx_seg->ar >> 13) & 1) << DESC_L_SHIFT) |
> + (((vmx_seg->ar >> 14) & 1) << DESC_B_SHIFT) |
> + (((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT);
> +}
> +
> +void hvf_put_xsave(CPUState *cpu_state)
> +{
> +
> + int x;
> + struct hvf_xsave_buf *xsave;
> +
> + xsave = X86_CPU(cpu_state)->env.kvm_xsave_buf;
> + memset(xsave, 0, sizeof(*xsave));
> +
> + memcpy(&xsave->data[4], &X86_CPU(cpu_state)->env.fpdp, sizeof(X86_CPU(cpu_state)->env.fpdp));
> + memcpy(&xsave->data[2], &X86_CPU(cpu_state)->env.fpip, sizeof(X86_CPU(cpu_state)->env.fpip));
> + memcpy(&xsave->data[8], &X86_CPU(cpu_state)->env.fpregs, sizeof(X86_CPU(cpu_state)->env.fpregs));
> + memcpy(&xsave->data[144], &X86_CPU(cpu_state)->env.ymmh_regs, sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
> + memcpy(&xsave->data[288], &X86_CPU(cpu_state)->env.zmmh_regs, sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
> + memcpy(&xsave->data[272], &X86_CPU(cpu_state)->env.opmask_regs, sizeof(X86_CPU(cpu_state)->env.opmask_regs));
> + memcpy(&xsave->data[240], &X86_CPU(cpu_state)->env.bnd_regs, sizeof(X86_CPU(cpu_state)->env.bnd_regs));
> + memcpy(&xsave->data[256], &X86_CPU(cpu_state)->env.bndcs_regs, sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
> + memcpy(&xsave->data[416], &X86_CPU(cpu_state)->env.hi16_zmm_regs, sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
> +
> + xsave->data[0] = (uint16_t)X86_CPU(cpu_state)->env.fpuc;
> + xsave->data[0] |= (X86_CPU(cpu_state)->env.fpus << 16);
> + xsave->data[0] |= (X86_CPU(cpu_state)->env.fpstt & 7) << 11;
> +
> + for (x = 0; x < 8; ++x)
> + xsave->data[1] |= ((!X86_CPU(cpu_state)->env.fptags[x]) << x);
> + xsave->data[1] |= (uint32_t)(X86_CPU(cpu_state)->env.fpop << 16);
> +
> + memcpy(&xsave->data[40], &X86_CPU(cpu_state)->env.xmm_regs, sizeof(X86_CPU(cpu_state)->env.xmm_regs));
> +
> + xsave->data[6] = X86_CPU(cpu_state)->env.mxcsr;
> + *(uint64_t *)&xsave->data[128] = X86_CPU(cpu_state)->env.xstate_bv;
> +
> + if (hv_vcpu_write_fpstate(cpu_state->hvf_fd, xsave->data, 4096)){
> + abort();
> + }
> +}
> +
> +void vmx_update_tpr(CPUState *cpu);
> +void hvf_put_segments(CPUState *cpu_state)
> +{
> + CPUX86State *env = &X86_CPU(cpu_state)->env;
> + struct vmx_segment seg;
> +
> + wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
> + wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
> +
> + wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
> + wvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
> +
> + //wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR2, env->cr[2]);
> + wvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3, env->cr[3]);
> + vmx_update_tpr(cpu_state);
> + wvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER, env->efer);
> +
> + macvm_set_cr4(cpu_state->hvf_fd, env->cr[4]);
> + macvm_set_cr0(cpu_state->hvf_fd, env->cr[0]);
> +
> + hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_CS);
> +
> + hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_DS);
> +
> + hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_ES);
> +
> + hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_SS);
> +
> + hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_FS);
> +
> + hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_GS);
> +
> + hvf_set_segment(cpu_state, &seg, &env->tr, true);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_TR);
> +
> + hvf_set_segment(cpu_state, &seg, &env->ldt, false);
> + vmx_write_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR);
> +
> + hv_vcpu_flush(cpu_state->hvf_fd);
> +}
> +
> +void hvf_put_msrs(CPUState *cpu_state)
> +{
> + CPUX86State *env = &X86_CPU(cpu_state)->env;
> +
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
> +
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_STAR, env->star);
> +
> +#ifdef TARGET_X86_64
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_CSTAR, env->cstar);
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, env->kernelgsbase);
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FMASK, env->fmask);
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_LSTAR, env->lstar);
> +#endif
> +
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_GSBASE, env->segs[R_GS].base);
> + hv_vcpu_write_msr(cpu_state->hvf_fd, MSR_FSBASE, env->segs[R_FS].base);
> +
> + // if (!osx_is_sierra())
> + // wvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET, env->tsc - rdtscp());
> + hv_vm_sync_tsc(env->tsc);
> +}
> +
> +
> +void hvf_get_xsave(CPUState *cpu_state)
> +{
> + int x;
> + struct hvf_xsave_buf *xsave;
> +
> + xsave = X86_CPU(cpu_state)->env.kvm_xsave_buf;
> +
> + if (hv_vcpu_read_fpstate(cpu_state->hvf_fd, xsave->data, 4096)) {
> + abort();
> + }
> +
> + memcpy(&X86_CPU(cpu_state)->env.fpdp, &xsave->data[4], sizeof(X86_CPU(cpu_state)->env.fpdp));
> + memcpy(&X86_CPU(cpu_state)->env.fpip, &xsave->data[2], sizeof(X86_CPU(cpu_state)->env.fpip));
> + memcpy(&X86_CPU(cpu_state)->env.fpregs, &xsave->data[8], sizeof(X86_CPU(cpu_state)->env.fpregs));
> + memcpy(&X86_CPU(cpu_state)->env.ymmh_regs, &xsave->data[144], sizeof(X86_CPU(cpu_state)->env.ymmh_regs));
> + memcpy(&X86_CPU(cpu_state)->env.zmmh_regs, &xsave->data[288], sizeof(X86_CPU(cpu_state)->env.zmmh_regs));
> + memcpy(&X86_CPU(cpu_state)->env.opmask_regs, &xsave->data[272], sizeof(X86_CPU(cpu_state)->env.opmask_regs));
> + memcpy(&X86_CPU(cpu_state)->env.bnd_regs, &xsave->data[240], sizeof(X86_CPU(cpu_state)->env.bnd_regs));
> + memcpy(&X86_CPU(cpu_state)->env.bndcs_regs, &xsave->data[256], sizeof(X86_CPU(cpu_state)->env.bndcs_regs));
> + memcpy(&X86_CPU(cpu_state)->env.hi16_zmm_regs, &xsave->data[416], sizeof(X86_CPU(cpu_state)->env.hi16_zmm_regs));
> +
> +
> + X86_CPU(cpu_state)->env.fpuc = (uint16_t)xsave->data[0];
> + X86_CPU(cpu_state)->env.fpus = (uint16_t)(xsave->data[0] >> 16);
> + X86_CPU(cpu_state)->env.fpstt = (X86_CPU(cpu_state)->env.fpus >> 11) & 7;
> + X86_CPU(cpu_state)->env.fpop = (uint16_t)(xsave->data[1] >> 16);
> +
> + for (x = 0; x < 8; ++x)
> + X86_CPU(cpu_state)->env.fptags[x] =
> + ((((uint16_t)xsave->data[1] >> x) & 1) == 0);
> +
> + memcpy(&X86_CPU(cpu_state)->env.xmm_regs, &xsave->data[40], sizeof(X86_CPU(cpu_state)->env.xmm_regs));
> +
> + X86_CPU(cpu_state)->env.mxcsr = xsave->data[6];
> + X86_CPU(cpu_state)->env.xstate_bv = *(uint64_t *)&xsave->data[128];
> +}
> +
> +void hvf_get_segments(CPUState *cpu_state)
> +{
> + CPUX86State *env = &X86_CPU(cpu_state)->env;
> +
> + struct vmx_segment seg;
> +
> + env->interrupt_injected = -1;
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_CS);
> + hvf_get_segment(&env->segs[R_CS], &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_DS);
> + hvf_get_segment(&env->segs[R_DS], &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_ES);
> + hvf_get_segment(&env->segs[R_ES], &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_FS);
> + hvf_get_segment(&env->segs[R_FS], &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_GS);
> + hvf_get_segment(&env->segs[R_GS], &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_SS);
> + hvf_get_segment(&env->segs[R_SS], &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_TR);
> + hvf_get_segment(&env->tr, &seg);
> +
> + vmx_read_segment_descriptor(cpu_state, &seg, REG_SEG_LDTR);
> + hvf_get_segment(&env->ldt, &seg);
> +
> + env->idt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_LIMIT);
> + env->idt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IDTR_BASE);
> + env->gdt.limit = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_LIMIT);
> + env->gdt.base = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_GDTR_BASE);
> +
> + env->cr[0] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR0);
> + env->cr[2] = 0;
> + env->cr[3] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR3);
> + env->cr[4] = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_CR4);
> +
> + env->efer = rvmcs(cpu_state->hvf_fd, VMCS_GUEST_IA32_EFER);
> +}
> +
> +void hvf_get_msrs(CPUState *cpu_state)
> +{
> + CPUX86State *env = &X86_CPU(cpu_state)->env;
> + uint64_t tmp;
> +
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_CS, &tmp);
> + env->sysenter_cs = tmp;
> +
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_ESP, &tmp);
> + env->sysenter_esp = tmp;
> +
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_SYSENTER_EIP, &tmp);
> + env->sysenter_eip = tmp;
> +
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_STAR, &env->star);
> +
> +#ifdef TARGET_X86_64
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_CSTAR, &env->cstar);
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_KERNELGSBASE, &env->kernelgsbase);
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_FMASK, &env->fmask);
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_LSTAR, &env->lstar);
> +#endif
> +
> + hv_vcpu_read_msr(cpu_state->hvf_fd, MSR_IA32_APICBASE, &tmp);
> +
> + env->tsc = rdtscp() + rvmcs(cpu_state->hvf_fd, VMCS_TSC_OFFSET);
> +}
> +
> +int hvf_put_registers(CPUState *cpu_state)
> +{
> + X86CPU *x86cpu = X86_CPU(cpu_state);
> + CPUX86State *env = &x86cpu->env;
> +
> + wreg(cpu_state->hvf_fd, HV_X86_RAX, env->regs[R_EAX]);
> + wreg(cpu_state->hvf_fd, HV_X86_RBX, env->regs[R_EBX]);
> + wreg(cpu_state->hvf_fd, HV_X86_RCX, env->regs[R_ECX]);
> + wreg(cpu_state->hvf_fd, HV_X86_RDX, env->regs[R_EDX]);
> + wreg(cpu_state->hvf_fd, HV_X86_RBP, env->regs[R_EBP]);
> + wreg(cpu_state->hvf_fd, HV_X86_RSP, env->regs[R_ESP]);
> + wreg(cpu_state->hvf_fd, HV_X86_RSI, env->regs[R_ESI]);
> + wreg(cpu_state->hvf_fd, HV_X86_RDI, env->regs[R_EDI]);
> + wreg(cpu_state->hvf_fd, HV_X86_R8, env->regs[8]);
> + wreg(cpu_state->hvf_fd, HV_X86_R9, env->regs[9]);
> + wreg(cpu_state->hvf_fd, HV_X86_R10, env->regs[10]);
> + wreg(cpu_state->hvf_fd, HV_X86_R11, env->regs[11]);
> + wreg(cpu_state->hvf_fd, HV_X86_R12, env->regs[12]);
> + wreg(cpu_state->hvf_fd, HV_X86_R13, env->regs[13]);
> + wreg(cpu_state->hvf_fd, HV_X86_R14, env->regs[14]);
> + wreg(cpu_state->hvf_fd, HV_X86_R15, env->regs[15]);
> + wreg(cpu_state->hvf_fd, HV_X86_RFLAGS, env->eflags);
> + wreg(cpu_state->hvf_fd, HV_X86_RIP, env->eip);
> +
> + wreg(cpu_state->hvf_fd, HV_X86_XCR0, env->xcr0);
> +
> + hvf_put_xsave(cpu_state);
> +
> + hvf_put_segments(cpu_state);
> +
> + hvf_put_msrs(cpu_state);
> +
> + wreg(cpu_state->hvf_fd, HV_X86_DR0, env->dr[0]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR1, env->dr[1]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR2, env->dr[2]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR3, env->dr[3]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR4, env->dr[4]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR5, env->dr[5]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR6, env->dr[6]);
> + wreg(cpu_state->hvf_fd, HV_X86_DR7, env->dr[7]);
> +
> + return 0;
> +}
> +
> +int hvf_get_registers(CPUState *cpu_state)
> +{
> + X86CPU *x86cpu = X86_CPU(cpu_state);
> + CPUX86State *env = &x86cpu->env;
> +
> +
> + env->regs[R_EAX] = rreg(cpu_state->hvf_fd, HV_X86_RAX);
> + env->regs[R_EBX] = rreg(cpu_state->hvf_fd, HV_X86_RBX);
> + env->regs[R_ECX] = rreg(cpu_state->hvf_fd, HV_X86_RCX);
> + env->regs[R_EDX] = rreg(cpu_state->hvf_fd, HV_X86_RDX);
> + env->regs[R_EBP] = rreg(cpu_state->hvf_fd, HV_X86_RBP);
> + env->regs[R_ESP] = rreg(cpu_state->hvf_fd, HV_X86_RSP);
> + env->regs[R_ESI] = rreg(cpu_state->hvf_fd, HV_X86_RSI);
> + env->regs[R_EDI] = rreg(cpu_state->hvf_fd, HV_X86_RDI);
> + env->regs[8] = rreg(cpu_state->hvf_fd, HV_X86_R8);
> + env->regs[9] = rreg(cpu_state->hvf_fd, HV_X86_R9);
> + env->regs[10] = rreg(cpu_state->hvf_fd, HV_X86_R10);
> + env->regs[11] = rreg(cpu_state->hvf_fd, HV_X86_R11);
> + env->regs[12] = rreg(cpu_state->hvf_fd, HV_X86_R12);
> + env->regs[13] = rreg(cpu_state->hvf_fd, HV_X86_R13);
> + env->regs[14] = rreg(cpu_state->hvf_fd, HV_X86_R14);
> + env->regs[15] = rreg(cpu_state->hvf_fd, HV_X86_R15);
> +
> + env->eflags = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
> + env->eip = rreg(cpu_state->hvf_fd, HV_X86_RIP);
> +
> + hvf_get_xsave(cpu_state);
> + env->xcr0 = rreg(cpu_state->hvf_fd, HV_X86_XCR0);
> +
> + hvf_get_segments(cpu_state);
> + hvf_get_msrs(cpu_state);
> +
> + env->dr[0] = rreg(cpu_state->hvf_fd, HV_X86_DR0);
> + env->dr[1] = rreg(cpu_state->hvf_fd, HV_X86_DR1);
> + env->dr[2] = rreg(cpu_state->hvf_fd, HV_X86_DR2);
> + env->dr[3] = rreg(cpu_state->hvf_fd, HV_X86_DR3);
> + env->dr[4] = rreg(cpu_state->hvf_fd, HV_X86_DR4);
> + env->dr[5] = rreg(cpu_state->hvf_fd, HV_X86_DR5);
> + env->dr[6] = rreg(cpu_state->hvf_fd, HV_X86_DR6);
> + env->dr[7] = rreg(cpu_state->hvf_fd, HV_X86_DR7);
> +
> + return 0;
> +}
> +
> +static void vmx_set_int_window_exiting(CPUState *cpu)
> +{
> + uint64_t val;
> + val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
> + wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val | VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
> +}
> +
> +void vmx_clear_int_window_exiting(CPUState *cpu)
> +{
> + uint64_t val;
> + val = rvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS);
> + wvmcs(cpu->hvf_fd, VMCS_PRI_PROC_BASED_CTLS, val & ~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
> +}
> +
> +#define NMI_VEC 2
> +
> +void hvf_inject_interrupts(CPUState *cpu_state)
> +{
> + X86CPU *x86cpu = X86_CPU(cpu_state);
> + int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) & VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
> +
> + uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);
> + uint64_t info = 0;
> +
> + if (idt_info & VMCS_IDT_VEC_VALID) {
> + uint8_t vector = idt_info & 0xff;
> + uint64_t intr_type = idt_info & VMCS_INTR_T_MASK;
> + info = idt_info;
> +
> + uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON);
> + if (intr_type == VMCS_INTR_T_NMI && reason != EXIT_REASON_TASK_SWITCH) {
> + allow_nmi = 1;
> + vmx_clear_nmi_blocking(cpu_state);
> + }
> +
> + if ((allow_nmi || intr_type != VMCS_INTR_T_NMI)) {
> + info &= ~(1 << 12); /* clear undefined bit */
> + if (intr_type == VMCS_INTR_T_SWINTR ||
> + intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||
> + intr_type == VMCS_INTR_T_SWEXCEPTION) {
> + uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
> + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
> + }
> + if (vector == EXCEPTION_BP || vector == EXCEPTION_OF) {
> + /*
> + * VT-x requires #BP and #OF to be injected as software
> + * exceptions.
> + */
> + info &= ~VMCS_INTR_T_MASK;
> + info |= VMCS_INTR_T_SWEXCEPTION;
> + uint64_t ins_len = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_INSTRUCTION_LENGTH);
> + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
> + }
> +
> + uint64_t err = 0;
> + if (idt_info & VMCS_INTR_DEL_ERRCODE) {
> + err = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR);
> + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err);
> + }
> + //printf("reinject %lx err %d\n", info, err);
> + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
> + };
> + }
> +
> + if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {
> + if (allow_nmi && !(info & VMCS_INTR_VALID)) {
> + cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
> + info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | NMI_VEC;
> + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
> + } else {
> + vmx_set_nmi_window_exiting(cpu_state);
> + }
> + }
> +
> + if (cpu_state->hvf_x86->interruptable && (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
> + (EFLAGS(cpu_state) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
> + int line = cpu_get_pic_interrupt(&x86cpu->env);
> + cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
> + if (line >= 0)
> + wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
> + }
> + if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD)
> + vmx_set_int_window_exiting(cpu_state);
> +}
> +
> +int hvf_process_events(CPUState *cpu_state)
> +{
> + X86CPU *cpu = X86_CPU(cpu_state);
> + CPUX86State *env = &cpu->env;
> +
> + EFLAGS(cpu_state) = rreg(cpu_state->hvf_fd, HV_X86_RFLAGS);
> +
> + if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
> + hvf_cpu_synchronize_state(cpu_state);
> + do_cpu_init(cpu);
> + }
> +
> + if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) {
> + cpu_state->interrupt_request &= ~CPU_INTERRUPT_POLL;
> + apic_poll_irq(cpu->apic_state);
> + }
> + if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(cpu_state) & IF_MASK)) ||
> + (cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) {
> + cpu_state->halted = 0;
> + }
> + if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) {
> + hvf_cpu_synchronize_state(cpu_state);
> + do_cpu_sipi(cpu);
> + }
> + if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) {
> + cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR;
> + hvf_cpu_synchronize_state(cpu_state);
> + apic_handle_tpr_access_report(cpu->apic_state, env->eip,
> + env->tpr_access_type);
> + }
> + return cpu_state->halted;
> +}
> +
> diff --git a/target/i386/hvf-utils/x86hvf.h b/target/i386/hvf-utils/x86hvf.h
> new file mode 100644
> index 0000000000..b4cb4c4d26
> --- /dev/null
> +++ b/target/i386/hvf-utils/x86hvf.h
> @@ -0,0 +1,19 @@
> +#ifndef X86HVF_H
> +#define X86HVF_H
> +#include "cpu.h"
> +#include "x86_descr.h"
> +
> +int hvf_process_events(CPUState *);
> +int hvf_put_registers(CPUState *);
> +int hvf_get_registers(CPUState *);
> +void hvf_inject_interrupts(CPUState *);
> +void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg, SegmentCache *qseg, bool is_tr);
> +void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg);
> +void hvf_put_xsave(CPUState *cpu_state);
> +void hvf_put_segments(CPUState *cpu_state);
> +void hvf_put_msrs(CPUState *cpu_state);
> +void hvf_get_xsave(CPUState *cpu_state);
> +void hvf_get_msrs(CPUState *cpu_state);
> +void vmx_clear_int_window_exiting(CPUState *cpu);
> +void hvf_get_segments(CPUState *cpu_state);
> +#endif
> --
> 2.14.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 03/14] hvf: add conditional macros around hvf code in cpus.c
2017-08-28 1:56 ` [Qemu-devel] [PATCH 03/14] hvf: add conditional macros around hvf code in cpus.c Sergio Andres Gomez Del Real
@ 2017-08-29 9:19 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:19 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:43PM -0500, Sergio Andres Gomez Del Real wrote:
> @@ -900,6 +904,11 @@ void cpu_synchronize_all_states(void)
>
> CPU_FOREACH(cpu) {
> cpu_synchronize_state(cpu);
> +#ifdef CONFIG_HVF
> + if (hvf_enabled()) {
> + hvf_cpu_synchronize_state(cpu);
> + }
> +#endif
Searching for CONFIG_KVM and CONFIG_HAX in cpus.c produces no results.
How do they solve the same problem without using #ifdef? They define
nop stubs in "system/$ACCEL.h" so that cpus.c does not need #ifdefs.
Please follow the same approach for hvf. Using stubs avoids "bitrot"
because the cpus.c kvm/hax code is always compiled, even when the
feature is disabled. This way no compiler errors/warnings can hide in
the #ifdef regions that aren't compiled by most people.
Please avoid #ifdef whereever possible.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 04/14] hvf: add fields to CPUState and CPUX86State; add definitions
2017-08-28 1:56 ` [Qemu-devel] [PATCH 04/14] hvf: add fields to CPUState and CPUX86State; add definitions Sergio Andres Gomez Del Real
@ 2017-08-29 9:31 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:31 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:44PM -0500, Sergio Andres Gomez Del Real wrote:
> This commit adds some fields specific to hvf in CPUState and
> CPUX86State. It also adds some handy #defines.
>
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
> ---
> include/qom/cpu.h | 8 ++++++++
> target/i386/cpu.h | 23 +++++++++++++++++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 25eefea7ab..c46eb61240 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -407,6 +407,14 @@ struct CPUState {
> * unnecessary flushes.
> */
> uint16_t pending_tlb_flush;
> +
> + // HVF
Please see ./CODING_STYLE "7. Comment style":
We use traditional C-style /* */ comments and avoid // comments.
> + bool hvf_vcpu_dirty;
> + uint64_t hvf_fd; // fd of vcpu created by HVF
File descriptors are ints, why is this uint64_t?
This also raises an issue: none of these fields are used in the patch.
This makes it hard to review the code. I don't know whether the
definitions are correct without seeing the code that uses them.
Please structure the patch series so that patches are self-contained,
logical changes that can be reviewed in isolation. These field
definitions should be made in the same patch uses the fields.
> + // Supporting data structures for VMCS capabilities
> + // and x86 emulation state
> + struct hvf_vcpu_caps* hvf_caps;
> + struct hvf_x86_state* hvf_x86;
Coding style:
1. Please use typedef struct {...} TypeName.
2. Please use TypeName *ptr.
> };
>
> QTAILQ_HEAD(CPUTailQ, CPUState);
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 051867399b..7d90f08b98 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -82,15 +82,19 @@
> #define R_GS 5
>
> /* segment descriptor fields */
> +#define DESC_G_SHIFT 23
> #define DESC_G_MASK (1 << 23)
> #define DESC_B_SHIFT 22
> #define DESC_B_MASK (1 << DESC_B_SHIFT)
> #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
> #define DESC_L_MASK (1 << DESC_L_SHIFT)
> +#define DESC_AVL_SHIFT 20
> #define DESC_AVL_MASK (1 << 20)
> +#define DESC_P_SHIFT 15
> #define DESC_P_MASK (1 << 15)
> #define DESC_DPL_SHIFT 13
> #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
> +#define DESC_S_SHIFT 12
> #define DESC_S_MASK (1 << 12)
Please reuse the new constants to avoid duplication (just like existing
code for DESC_B_MASK does):
#define DESC_S_SHIFT 12
#define DESC_S_MASK (1 << DESC_S_SHIFT)
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 06/14] hvf: add compilation rules to Makefile.objs
2017-08-28 1:56 ` [Qemu-devel] [PATCH 06/14] hvf: add compilation rules to Makefile.objs Sergio Andres Gomez Del Real
@ 2017-08-29 9:34 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:34 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:46PM -0500, Sergio Andres Gomez Del Real wrote:
> This commit adds to target/i386/Makefile.objs the necessary rules so
> that the new files for hvf are compiled by the build system.
> It also adds handling of the -enable-hvf argument in the main function
> in vl.c.
>
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
> ---
> target/i386/Makefile.objs | 1 +
> vl.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/target/i386/Makefile.objs b/target/i386/Makefile.objs
> index 6a26e9d9f0..0bef89c099 100644
> --- a/target/i386/Makefile.objs
> +++ b/target/i386/Makefile.objs
> @@ -12,4 +12,5 @@ obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-windows.o
> endif
> ifdef CONFIG_DARWIN
> obj-$(CONFIG_HAX) += hax-all.o hax-mem.o hax-darwin.o
> +obj-$(CONFIG_HVF) += hvf-utils/ hvf-all.o
> endif
This should be in the commit that imported the .c files. They should be
compiled right away.
> diff --git a/vl.c b/vl.c
> index 8e247cc2a2..de7d2a3858 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -3751,6 +3751,13 @@ int main(int argc, char **argv, char **envp)
> olist = qemu_find_opts("machine");
> qemu_opts_parse_noisily(olist, "accel=hax", false);
> break;
> +#if defined(__APPLE__)
> + case QEMU_OPTION_enable_hvf:
> + olist = qemu_find_opts("machine");
> + qemu_opts_parse_noisily(olist, "accel=hvf", false);
> + hvf_disable(0);
> + break;
> +#endif
This code change is independent of the Makefile.objs change. It should
be a spearate commit.
As mentioned in another email, -enable-hvf should be dropped.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 07/14] hvf: run hvf code through checkpatch.pl and fix style issues
2017-08-28 1:56 ` [Qemu-devel] [PATCH 07/14] hvf: run hvf code through checkpatch.pl and fix style issues Sergio Andres Gomez Del Real
@ 2017-08-29 9:35 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:35 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:47PM -0500, Sergio Andres Gomez Del Real wrote:
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
Please make this the 2nd patch so there are no other patches in between
that modify code that violates coding style.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 08/14] apic: add function to apic that will be used by hvf
2017-08-28 1:56 ` [Qemu-devel] [PATCH 08/14] apic: add function to apic that will be used by hvf Sergio Andres Gomez Del Real
@ 2017-08-29 9:36 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:36 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:48PM -0500, Sergio Andres Gomez Del Real wrote:
> This commit moves (hides) the function apic_get_highest_priority_irr to
> apic.c and exports it through the interface in apic.h for use by hvf.
I don't see a move. This patch only adds a new function. Did you
forget to delete the old function?
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
> ---
> hw/intc/apic.c | 11 +++++++++++
> include/hw/i386/apic.h | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/hw/intc/apic.c b/hw/intc/apic.c
> index fe15fb6024..3de59d07fd 100644
> --- a/hw/intc/apic.c
> +++ b/hw/intc/apic.c
> @@ -305,6 +305,17 @@ static void apic_set_tpr(APICCommonState *s, uint8_t val)
> }
> }
>
> +int apic_get_highest_priority_irr(DeviceState *dev)
> +{
> + APICCommonState *s;
> +
> + if (!dev) {
> + return -1;
> + }
> + s = APIC_COMMON(dev);
> + return get_highest_priority_int(s->irr);
> +}
> +
> static uint8_t apic_get_tpr(APICCommonState *s)
> {
> apic_sync_vapic(s, SYNC_FROM_VAPIC);
> diff --git a/include/hw/i386/apic.h b/include/hw/i386/apic.h
> index ea48ea9389..a9f6c0aa33 100644
> --- a/include/hw/i386/apic.h
> +++ b/include/hw/i386/apic.h
> @@ -20,6 +20,7 @@ void apic_init_reset(DeviceState *s);
> void apic_sipi(DeviceState *s);
> void apic_poll_irq(DeviceState *d);
> void apic_designate_bsp(DeviceState *d, bool bsp);
> +int apic_get_highest_priority_irr(DeviceState *dev);
>
> /* pc.c */
> DeviceState *cpu_get_current_apic(void);
> --
> 2.14.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code
2017-08-28 1:56 ` [Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code Sergio Andres Gomez Del Real
@ 2017-08-29 9:44 ` Stefan Hajnoczi
0 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:44 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:50PM -0500, Sergio Andres Gomez Del Real wrote:
> This commit adds code to request the cpuid features supported by the
> host and hvf; it calls hvf_get_supported_cpuid if hvf is compiled with
> QEMU and enabled.
>
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
> ---
> cpus.c | 2 +
> include/qom/cpu.h | 6 +--
> include/sysemu/hvf.h | 18 ++++++---
> target/i386/cpu-qom.h | 4 +-
> target/i386/cpu.c | 108 ++++++++++++++++++++++++++++++++++++++++----------
> target/i386/hvf-all.c | 20 +++++-----
> 6 files changed, 113 insertions(+), 45 deletions(-)
>
> diff --git a/cpus.c b/cpus.c
> index 6754ce17cc..2411dfcd3f 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -37,7 +37,9 @@
> #include "sysemu/hw_accel.h"
> #include "sysemu/kvm.h"
> #include "sysemu/hax.h"
> +#ifdef CONFIG_HVF
> #include "sysemu/hvf.h"
> +#endif
Please avoid #ifdefs. They are not necessary for kvm or hax.
> #include "qmp-commands.h"
> #include "exec/exec-all.h"
>
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index c46eb61240..ef74c2ce3c 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -408,13 +408,9 @@ struct CPUState {
> */
> uint16_t pending_tlb_flush;
>
> - // HVF
> bool hvf_vcpu_dirty;
> uint64_t hvf_fd; // fd of vcpu created by HVF
> - // Supporting data structures for VMCS capabilities
> - // and x86 emulation state
> - struct hvf_vcpu_caps* hvf_caps;
> - struct hvf_x86_state* hvf_x86;
> + struct hvf_x86_state *hvf_x86;
Please squash this with the change that adds these fields. Patch series
should avoid "code churn" where code is added and then changed again in
the same patch series. Arrange the patch series in a logical order and
squash down commits using git-rebase -i so new code is introduced in its
final state. This makes review easier and the git commit history
cleaner (i.e. easier to bisect, backport, and use git-blame(1)).
There are more instances of code churn below.
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (14 preceding siblings ...)
2017-08-28 7:24 ` [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU no-reply
@ 2017-08-29 9:51 ` Stefan Hajnoczi
2017-08-29 9:53 ` Stefan Hajnoczi
16 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:51 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:40PM -0500, Sergio Andres Gomez Del Real wrote:
> The following patchset adds to QEMU the supporting for macOS's native
> hypervisor, Hypervisor.framework (hvf). The code base is taken from
> Google's Android emulator at
> https://android.googlesource.com/platform/external/qemu/+/emu-master-dev.
What is the status of this feature? Is it expected to run everything
that TCG can run or are there limitations? Is live migration supported,
etc?
How do you test hvf? Are there automated test cases?
Stefan
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
` (15 preceding siblings ...)
2017-08-29 9:51 ` Stefan Hajnoczi
@ 2017-08-29 9:53 ` Stefan Hajnoczi
16 siblings, 0 replies; 27+ messages in thread
From: Stefan Hajnoczi @ 2017-08-29 9:53 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:40PM -0500, Sergio Andres Gomez Del Real wrote:
> The following patchset adds to QEMU the supporting for macOS's native
> hypervisor, Hypervisor.framework (hvf). The code base is taken from
> Google's Android emulator at
> https://android.googlesource.com/platform/external/qemu/+/emu-master-dev.
There is no ./MAINTAINERS entry for these new files.
Who will maintain this code?
Stefan
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository
2017-08-28 1:56 ` [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository Sergio Andres Gomez Del Real
2017-08-29 9:12 ` Stefan Hajnoczi
@ 2017-08-29 11:22 ` Daniel P. Berrange
1 sibling, 0 replies; 27+ messages in thread
From: Daniel P. Berrange @ 2017-08-29 11:22 UTC (permalink / raw)
To: Sergio Andres Gomez Del Real; +Cc: qemu-devel
On Sun, Aug 27, 2017 at 08:56:42PM -0500, Sergio Andres Gomez Del Real wrote:
> This file begins tracking the files that will be the code base for HVF
> support in QEMU.
>
> Signed-off-by: Sergio Andres Gomez Del Real <Sergio.G.DelReal@gmail.com>
> ---
> diff --git a/target/i386/hvf-all.c b/target/i386/hvf-all.c
> new file mode 100644
> index 0000000000..06cd8429eb
> --- /dev/null
> +++ b/target/i386/hvf-all.c
> @@ -0,0 +1,982 @@
There's no copyright header on this file.
A few others a missing copyright headers too, but they're all simple
.h files, so not critical. This, though, is a major .c file so I think
it really should have a copyright header present. IIUC, this is not
your code, but rather copied from the google repo, so ought to get the
original author to update this.
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +
> +#include "sysemu/hvf.h"
> +#include "hvf-i386.h"
> +#include "hvf-utils/vmcs.h"
> +#include "hvf-utils/vmx.h"
> +#include "hvf-utils/x86.h"
> +#include "hvf-utils/x86_descr.h"
> +#include "hvf-utils/x86_mmu.h"
> +#include "hvf-utils/x86_decode.h"
> +#include "hvf-utils/x86_emu.h"
> +#include "hvf-utils/x86_cpuid.h"
> +#include "hvf-utils/x86hvf.h"
> +
> +#include <Hypervisor/hv.h>
> +#include <Hypervisor/hv_vmx.h>
> +
> +#include "exec/address-spaces.h"
> +#include "exec/exec-all.h"
> +#include "exec/ioport.h"
> +#include "hw/i386/apic_internal.h"
> +#include "hw/boards.h"
> +#include "qemu/main-loop.h"
> +#include "strings.h"
> +#include "trace.h"
> +#include "sysemu/accel.h"
> +#include "sysemu/sysemu.h"
> +#include "target/i386/cpu.h"
> +
> +pthread_rwlock_t mem_lock = PTHREAD_RWLOCK_INITIALIZER;
> +HVFState *hvf_state;
> +static int hvf_disabled = 1;
> +
> +static void assert_hvf_ok(hv_return_t ret)
> +{
> + if (ret == HV_SUCCESS)
> + return;
> +
> + switch (ret) {
> + case HV_ERROR:
> + fprintf(stderr, "Error: HV_ERROR\n");
> + break;
> + case HV_BUSY:
> + fprintf(stderr, "Error: HV_BUSY\n");
> + break;
> + case HV_BAD_ARGUMENT:
> + fprintf(stderr, "Error: HV_BAD_ARGUMENT\n");
> + break;
> + case HV_NO_RESOURCES:
> + fprintf(stderr, "Error: HV_NO_RESOURCES\n");
> + break;
> + case HV_NO_DEVICE:
> + fprintf(stderr, "Error: HV_NO_DEVICE\n");
> + break;
> + case HV_UNSUPPORTED:
> + fprintf(stderr, "Error: HV_UNSUPPORTED\n");
> + break;
> + default:
> + fprintf(stderr, "Unknown Error\n");
> + }
> +
> + abort();
> +}
There's loads of fprintfs() throughout this file - it really needs to
be fixed to use error_report()
Regards,
Daniel
--
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^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2017-08-29 11:22 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-28 1:56 [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 01/14] hvf: add support for Hypervisor.framework in the configure script Sergio Andres Gomez Del Real
2017-08-29 9:00 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 02/14] hvf: add code base from Google's QEMU repository Sergio Andres Gomez Del Real
2017-08-29 9:12 ` Stefan Hajnoczi
2017-08-29 11:22 ` Daniel P. Berrange
2017-08-28 1:56 ` [Qemu-devel] [PATCH 03/14] hvf: add conditional macros around hvf code in cpus.c Sergio Andres Gomez Del Real
2017-08-29 9:19 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 04/14] hvf: add fields to CPUState and CPUX86State; add definitions Sergio Andres Gomez Del Real
2017-08-29 9:31 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 05/14] hvf: use new helper functions for put/get xsave Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 06/14] hvf: add compilation rules to Makefile.objs Sergio Andres Gomez Del Real
2017-08-29 9:34 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 07/14] hvf: run hvf code through checkpatch.pl and fix style issues Sergio Andres Gomez Del Real
2017-08-29 9:35 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 08/14] apic: add function to apic that will be used by hvf Sergio Andres Gomez Del Real
2017-08-29 9:36 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 09/14] hvf: implement hvf_get_supported_cpuid Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 10/14] hvf: refactor cpuid code Sergio Andres Gomez Del Real
2017-08-29 9:44 ` Stefan Hajnoczi
2017-08-28 1:56 ` [Qemu-devel] [PATCH 11/14] hvf: implement vga dirty page tracking Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 12/14] hvf: move fields from CPUState to CPUX86State Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 13/14] hvf: refactor event injection code for hvf Sergio Andres Gomez Del Real
2017-08-28 1:56 ` [Qemu-devel] [PATCH 14/14] hvf: inject General Protection Fault when vmexit through vmcall Sergio Andres Gomez Del Real
2017-08-28 7:24 ` [Qemu-devel] [PATCH 00/14] add support for Hypervisor.framework in QEMU no-reply
2017-08-29 9:51 ` Stefan Hajnoczi
2017-08-29 9:53 ` Stefan Hajnoczi
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