From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750908AbdHaFiG (ORCPT ); Thu, 31 Aug 2017 01:38:06 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:56752 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750747AbdHaFiE (ORCPT ); Thu, 31 Aug 2017 01:38:04 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 005A46239E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Wed, 30 Aug 2017 22:38:00 -0700 From: Stephen Boyd To: Eugeniy Paltsev Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, Michael Turquette , Rob Herring , Mark Rutland Subject: Re: [PATCH v4] ARC: clk: introduce HSDK pll driver Message-ID: <20170831053800.GC21656@codeaurora.org> References: <20170825173914.32121-1-Eugeniy.Paltsev@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170825173914.32121-1-Eugeniy.Paltsev@synopsys.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/25, Eugeniy Paltsev wrote: > HSDK board manages its clocks using various PLLs. These PLL have same > dividers and corresponding control registers mapped to different addresses. > So we add one common driver for such PLLs. > > Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and > ODIV. Output clock value is managed using these dividers. > > We add pre-defined tables with supported rate values and appropriate > configurations of IDIV, FBDIV and ODIV for each value. > > As of today we add support for PLLs that generate clock for the > HSDK arc cpus, system, ddr, AXI tunnel and hdmi. > > By this patch we add support for several plls (arc cpus pll and others), > so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll > and regular probing for others plls. > > Signed-off-by: Eugeniy Paltsev > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: sboyd@codeaurora.org (Stephen Boyd) Date: Wed, 30 Aug 2017 22:38:00 -0700 Subject: [PATCH v4] ARC: clk: introduce HSDK pll driver In-Reply-To: <20170825173914.32121-1-Eugeniy.Paltsev@synopsys.com> References: <20170825173914.32121-1-Eugeniy.Paltsev@synopsys.com> List-ID: Message-ID: <20170831053800.GC21656@codeaurora.org> To: linux-snps-arc@lists.infradead.org On 08/25, Eugeniy Paltsev wrote: > HSDK board manages its clocks using various PLLs. These PLL have same > dividers and corresponding control registers mapped to different addresses. > So we add one common driver for such PLLs. > > Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and > ODIV. Output clock value is managed using these dividers. > > We add pre-defined tables with supported rate values and appropriate > configurations of IDIV, FBDIV and ODIV for each value. > > As of today we add support for PLLs that generate clock for the > HSDK arc cpus, system, ddr, AXI tunnel and hdmi. > > By this patch we add support for several plls (arc cpus pll and others), > so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll > and regular probing for others plls. > > Signed-off-by: Eugeniy Paltsev > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project