From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752100AbdIANHK (ORCPT ); Fri, 1 Sep 2017 09:07:10 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:52162 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751911AbdIANHI (ORCPT ); Fri, 1 Sep 2017 09:07:08 -0400 Date: Fri, 1 Sep 2017 15:06:56 +0200 From: Maxime Ripard To: Stefan Mavrodiev Cc: Stefan Mavrodiev , Rob Herring , Mark Rutland , Russell King , Chen-Yu Tsai , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: Re: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 Message-ID: <20170901130656.tfiqepmxxh2zrfee@flea> References: <1503901963-9457-1-git-send-email-stefan@olimex.com> <1503901963-9457-2-git-send-email-stefan@olimex.com> <20170830143728.friajjequvioqjpu@flea.lan> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="igbzx7m6so37linx" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170714 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --igbzx7m6so37linx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Aug 31, 2017 at 08:20:18AM +0300, Stefan Mavrodiev wrote: > > > From revision J the board uses new phy chip LAN8710. Compared > > > with RTL8201, RA17 pin is TXERR. It has pullup which causes phy > > > not to work. To fix this PA17 is muxed with GMAC function. This > > > makes the pin output-low. > > >=20 > > > This patch is compatible with earlier board revisions, since this > > > pin wasn't connected to phy. > > >=20 > > > Signed-off-by: Stefan Mavrodiev > > > --- > > > arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > >=20 > > > diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/a= rm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > index 0b7403e..cb1b081 100644 > > > --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > @@ -102,7 +102,7 @@ > > > &gmac { > > > pinctrl-names =3D "default"; > > > - pinctrl-0 =3D <&gmac_pins_mii_a>; > > > + pinctrl-0 =3D <&gmac_pins_mii_a>,<&gmac_txerr>; > > > phy =3D <&phy1>; > > > phy-mode =3D "mii"; > > > status =3D "okay"; > > > @@ -229,6 +229,11 @@ > > > }; > > > &pio { > > > + gmac_txerr: gmac_txerr@0 { > > > + pins =3D "PA17"; > > > + function =3D "gmac"; > > > + }; > > > + > > The patch looks fine, I still have one question though. > >=20 > > Can a PHY operate without this signal? My real question is, would it > > make sense to mux that pin for all the users, or is it an optional > > signal that each board designer can choose to use or not? > >=20 > > Thanks! > > Maxime > > This phy (LAN8710) cannot work without this pin. Part of the problem > is in that we've replaced without paying attention to this signal. >=20 > RTL8201 has no TXERR pin. The pin PA17 is used as reset signal and > therefore is pulled up with resistor. However on old revisions this > option (there is jumper pad between SOC and PHY). >=20 > As I said, LAN8710 cannot work without this signal. In the datasheet > is written: > > ... > The controller drives TXER high when a transmit error is detected. > ... >=20 > In the current variant of the dts, all data is threated as error. Sorry if my question was unclear, I meant to ask for all PHYs connected to an A20. I got that you were needing it for that particular one :) > So to answer you question. This is feature only on our board and > highly depends on the chosen PHY. I don't think this should be > muxed for all users. Ok, I guess it answers it. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --igbzx7m6so37linx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJZqVtwAAoJEBx+YmzsjxAgPP8QAIVqoYjLl/345HiGHjYDuYm6 eNpVEeeffrIvKMJBkEz3hdijHJXocVtzudm3I+gMGzJcEQxmHPjesS0jqKLpRkAT mWRO8bjES0562StfefshDZtXLjhHFnmal+9nGsvHW43gHW8FuGtGLSR5LVCqgnIP Y9M5M0iOtcZfX3egbYJ9A8NNdC3H/7aPwX85Trxbu2TMwReFSYta6QkkHjiR1sA0 q3uT7a9Pht7WNcHy3TVeKFY7o6aI9PuONNdldIcBVC/lzGHdLIE/qnKhgaOIB/G5 IzSFwfzKxFkbKI8jJ5Cg2XDgDJz0iOlyvuvvlp0pcZfX0U/1sY9Pv6a2pfQSyyEj xHqYIZP7BpCNV6gthG3zerK3m5VRPgqLm5j7obC9E3XlcozqpCnkr2fFc0EPt2tr EHPuXIoiklskfHOKP7Y0fQw7bMbzRKK9udCAi/6NBMnGSjM1UXXh+hlRGfYvIsWz 5ZFAeiljQITMV3sZeOwKldolQhPWOdmfrSM2dnLKyFRE1ZAZl4i4gUijB0K+chRB KPFZRHFysi9pHcpRQjNQ+TzNINWwQOo+U/SOe2H4DbymnlN/GPDRJ6L+IhaVZGhU j9kzPqsNVvRZAUcSo8WSWdkT1qkkOqEHmRSmw1JEkQKhKglGbHdeQUWH0CyVoGVs RSiqVkwEetSKlEgSwpZ3 =3pit -----END PGP SIGNATURE----- --igbzx7m6so37linx-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 Date: Fri, 1 Sep 2017 15:06:56 +0200 Message-ID: <20170901130656.tfiqepmxxh2zrfee@flea> References: <1503901963-9457-1-git-send-email-stefan@olimex.com> <1503901963-9457-2-git-send-email-stefan@olimex.com> <20170830143728.friajjequvioqjpu@flea.lan> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1331137536867260590==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Stefan Mavrodiev Cc: Mark Rutland , devicetree@vger.kernel.org, Stefan Mavrodiev , linux-sunxi@googlegroups.com, Russell King , linux-kernel@vger.kernel.org, Chen-Yu Tsai , Rob Herring , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org --===============1331137536867260590== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="igbzx7m6so37linx" Content-Disposition: inline --igbzx7m6so37linx Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Aug 31, 2017 at 08:20:18AM +0300, Stefan Mavrodiev wrote: > > > From revision J the board uses new phy chip LAN8710. Compared > > > with RTL8201, RA17 pin is TXERR. It has pullup which causes phy > > > not to work. To fix this PA17 is muxed with GMAC function. This > > > makes the pin output-low. > > >=20 > > > This patch is compatible with earlier board revisions, since this > > > pin wasn't connected to phy. > > >=20 > > > Signed-off-by: Stefan Mavrodiev > > > --- > > > arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > >=20 > > > diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/a= rm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > index 0b7403e..cb1b081 100644 > > > --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > @@ -102,7 +102,7 @@ > > > &gmac { > > > pinctrl-names =3D "default"; > > > - pinctrl-0 =3D <&gmac_pins_mii_a>; > > > + pinctrl-0 =3D <&gmac_pins_mii_a>,<&gmac_txerr>; > > > phy =3D <&phy1>; > > > phy-mode =3D "mii"; > > > status =3D "okay"; > > > @@ -229,6 +229,11 @@ > > > }; > > > &pio { > > > + gmac_txerr: gmac_txerr@0 { > > > + pins =3D "PA17"; > > > + function =3D "gmac"; > > > + }; > > > + > > The patch looks fine, I still have one question though. > >=20 > > Can a PHY operate without this signal? My real question is, would it > > make sense to mux that pin for all the users, or is it an optional > > signal that each board designer can choose to use or not? > >=20 > > Thanks! > > Maxime > > This phy (LAN8710) cannot work without this pin. Part of the problem > is in that we've replaced without paying attention to this signal. >=20 > RTL8201 has no TXERR pin. The pin PA17 is used as reset signal and > therefore is pulled up with resistor. However on old revisions this > option (there is jumper pad between SOC and PHY). >=20 > As I said, LAN8710 cannot work without this signal. In the datasheet > is written: > > ... > The controller drives TXER high when a transmit error is detected. > ... >=20 > In the current variant of the dts, all data is threated as error. Sorry if my question was unclear, I meant to ask for all PHYs connected to an A20. I got that you were needing it for that particular one :) > So to answer you question. This is feature only on our board and > highly depends on the chosen PHY. I don't think this should be > muxed for all users. Ok, I guess it answers it. Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com --igbzx7m6so37linx Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJZqVtwAAoJEBx+YmzsjxAgPP8QAIVqoYjLl/345HiGHjYDuYm6 eNpVEeeffrIvKMJBkEz3hdijHJXocVtzudm3I+gMGzJcEQxmHPjesS0jqKLpRkAT mWRO8bjES0562StfefshDZtXLjhHFnmal+9nGsvHW43gHW8FuGtGLSR5LVCqgnIP Y9M5M0iOtcZfX3egbYJ9A8NNdC3H/7aPwX85Trxbu2TMwReFSYta6QkkHjiR1sA0 q3uT7a9Pht7WNcHy3TVeKFY7o6aI9PuONNdldIcBVC/lzGHdLIE/qnKhgaOIB/G5 IzSFwfzKxFkbKI8jJ5Cg2XDgDJz0iOlyvuvvlp0pcZfX0U/1sY9Pv6a2pfQSyyEj xHqYIZP7BpCNV6gthG3zerK3m5VRPgqLm5j7obC9E3XlcozqpCnkr2fFc0EPt2tr EHPuXIoiklskfHOKP7Y0fQw7bMbzRKK9udCAi/6NBMnGSjM1UXXh+hlRGfYvIsWz 5ZFAeiljQITMV3sZeOwKldolQhPWOdmfrSM2dnLKyFRE1ZAZl4i4gUijB0K+chRB KPFZRHFysi9pHcpRQjNQ+TzNINWwQOo+U/SOe2H4DbymnlN/GPDRJ6L+IhaVZGhU j9kzPqsNVvRZAUcSo8WSWdkT1qkkOqEHmRSmw1JEkQKhKglGbHdeQUWH0CyVoGVs RSiqVkwEetSKlEgSwpZ3 =3pit -----END PGP SIGNATURE----- --igbzx7m6so37linx-- --===============1331137536867260590== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============1331137536867260590==-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Fri, 1 Sep 2017 15:06:56 +0200 Subject: [PATCH v2 1/2] ARM: dts: sun7i: Fix A20-OLinuXino-MICRO dts for LAN8710 In-Reply-To: References: <1503901963-9457-1-git-send-email-stefan@olimex.com> <1503901963-9457-2-git-send-email-stefan@olimex.com> <20170830143728.friajjequvioqjpu@flea.lan> Message-ID: <20170901130656.tfiqepmxxh2zrfee@flea> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Aug 31, 2017 at 08:20:18AM +0300, Stefan Mavrodiev wrote: > > > From revision J the board uses new phy chip LAN8710. Compared > > > with RTL8201, RA17 pin is TXERR. It has pullup which causes phy > > > not to work. To fix this PA17 is muxed with GMAC function. This > > > makes the pin output-low. > > > > > > This patch is compatible with earlier board revisions, since this > > > pin wasn't connected to phy. > > > > > > Signed-off-by: Stefan Mavrodiev > > > --- > > > arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 7 ++++++- > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > index 0b7403e..cb1b081 100644 > > > --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts > > > @@ -102,7 +102,7 @@ > > > &gmac { > > > pinctrl-names = "default"; > > > - pinctrl-0 = <&gmac_pins_mii_a>; > > > + pinctrl-0 = <&gmac_pins_mii_a>,<&gmac_txerr>; > > > phy = <&phy1>; > > > phy-mode = "mii"; > > > status = "okay"; > > > @@ -229,6 +229,11 @@ > > > }; > > > &pio { > > > + gmac_txerr: gmac_txerr at 0 { > > > + pins = "PA17"; > > > + function = "gmac"; > > > + }; > > > + > > The patch looks fine, I still have one question though. > > > > Can a PHY operate without this signal? My real question is, would it > > make sense to mux that pin for all the users, or is it an optional > > signal that each board designer can choose to use or not? > > > > Thanks! > > Maxime > > This phy (LAN8710) cannot work without this pin. Part of the problem > is in that we've replaced without paying attention to this signal. > > RTL8201 has no TXERR pin. The pin PA17 is used as reset signal and > therefore is pulled up with resistor. However on old revisions this > option (there is jumper pad between SOC and PHY). > > As I said, LAN8710 cannot work without this signal. In the datasheet > is written: > > ... > The controller drives TXER high when a transmit error is detected. > ... > > In the current variant of the dts, all data is threated as error. Sorry if my question was unclear, I meant to ask for all PHYs connected to an A20. I got that you were needing it for that particular one :) > So to answer you question. This is feature only on our board and > highly depends on the chosen PHY. I don't think this should be > muxed for all users. Ok, I guess it answers it. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: