From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753098AbdIERpL (ORCPT ); Tue, 5 Sep 2017 13:45:11 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:34536 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752292AbdIERpH (ORCPT ); Tue, 5 Sep 2017 13:45:07 -0400 X-Google-Smtp-Source: ADKCNb5I4FJTAc6Pr8CIX+Nqw8WBhKPpT+l3XWl7oX6+ixsgoCWndIGosZNd1YYo0XMPyuZI1QbKNQ== Date: Tue, 5 Sep 2017 10:45:29 -0700 From: Nicolin Chen To: Mark Brown Cc: =?utf-8?Q?=C5=81ukasz?= Majewski , Timur Tabi , Xiubo Li , Fabio Estevam , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] sound: soc: fsl: Do not set DAI sysclk when it is equal to system freq Message-ID: <20170905174528.GA23906@Asurada-Nvidia> References: <1504436701-20700-1-git-send-email-lukma@denx.de> <20170905050602.GA2774@Asurada-CZ80> <20170905075247.GA6112@Asurada> <20170905151550.5mhb535p22lsohlh@sirena.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170905151550.5mhb535p22lsohlh@sirena.org.uk> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 05, 2017 at 04:15:50PM +0100, Mark Brown wrote: > > Just to be clear: > > > What clock shall be set with: > > > struct snd_soc_dai_ops { > > int (*set_sysclk)(struct snd_soc_dai *dai, > > int clk_id, unsigned int freq, int dir); > > } > > > callback? > > > The SSI IP block or BCLK ? > > Not the BCLK, probably the IP clock but perhaps nothing. The bclk is > usually derived from the sample rate and width, the system clock is the > clock rate going into the device. It doesn't *have* to be configured > (particuarly if it's discoverable by the IP and managable via the clock > API). Hmm...to clarify the things, some background here: SSI has mainly two different clock inputs internally (not external pads such as bclk or lrclk): IP block clock (ipg_clk in Reference Manual) and sys clock (ccm_ssi_clk in Reference Manual). According to RM, ccm_ssi_clk: "module/system clock for bit clock generation". The ipg clock is merely used to access registers, and has nothing (directly) to do with external clock outputs. The driver shall not change the ipg clock as the system ipg clock (its parent clock) might be messed and even system time would get weird -- happened once when the fsl_spdif driver used to call clk_set_rate() on its ipg clock. Although the clock controller should have some kind of protection in my opinion, we just avoid IP clock rate change in all audio drivers as well. On the other hand, the sys clock (baudclk in the driver) should be configured whenever it's related to external clock outputs. When I implemented this set_sysclk() for fsl_ssi.c, I used it to set this sys clock (baudclk) by a machine driver, in order to set bit clock. Then someone patched the driver by moving all the code to set_bclk() to make machine drivers simpler. Now the set_sysclk() is remained to give machine drivers a chance to override clock configurations in the hw_params(). This could be used in TDM or some other special cases (It could also have a purpose for backwards compatibility). So here, we should set baudclk (BCLK generator).