From: keith.busch@intel.com (Keith Busch)
Subject: [PATCH 4/4] nvme-pci: implement the HMB entry number and size limitations
Date: Wed, 6 Sep 2017 16:11:32 -0400 [thread overview]
Message-ID: <20170906201131.GE17331@localhost.localdomain> (raw)
In-Reply-To: <20170906135532.21358-5-hch@lst.de>
On Wed, Sep 06, 2017@03:55:32PM +0200, Christoph Hellwig wrote:
> Adds support for the new Host Memory Buffer Minimum Descriptor Entry Size
> and Host Memory Maximum Descriptors Entries field that were added in
> TP 4002 HMB Enhancements. These allow the controller to advertise
> limits for the usual number of segments in the host memory buffer, as
> well as a minimum usable per-segment size.
>
> Signed-off-by: Christoph Hellwig <hch at lst.de>
Looks good.
Reviewed-by: Keith Busch <keith.busch at intel.com>
prev parent reply other threads:[~2017-09-06 20:11 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-06 13:55 nvme host memory buffer fixes and updates Christoph Hellwig
2017-09-06 13:55 ` [PATCH 1/4] nvme-pci: fix host memory buffer allocation fallback Christoph Hellwig
2017-09-06 13:55 ` Christoph Hellwig
2017-09-06 20:12 ` Keith Busch
2017-09-06 20:12 ` Keith Busch
2017-09-06 13:55 ` [PATCH 2/4] nvme-pci: use appropriate initial chunk size for HMB allocation Christoph Hellwig
2017-09-06 13:55 ` Christoph Hellwig
2017-09-06 20:13 ` Keith Busch
2017-09-06 20:13 ` Keith Busch
2017-09-06 13:55 ` [PATCH 3/4] nvme-pci: propagate (some) errors from host memory buffer setup Christoph Hellwig
2017-09-06 13:55 ` Christoph Hellwig
2017-09-06 14:19 ` Holger Hoffstätte
2017-09-06 14:19 ` Holger Hoffstätte
2017-09-06 20:27 ` Keith Busch
2017-09-06 20:27 ` Keith Busch
2017-09-06 21:49 ` Keith Busch
2017-09-06 21:49 ` Keith Busch
2017-09-06 13:55 ` [PATCH 4/4] nvme-pci: implement the HMB entry number and size limitations Christoph Hellwig
2017-09-06 20:11 ` Keith Busch [this message]
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