From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753139AbdIFUwt (ORCPT ); Wed, 6 Sep 2017 16:52:49 -0400 Received: from mail-pg0-f45.google.com ([74.125.83.45]:37528 "EHLO mail-pg0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753080AbdIFUwq (ORCPT ); Wed, 6 Sep 2017 16:52:46 -0400 X-Google-Smtp-Source: ADKCNb5T5v2TVgx8pFiBs2Zns7pULjRtkGxzCYgMJV5mD95JjcESvUTZG603XHzF+RUGCJfv28B4Nw== From: Douglas Anderson To: kishon@ti.com, heiko@sntech.de, zyw@rock-chips.com Cc: shawnn@chromium.org, dnschneid@chromium.org, Douglas Anderson , linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] phy: rockchip-typec: Do the calibration more correctly Date: Wed, 6 Sep 2017 13:52:01 -0700 Message-Id: <20170906205201.16207-4-dianders@chromium.org> X-Mailer: git-send-email 2.14.1.581.gf28d330327-goog In-Reply-To: <20170906205201.16207-1-dianders@chromium.org> References: <20170906205201.16207-1-dianders@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Calculate the calibration code as per the docs. The docs talk about reading and averaging the pullup and pulldown calibration codes. They also talk about adding in some adjustment codes. Let's do what the docs say. In practice this doesn't seem to matter a whole lot. On a device I tested the pullup and pulldown codes were nearly the same (0x23 and 0x24) and the adjustment codes were 0. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- drivers/phy/rockchip/phy-rockchip-typec.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index b8696a7c45fb..e59983a82dcc 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -194,6 +194,7 @@ /* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */ #define AUX_CH_LANE 8 + #define TX_ANA_CTRL_REG_1 (0x5020 << 2) #define TXDA_DP_AUX_EN BIT(15) @@ -560,24 +561,33 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy) u16 val; u16 tx_ana_ctrl_reg_1; u16 tx_ana_ctrl_reg_2; - s32 pu_calib_code; - - /* disable txda_cal_latch_en for rewrite the calibration values */ - tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1); - tx_ana_ctrl_reg_1 &= ~TXDA_CAL_LATCH_EN; - writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); + s32 pu_calib_code, pd_calib_code; + s32 pu_adj, pd_adj; + u16 calib; /* - * read a resistor calibration code from CMN_TXPUCAL_CTRL[5:0] and - * write it to TX_DIG_CTRL_REG_2[5:0]. + * Calculate calibration code as per docs: use an average of the + * pull down and pull up. Then add in adjustments. */ val = readl(tcphy->base + CMN_TXPUCAL_CTRL); pu_calib_code = CMN_CALIB_CODE_POS(val); + val = readl(tcphy->base + CMN_TXPDCAL_CTRL); + pd_calib_code = CMN_CALIB_CODE_POS(val); + val = readl(tcphy->base + CMN_TXPU_ADJ_CTRL); + pu_adj = CMN_CALIB_CODE(val); + val = readl(tcphy->base + CMN_TXPD_ADJ_CTRL); + pd_adj = CMN_CALIB_CODE(val); + calib = (pu_calib_code + pd_calib_code) / 2 + pu_adj + pd_adj; + + /* disable txda_cal_latch_en for rewrite the calibration values */ + tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1); + tx_ana_ctrl_reg_1 &= ~TXDA_CAL_LATCH_EN; + writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); /* write the calibration, then delay 10 ms as sample in docs */ val = readl(tcphy->base + TX_DIG_CTRL_REG_2); val &= ~(TX_RESCAL_CODE_MASK << TX_RESCAL_CODE_OFFSET); - val |= pu_calib_code << TX_RESCAL_CODE_OFFSET; + val |= calib << TX_RESCAL_CODE_OFFSET; writel(val, tcphy->base + TX_DIG_CTRL_REG_2); usleep_range(10000, 10050); -- 2.14.1.581.gf28d330327-goog From mboxrd@z Thu Jan 1 00:00:00 1970 From: dianders@chromium.org (Douglas Anderson) Date: Wed, 6 Sep 2017 13:52:01 -0700 Subject: [PATCH 3/3] phy: rockchip-typec: Do the calibration more correctly In-Reply-To: <20170906205201.16207-1-dianders@chromium.org> References: <20170906205201.16207-1-dianders@chromium.org> Message-ID: <20170906205201.16207-4-dianders@chromium.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Calculate the calibration code as per the docs. The docs talk about reading and averaging the pullup and pulldown calibration codes. They also talk about adding in some adjustment codes. Let's do what the docs say. In practice this doesn't seem to matter a whole lot. On a device I tested the pullup and pulldown codes were nearly the same (0x23 and 0x24) and the adjustment codes were 0. Reviewed-by: Chris Zhong Signed-off-by: Douglas Anderson --- drivers/phy/rockchip/phy-rockchip-typec.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index b8696a7c45fb..e59983a82dcc 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -194,6 +194,7 @@ /* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */ #define AUX_CH_LANE 8 + #define TX_ANA_CTRL_REG_1 (0x5020 << 2) #define TXDA_DP_AUX_EN BIT(15) @@ -560,24 +561,33 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy) u16 val; u16 tx_ana_ctrl_reg_1; u16 tx_ana_ctrl_reg_2; - s32 pu_calib_code; - - /* disable txda_cal_latch_en for rewrite the calibration values */ - tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1); - tx_ana_ctrl_reg_1 &= ~TXDA_CAL_LATCH_EN; - writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); + s32 pu_calib_code, pd_calib_code; + s32 pu_adj, pd_adj; + u16 calib; /* - * read a resistor calibration code from CMN_TXPUCAL_CTRL[5:0] and - * write it to TX_DIG_CTRL_REG_2[5:0]. + * Calculate calibration code as per docs: use an average of the + * pull down and pull up. Then add in adjustments. */ val = readl(tcphy->base + CMN_TXPUCAL_CTRL); pu_calib_code = CMN_CALIB_CODE_POS(val); + val = readl(tcphy->base + CMN_TXPDCAL_CTRL); + pd_calib_code = CMN_CALIB_CODE_POS(val); + val = readl(tcphy->base + CMN_TXPU_ADJ_CTRL); + pu_adj = CMN_CALIB_CODE(val); + val = readl(tcphy->base + CMN_TXPD_ADJ_CTRL); + pd_adj = CMN_CALIB_CODE(val); + calib = (pu_calib_code + pd_calib_code) / 2 + pu_adj + pd_adj; + + /* disable txda_cal_latch_en for rewrite the calibration values */ + tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1); + tx_ana_ctrl_reg_1 &= ~TXDA_CAL_LATCH_EN; + writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1); /* write the calibration, then delay 10 ms as sample in docs */ val = readl(tcphy->base + TX_DIG_CTRL_REG_2); val &= ~(TX_RESCAL_CODE_MASK << TX_RESCAL_CODE_OFFSET); - val |= pu_calib_code << TX_RESCAL_CODE_OFFSET; + val |= calib << TX_RESCAL_CODE_OFFSET; writel(val, tcphy->base + TX_DIG_CTRL_REG_2); usleep_range(10000, 10050); -- 2.14.1.581.gf28d330327-goog