From: Paul Burton <paul.burton@imgtec.com> To: Thomas Gleixner <tglx@linutronix.de>, Ralf Baechle <ralf@linux-mips.org> Cc: <dianders@chromium.org>, James Hogan <james.hogan@imgtec.com>, Brian Norris <briannorris@chromium.org>, Jason Cooper <jason@lakedaemon.net>, <jeffy.chen@rock-chips.com>, Marc Zyngier <marc.zyngier@arm.com>, <linux-kernel@vger.kernel.org>, <linux-mips@linux-mips.org>, <tfiga@chromium.org>, Paul Burton <paul.burton@imgtec.com> Subject: [RFC PATCH v1 6/9] MIPS: perf: percpu_devid interrupt support Date: Thu, 7 Sep 2017 16:25:39 -0700 [thread overview] Message-ID: <20170907232542.20589-7-paul.burton@imgtec.com> (raw) In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> The MIPS CPU performance counter overflow interrupt is really a percpu interrupt, but up until now we have not used the percpu interrupt APIs to configure & control it. In preparation for doing so, introduce support for percpu_devid interrupts in the MIPS perf implementation. We switch from using request_irq() to using either setup_irq() or setup_percpu_irq() with an explicit struct irqaction such that we can set the flags, handler & name for that struct irqaction once rather than needing to duplicate them in calls to request_irq() and request_percpu_irq(). The IRQF_NOAUTOEN flag is passed because percpu interrupts automatically get IRQ_NOAUTOEN set by irq_set_percpu_devid_flags(). We opt into accepting this behaviour & explicitly enable the interrupt in mipspmu_enable() right after configuring the local performance counters. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- arch/mips/kernel/perf_event_mipsxx.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index cae36ca400e9..af7bae79dc51 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -514,6 +514,11 @@ static void mipspmu_enable(struct pmu *pmu) write_unlock(&pmuint_rwlock); #endif resume_local_counters(); + + if (irq_is_percpu_devid(mipspmu.irq)) + enable_percpu_irq(mipspmu.irq, IRQ_TYPE_NONE); + else + enable_irq(mipspmu.irq); } /* @@ -538,24 +543,27 @@ static void mipspmu_disable(struct pmu *pmu) static atomic_t active_events = ATOMIC_INIT(0); static DEFINE_MUTEX(pmu_reserve_mutex); +static struct irqaction c0_perf_irqaction = { + .handler = mipsxx_pmu_handle_irq, + .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED | IRQF_NOAUTOEN, + .name = "mips_perf_pmu", + .percpu_dev_id = &mipspmu, +}; + static int mipspmu_get_irq(void) { - int err; + if (irq_is_percpu_devid(mipspmu.irq)) + return setup_percpu_irq(mipspmu.irq, &c0_perf_irqaction); - err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, - IRQF_PERCPU | IRQF_NOBALANCING | - IRQF_NO_THREAD | IRQF_NO_SUSPEND | - IRQF_SHARED, - "mips_perf_pmu", &mipspmu); - if (err) - pr_warn("Unable to request IRQ%d for MIPS performance counters!\n", - mipspmu.irq); - return err; + return setup_irq(mipspmu.irq, &c0_perf_irqaction); } static void mipspmu_free_irq(void) { - free_irq(mipspmu.irq, &mipspmu); + if (irq_is_percpu_devid(mipspmu.irq)) + remove_percpu_irq(mipspmu.irq, &c0_perf_irqaction); + else + remove_irq(mipspmu.irq, &c0_perf_irqaction); } /* -- 2.14.1
WARNING: multiple messages have this Message-ID (diff)
From: Paul Burton <paul.burton@imgtec.com> To: Thomas Gleixner <tglx@linutronix.de>, Ralf Baechle <ralf@linux-mips.org> Cc: dianders@chromium.org, James Hogan <james.hogan@imgtec.com>, Brian Norris <briannorris@chromium.org>, Jason Cooper <jason@lakedaemon.net>, jeffy.chen@rock-chips.com, Marc Zyngier <marc.zyngier@arm.com>, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, tfiga@chromium.org, Paul Burton <paul.burton@imgtec.com> Subject: [RFC PATCH v1 6/9] MIPS: perf: percpu_devid interrupt support Date: Thu, 7 Sep 2017 16:25:39 -0700 [thread overview] Message-ID: <20170907232542.20589-7-paul.burton@imgtec.com> (raw) Message-ID: <20170907232539.3Xkx3rVwSOmFOYjNpmdpS1Vx16ymZkkXw5fDv-DzN3Q@z> (raw) In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> The MIPS CPU performance counter overflow interrupt is really a percpu interrupt, but up until now we have not used the percpu interrupt APIs to configure & control it. In preparation for doing so, introduce support for percpu_devid interrupts in the MIPS perf implementation. We switch from using request_irq() to using either setup_irq() or setup_percpu_irq() with an explicit struct irqaction such that we can set the flags, handler & name for that struct irqaction once rather than needing to duplicate them in calls to request_irq() and request_percpu_irq(). The IRQF_NOAUTOEN flag is passed because percpu interrupts automatically get IRQ_NOAUTOEN set by irq_set_percpu_devid_flags(). We opt into accepting this behaviour & explicitly enable the interrupt in mipspmu_enable() right after configuring the local performance counters. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- arch/mips/kernel/perf_event_mipsxx.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index cae36ca400e9..af7bae79dc51 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -514,6 +514,11 @@ static void mipspmu_enable(struct pmu *pmu) write_unlock(&pmuint_rwlock); #endif resume_local_counters(); + + if (irq_is_percpu_devid(mipspmu.irq)) + enable_percpu_irq(mipspmu.irq, IRQ_TYPE_NONE); + else + enable_irq(mipspmu.irq); } /* @@ -538,24 +543,27 @@ static void mipspmu_disable(struct pmu *pmu) static atomic_t active_events = ATOMIC_INIT(0); static DEFINE_MUTEX(pmu_reserve_mutex); +static struct irqaction c0_perf_irqaction = { + .handler = mipsxx_pmu_handle_irq, + .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED | IRQF_NOAUTOEN, + .name = "mips_perf_pmu", + .percpu_dev_id = &mipspmu, +}; + static int mipspmu_get_irq(void) { - int err; + if (irq_is_percpu_devid(mipspmu.irq)) + return setup_percpu_irq(mipspmu.irq, &c0_perf_irqaction); - err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, - IRQF_PERCPU | IRQF_NOBALANCING | - IRQF_NO_THREAD | IRQF_NO_SUSPEND | - IRQF_SHARED, - "mips_perf_pmu", &mipspmu); - if (err) - pr_warn("Unable to request IRQ%d for MIPS performance counters!\n", - mipspmu.irq); - return err; + return setup_irq(mipspmu.irq, &c0_perf_irqaction); } static void mipspmu_free_irq(void) { - free_irq(mipspmu.irq, &mipspmu); + if (irq_is_percpu_devid(mipspmu.irq)) + remove_percpu_irq(mipspmu.irq, &c0_perf_irqaction); + else + remove_irq(mipspmu.irq, &c0_perf_irqaction); } /* -- 2.14.1
next prev parent reply other threads:[~2017-09-07 23:27 UTC|newest] Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-05-31 9:58 [patch 0/2] genirq: Handle NOAUTOEN interrupts correctly Thomas Gleixner 2017-05-31 9:58 ` [patch 1/2] genirq: Handle NOAUTOEN interrupt setup proper Thomas Gleixner 2017-05-31 13:54 ` Marc Zyngier 2017-05-31 15:18 ` Thomas Gleixner 2017-06-04 12:47 ` [tip:irq/core] " tip-bot for Thomas Gleixner 2017-05-31 9:58 ` [patch 2/2] genirq: Warn when IRQ_NOAUTOEN is used with shared interrupts Thomas Gleixner 2017-06-04 12:48 ` [tip:irq/core] " tip-bot for Thomas Gleixner 2017-09-06 6:00 ` [2/2] " Paul Burton 2017-09-06 8:16 ` Thomas Gleixner 2017-09-06 14:01 ` Paul Burton 2017-09-06 14:14 ` Thomas Gleixner 2017-09-07 1:18 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 0/9] Support shared percpu interrupts; clean up MIPS hacks Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 1/9] genirq: Allow shared interrupt users to opt into IRQ_NOAUTOEN Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 2/9] genirq: Support shared per_cpu_devid interrupts Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-25 21:06 ` Thomas Gleixner 2017-09-26 12:00 ` Thomas Gleixner 2017-10-19 14:08 ` Thomas Gleixner 2017-09-07 23:25 ` [RFC PATCH v1 3/9] genirq: Introduce irq_is_percpu_devid() Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 4/9] MIPS: Remove perf_irq interrupt sharing fallback Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 5/9] MIPS: Remove perf_irq Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` Paul Burton [this message] 2017-09-07 23:25 ` [RFC PATCH v1 6/9] MIPS: perf: percpu_devid interrupt support Paul Burton 2017-10-19 14:12 ` Thomas Gleixner 2017-09-07 23:25 ` [RFC PATCH v1 7/9] MIPS: cevt-r4k: " Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Paul Burton 2017-09-07 23:25 ` Paul Burton 2017-09-07 23:25 ` [RFC PATCH v1 9/9] irqchip: mips-gic: Remove gic_all_vpes_local_irq_controller Paul Burton 2017-09-07 23:25 ` Paul Burton
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