From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753317AbdIGX20 (ORCPT ); Thu, 7 Sep 2017 19:28:26 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:48237 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751969AbdIGX2Y (ORCPT ); Thu, 7 Sep 2017 19:28:24 -0400 From: Paul Burton To: Thomas Gleixner , Ralf Baechle CC: , James Hogan , Brian Norris , Jason Cooper , , Marc Zyngier , , , , Paul Burton Subject: [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Date: Thu, 7 Sep 2017 16:25:41 -0700 Message-ID: <20170907232542.20589-9-paul.burton@imgtec.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> References: <1682867.tATABVWsV9@np-p-burton> <20170907232542.20589-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.20.1.88] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MIPS timer, fast debug channel (FDC) & performance counter overflow interrupts are all really percpu interrupts. However up until now the users of these interrupt haven't used the percpu interrupt APIs to configure & control them; instead using the regular non-percpu APIs such as request_irq(), enable_irq() etc. This has required hacks elsewhere, and generally does not fit well with the fact that the interrupts are actually percpu. The users of these interrupts are now prepared for them to be used with the percpu interrupt APIs, so set them up as percpu_devid interrupts in order to allow these users to begin using the percpu interrupt APIs. Signed-off-by: Paul Burton Cc: James Hogan Cc: Jason Cooper Cc: Marc Zyngier Cc: Ralf Baechle Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 66f97fde13d8..8f7de01f6f35 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -166,7 +166,14 @@ static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, if (cpu_has_vint) set_vi_handler(hw, plat_irq_dispatch); - irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + if ((irq == cp0_compare_irq) || + (irq == cp0_fdc_irq) || + (irq == cp0_perfcount_irq)) { + irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq); + irq_set_percpu_devid(irq); + } else { + irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + } return 0; } -- 2.14.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:15715 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23994844AbdIGX23YFdrk (ORCPT ); Fri, 8 Sep 2017 01:28:29 +0200 From: Paul Burton Subject: [RFC PATCH v1 8/9] irqchip: mips-cpu: Set timer, FDC & perf interrupts percpu_devid Date: Thu, 7 Sep 2017 16:25:41 -0700 Message-ID: <20170907232542.20589-9-paul.burton@imgtec.com> In-Reply-To: <20170907232542.20589-1-paul.burton@imgtec.com> References: <1682867.tATABVWsV9@np-p-burton> <20170907232542.20589-1-paul.burton@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Thomas Gleixner , Ralf Baechle Cc: dianders@chromium.org, James Hogan , Brian Norris , Jason Cooper , jeffy.chen@rock-chips.com, Marc Zyngier , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, tfiga@chromium.org, Paul Burton Message-ID: <20170907232541.Bqd85clgV54l0H2wZdl-T3kDcl0WF3D6LEapfAk5z4M@z> The MIPS timer, fast debug channel (FDC) & performance counter overflow interrupts are all really percpu interrupts. However up until now the users of these interrupt haven't used the percpu interrupt APIs to configure & control them; instead using the regular non-percpu APIs such as request_irq(), enable_irq() etc. This has required hacks elsewhere, and generally does not fit well with the fact that the interrupts are actually percpu. The users of these interrupts are now prepared for them to be used with the percpu interrupt APIs, so set them up as percpu_devid interrupts in order to allow these users to begin using the percpu interrupt APIs. Signed-off-by: Paul Burton Cc: James Hogan Cc: Jason Cooper Cc: Marc Zyngier Cc: Ralf Baechle Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org --- drivers/irqchip/irq-mips-cpu.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c index 66f97fde13d8..8f7de01f6f35 100644 --- a/drivers/irqchip/irq-mips-cpu.c +++ b/drivers/irqchip/irq-mips-cpu.c @@ -166,7 +166,14 @@ static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, if (cpu_has_vint) set_vi_handler(hw, plat_irq_dispatch); - irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + if ((irq == cp0_compare_irq) || + (irq == cp0_fdc_irq) || + (irq == cp0_perfcount_irq)) { + irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq); + irq_set_percpu_devid(irq); + } else { + irq_set_chip_and_handler(irq, chip, handle_percpu_irq); + } return 0; } -- 2.14.1