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Date: Mon, 11 Sep 2017 06:21:34 +0100
From: "Maciej W. Rozycki" <macro@imgtec.com>
Subject: Re: [PATCH] MIPS: Add basic R5900 support
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To: Fredrik Noring <noring@nocrew.org>
Cc: linux-mips@linux-mips.org
Message-ID: <20170911052134.IsOtfHVN_y3zMRQpE-DBohN0iGUmfcD1hdHnFq3bwEg@z>

On Sat, 9 Sep 2017, Maciej W. Rozycki wrote:

>  Can you please try flipping the bits instead then, e.g.:
> 
> 	uint32_t fcsr0, fcsr1;
> 	asm volatile (" cfc1 %0,$31\n"
> 		      " lui  %1,0xfffc\n"

 Actually can you please substitute:

		      " li   %1,0xfffc0003\n"

here, so that we know how RM behaves?

 Again, it is odd to see it set to 1 (towards zero) by default and if it 
is hardwired, then `->fpu_csr31' and `->fpu_msk31' will have to be 
updated, AT_FPUCW exported and glibc adjusted.

  Maciej