From mboxrd@z Thu Jan 1 00:00:00 1970 From: Catalin Marinas Subject: Re: [PATCH v2 10/28] arm64/sve: Low-level CPU setup Date: Wed, 13 Sep 2017 06:32:06 -0700 Message-ID: <20170913133206.rwobtu7ft5nrsh4p@localhost> References: <1504198860-12951-1-git-send-email-Dave.Martin@arm.com> <1504198860-12951-11-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from foss.arm.com ([217.140.101.70]:51620 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751019AbdIMNcJ (ORCPT ); Wed, 13 Sep 2017 09:32:09 -0400 Content-Disposition: inline In-Reply-To: <1504198860-12951-11-git-send-email-Dave.Martin@arm.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, libc-alpha@sourceware.org, Ard Biesheuvel , Szabolcs Nagy , Will Deacon , Richard Sandiford , Alex =?iso-8859-1?Q?Benn=E9e?= , kvmarm@lists.cs.columbia.edu On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote: > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 877d42f..dd22ef2 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include > > #ifdef CONFIG_ARM64_64K_PAGES > #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K > @@ -186,8 +187,17 @@ ENTRY(__cpu_setup) > tlbi vmalle1 // Invalidate local TLB > dsb nsh > > - mov x0, #3 << 20 > - msr cpacr_el1, x0 // Enable FP/ASIMD > + mov x0, #3 << 20 // FEN > + > + /* SVE */ > + mrs x5, id_aa64pfr0_el1 > + ubfx x5, x5, #ID_AA64PFR0_SVE_SHIFT, #4 > + cbz x5, 1f > + > + bic x0, x0, #CPACR_EL1_ZEN > + orr x0, x0, #CPACR_EL1_ZEN_EL1EN // SVE: trap for EL0, not EL1 > +1: msr cpacr_el1, x0 // Enable FP/ASIMD For EL1, I wonder whether we could move this later to cpufeature.c. IIRC I tried to do the same with FPSIMD but hit an issue with EFI run-time services (I may be wrong though). -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 From: catalin.marinas@arm.com (Catalin Marinas) Date: Wed, 13 Sep 2017 06:32:06 -0700 Subject: [PATCH v2 10/28] arm64/sve: Low-level CPU setup In-Reply-To: <1504198860-12951-11-git-send-email-Dave.Martin@arm.com> References: <1504198860-12951-1-git-send-email-Dave.Martin@arm.com> <1504198860-12951-11-git-send-email-Dave.Martin@arm.com> Message-ID: <20170913133206.rwobtu7ft5nrsh4p@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Aug 31, 2017 at 06:00:42PM +0100, Dave P Martin wrote: > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 877d42f..dd22ef2 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -27,6 +27,7 @@ > #include > #include > #include > +#include > > #ifdef CONFIG_ARM64_64K_PAGES > #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K > @@ -186,8 +187,17 @@ ENTRY(__cpu_setup) > tlbi vmalle1 // Invalidate local TLB > dsb nsh > > - mov x0, #3 << 20 > - msr cpacr_el1, x0 // Enable FP/ASIMD > + mov x0, #3 << 20 // FEN > + > + /* SVE */ > + mrs x5, id_aa64pfr0_el1 > + ubfx x5, x5, #ID_AA64PFR0_SVE_SHIFT, #4 > + cbz x5, 1f > + > + bic x0, x0, #CPACR_EL1_ZEN > + orr x0, x0, #CPACR_EL1_ZEN_EL1EN // SVE: trap for EL0, not EL1 > +1: msr cpacr_el1, x0 // Enable FP/ASIMD For EL1, I wonder whether we could move this later to cpufeature.c. IIRC I tried to do the same with FPSIMD but hit an issue with EFI run-time services (I may be wrong though). -- Catalin