From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: vathsala nagaraju <vathsala.nagaraju@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>,
intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: Re: [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2
Date: Wed, 20 Sep 2017 17:44:03 +0300 [thread overview]
Message-ID: <20170920144403.GA4914@intel.com> (raw)
In-Reply-To: <1505917955-6623-2-git-send-email-vathsala.nagaraju@intel.com>
On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> CC: Puthikorn Voravootivat <puthik@chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> */
> uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> uint32_t val;
> + uint8_t sink_latency;
>
> val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
> * mesh at all with our frontbuffer tracking. And the hw alone isn't
> * good enough. */
> val |= EDP_PSR2_ENABLE |
> - EDP_SU_TRACK_ENABLE |
> - EDP_FRAMES_BEFORE_SU_ENTRY;
> + EDP_SU_TRACK_ENABLE;
> +
> + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> + &sink_latency)) {
== 1
> + sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> + val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
> + } else {
> + val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> + }
>
> if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
> val |= EDP_PSR2_TP2_TIME_2500;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2017-09-20 14:44 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-20 14:32 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-20 14:32 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-20 14:44 ` Ville Syrjälä [this message]
2017-09-20 15:19 ` Vivi, Rodrigo
2017-09-22 15:58 ` vathsala nagaraju
2017-09-22 23:54 ` Rodrigo Vivi
2017-09-28 16:54 ` Rodrigo Vivi
2017-09-29 11:36 ` Jani Nikula
2017-09-20 14:58 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: Add defines for latency in sink Patchwork
2017-09-20 15:51 ` ✗ Fi.CI.IGT: warning " Patchwork
2017-09-20 22:07 ` [PATCH 1/2] " Rodrigo Vivi
2017-09-21 14:42 ` Rodrigo Vivi
2017-09-26 5:11 ` Daniel Vetter
2017-09-26 17:37 ` Puthikorn Voravootivat
2017-09-26 20:37 ` Puthikorn Voravootivat
2017-09-26 20:53 ` [Intel-gfx] " Rodrigo Vivi
2017-09-23 0:34 vathsala nagaraju
2017-09-23 0:34 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
2017-09-25 8:30 ` [Intel-gfx] " Jani Nikula
2017-09-25 9:10 ` vathsala nagaraju
2017-09-25 16:57 ` Rodrigo Vivi
2017-09-26 9:59 [PATCH 1/2] drm/dp: Add defines for latency in sink vathsala nagaraju
2017-09-26 9:59 ` [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2 vathsala nagaraju
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