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From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info
Date: Fri, 22 Sep 2017 18:32:35 +0100	[thread overview]
Message-ID: <20170922173252.10137-5-matthew.auld@intel.com> (raw)
In-Reply-To: <20170922173252.10137-1-matthew.auld@intel.com>

In preparation for huge gtt pages expose page_sizes as part of the
device info, to indicate the page sizes supported by the HW.  Currently
only 4K is supported.

v2: s/page_size_mask/page_sizes/

Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h                  |  1 +
 drivers/gpu/drm/i915/i915_gem_gtt.h              |  7 ++++++-
 drivers/gpu/drm/i915/i915_pci.c                  | 20 ++++++++++++++++++++
 drivers/gpu/drm/i915/selftests/mock_gem_device.c |  3 +++
 4 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b59714f0c1bf..869e46306c49 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -862,6 +862,7 @@ struct intel_device_info {
 	u8 gt; /* GT number, 0 if undefined */
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
+	unsigned int page_sizes; /* page sizes supported by the HW */
 #define DEFINE_FLAG(name) u8 name:1
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index f62fb903dc24..88e9724d5fc7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -42,7 +42,12 @@
 #include "i915_gem_request.h"
 #include "i915_selftest.h"
 
-#define I915_GTT_PAGE_SIZE 4096UL
+#define I915_GTT_PAGE_SIZE_4K BIT(12)
+#define I915_GTT_PAGE_SIZE_64K BIT(16)
+#define I915_GTT_PAGE_SIZE_2M BIT(21)
+
+#define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
+
 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
 
 #define I915_FENCE_REG_NONE -1
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da60866b6628..84cdab3c5f09 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -56,6 +56,10 @@
 	.color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
 
 /* Keep in gen based order, and chronological order within a gen */
+
+#define GEN_DEFAULT_PAGE_SIZES \
+	.page_sizes = I915_GTT_PAGE_SIZE_4K
+
 #define GEN2_FEATURES \
 	.gen = 2, .num_pipes = 1, \
 	.has_overlay = 1, .overlay_needs_physical = 1, \
@@ -65,6 +69,7 @@
 	.ring_mask = RENDER_RING, \
 	.has_snoop = true, \
 	GEN_DEFAULT_PIPEOFFSETS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i830_info __initconst = {
@@ -98,6 +103,7 @@ static const struct intel_device_info intel_i865g_info __initconst = {
 	.ring_mask = RENDER_RING, \
 	.has_snoop = true, \
 	GEN_DEFAULT_PIPEOFFSETS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i915g_info __initconst = {
@@ -161,6 +167,7 @@ static const struct intel_device_info intel_pineview_info __initconst = {
 	.ring_mask = RENDER_RING, \
 	.has_snoop = true, \
 	GEN_DEFAULT_PIPEOFFSETS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
 static const struct intel_device_info intel_i965g_info __initconst = {
@@ -203,6 +210,7 @@ static const struct intel_device_info intel_gm45_info __initconst = {
 	.ring_mask = RENDER_RING | BSD_RING, \
 	.has_snoop = true, \
 	GEN_DEFAULT_PIPEOFFSETS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
 static const struct intel_device_info intel_ironlake_d_info __initconst = {
@@ -226,6 +234,7 @@ static const struct intel_device_info intel_ironlake_m_info __initconst = {
 	.has_rc6p = 1, \
 	.has_aliasing_ppgtt = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	CURSOR_OFFSETS
 
 #define SNB_D_PLATFORM \
@@ -269,6 +278,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info __initconst =
 	.has_aliasing_ppgtt = 1, \
 	.has_full_ppgtt = 1, \
 	GEN_DEFAULT_PIPEOFFSETS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	IVB_CURSOR_OFFSETS
 
 #define IVB_D_PLATFORM \
@@ -325,6 +335,7 @@ static const struct intel_device_info intel_valleyview_info __initconst = {
 	.has_snoop = true,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	GEN_DEFAULT_PAGE_SIZES,
 	GEN_DEFAULT_PIPEOFFSETS,
 	CURSOR_OFFSETS
 };
@@ -363,6 +374,7 @@ static const struct intel_device_info intel_haswell_gt3_info __initconst = {
 #define BDW_FEATURES \
 	HSW_FEATURES, \
 	BDW_COLORS, \
+	GEN_DEFAULT_PAGE_SIZES, \
 	.has_logical_ring_contexts = 1, \
 	.has_full_48bit_ppgtt = 1, \
 	.has_64bit_reloc = 1, \
@@ -415,13 +427,18 @@ static const struct intel_device_info intel_cherryview_info __initconst = {
 	.has_reset_engine = 1,
 	.has_snoop = true,
 	.display_mmio_offset = VLV_DISPLAY_BASE,
+	GEN_DEFAULT_PAGE_SIZES,
 	GEN_CHV_PIPEOFFSETS,
 	CURSOR_OFFSETS,
 	CHV_COLORS,
 };
 
+#define GEN9_DEFAULT_PAGE_SIZES \
+	.page_sizes = I915_GTT_PAGE_SIZE_4K
+
 #define SKL_PLATFORM \
 	BDW_FEATURES, \
+	GEN9_DEFAULT_PAGE_SIZES, \
 	.gen = 9, \
 	.platform = INTEL_SKYLAKE, \
 	.has_csr = 1, \
@@ -477,6 +494,7 @@ static const struct intel_device_info intel_skylake_gt4_info __initconst = {
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_ipc = 1, \
+	GEN9_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS, \
 	BDW_COLORS
@@ -496,6 +514,7 @@ static const struct intel_device_info intel_geminilake_info __initconst = {
 
 #define KBL_PLATFORM \
 	BDW_FEATURES, \
+	GEN9_DEFAULT_PAGE_SIZES, \
 	.gen = 9, \
 	.platform = INTEL_KABYLAKE, \
 	.has_csr = 1, \
@@ -546,6 +565,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info __initconst = {
 
 static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
 	BDW_FEATURES,
+	GEN9_DEFAULT_PAGE_SIZES, \
 	.is_alpha_support = 1,
 	.platform = INTEL_CANNONLAKE,
 	.gen = 10,
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index ed3407b078e7..1785c63ad797 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -174,6 +174,9 @@ struct drm_i915_private *mock_gem_device(void)
 
 	mkwrite_device_info(i915)->gen = -1;
 
+	mkwrite_device_info(i915)->page_sizes =
+		I915_GTT_PAGE_SIZE_4K;
+
 	spin_lock_init(&i915->mm.object_stat_lock);
 	mock_uncore_init(i915);
 
-- 
2.13.5

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  parent reply	other threads:[~2017-09-22 17:33 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 17:32 [PATCH 00/21] huge gtt pages Matthew Auld
2017-09-22 17:32 ` [PATCH 01/21] mm/shmem: introduce shmem_file_setup_with_mnt Matthew Auld
2017-09-22 17:32 ` [PATCH 02/21] drm/i915: introduce simple gemfs Matthew Auld
2017-09-22 17:32   ` Matthew Auld
2017-09-23  8:36   ` Chris Wilson
2017-09-25 18:06   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 03/21] drm/i915/gemfs: enable THP Matthew Auld
2017-09-22 17:32 ` Matthew Auld [this message]
2017-09-23  8:39   ` [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info Chris Wilson
2017-09-22 17:32 ` [PATCH 05/21] drm/i915: push set_pages down to the callers Matthew Auld
2017-09-23  8:41   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 06/21] drm/i915: introduce page_size members Matthew Auld
2017-09-23  8:42   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 07/21] drm/i915: introduce vm set_pages/clear_pages Matthew Auld
2017-09-23  8:43   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 08/21] drm/i915: align the vma start to the largest gtt page size Matthew Auld
2017-09-23  8:46   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 09/21] drm/i915: align 64K objects to 2M Matthew Auld
2017-09-23  8:46   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 10/21] drm/i915: enable IPS bit for 64K pages Matthew Auld
2017-09-26 12:20   ` Mika Kuoppala
2017-09-22 17:32 ` [PATCH 11/21] drm/i915: disable GTT cache for 2M pages Matthew Auld
2017-09-26 11:41   ` Mika Kuoppala
2017-09-22 17:32 ` [PATCH 12/21] drm/i915: support 2M pages for the 48b PPGTT Matthew Auld
2017-09-23  8:48   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 13/21] drm/i915: add support for 64K scratch page Matthew Auld
2017-09-23  8:52   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 14/21] drm/i915: support 64K pages for the 48b PPGTT Matthew Auld
2017-09-23  8:53   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 15/21] drm/i915: accurate page size tracking for the ppgtt Matthew Auld
2017-09-23  8:54   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 16/21] drm/i915/debugfs: include some gtt page size metrics Matthew Auld
2017-09-23  8:56   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 17/21] drm/i915/selftests: huge page tests Matthew Auld
2017-09-23  8:30   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 18/21] drm/i915/selftests: mix huge pages Matthew Auld
2017-09-23  8:57   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 19/21] drm/i915: disable platform support for vGPU huge gtt pages Matthew Auld
2017-09-22 18:12   ` Zhenyu Wang
2017-09-23  8:57   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 20/21] drm/i915: enable platform support for 64K pages Matthew Auld
2017-09-23  8:58   ` Chris Wilson
2017-09-22 17:32 ` [PATCH 21/21] drm/i915: enable platform support for 2M pages Matthew Auld
2017-09-23  8:58   ` Chris Wilson
2017-09-22 18:20 ` ✓ Fi.CI.BAT: success for huge gtt pages (rev8) Patchwork
2017-09-22 22:33 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-09-29 16:10 [PATCH 00/21] huge gtt pages Matthew Auld
2017-09-29 16:10 ` [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info Matthew Auld
2017-10-05 15:18 [PATCH 00/21] huge gtt pages Matthew Auld
2017-10-05 15:18 ` [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info Matthew Auld
2017-10-06 14:50 [PATCH 00/21] huge gtt pages Matthew Auld
2017-10-06 14:50 ` [PATCH 04/21] drm/i915: introduce page_sizes field to dev_info Matthew Auld

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