From mboxrd@z Thu Jan  1 00:00:00 1970
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Subject: Re: [PATCH 19/21] drm/i915: disable platform support
 for vGPU huge gtt pages
Date: Sat, 23 Sep 2017 02:12:20 +0800
Message-ID: <20170922181220.gzlj2enevcswnkzk@zhen-hp.sh.intel.com>
References: <20170922173252.10137-1-matthew.auld@intel.com>
 <20170922173252.10137-20-matthew.auld@intel.com>
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On 2017.09.22 18:32:50 +0100, Matthew Auld wrote:
> Currently gvt gtt handling doesn't support huge page entries, so disable
> for now.
>=20
> v2: remove useless 48b PPGTT check
>=20
> Suggested-by: Zhenyu Wang <zhenyuw@linux.intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>=20
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_=
gem.c
> index 750c04002304..f98d8a08167b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_pri=
v)
> =20
>  	mutex_lock(&dev_priv->drm.struct_mutex);
> =20
> +	/* We need to fallback to 4K pages since gvt gtt handling doesn't
> +	 * support huge page entries - we will need to check either hypervisor
> +	 * mm can support huge guest page or just do emulation in gvt.
> +	 */
> +	if (intel_vgpu_active(dev_priv))
> +		mkwrite_device_info(dev_priv)->page_sizes =3D
> +			I915_GTT_PAGE_SIZE_4K;
> +
>  	dev_priv->mm.unordered_timeline =3D dma_fence_context_alloc(1);
> =20
>  	if (!i915_modparams.enable_execlists) {
> --=20
> 2.13.5
>=20

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>

thanks
--=20
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

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