[PATCH igt 1/7] igt/gem_sync: Sync before starting the clock

[PATCH igt 1/7] igt/gem_sync: Sync before starting the clock

[Chris Wilson]

Hide the initial setup cost of a new batch by performing it before we
start the clock for measuring the execute-wait latency.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 tests/gem_sync.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/gem_sync.c b/tests/gem_sync.c
index 8ed9760d..c9e2f014 100644
--- a/tests/gem_sync.c
+++ b/tests/gem_sync.c
@@ -138,6 +138,7 @@ sync_ring(int fd, unsigned ring, int num_children, int timeout)
 		execbuf.buffer_count = 1;
 		execbuf.flags = engines[child % num_engines];
 		gem_execbuf(fd, &execbuf);
+		gem_sync(fd, object.handle);
 
 		start = gettime();
 		cycles = 0;
@@ -553,6 +554,7 @@ sync_all(int fd, int num_children, int timeout)
 		execbuf.buffers_ptr = to_user_pointer(&object);
 		execbuf.buffer_count = 1;
 		gem_execbuf(fd, &execbuf);
+		gem_sync(fd, object.handle);
 
 		start = gettime();
 		cycles = 0;
@@ -773,6 +775,7 @@ preempt(int fd, unsigned ring, int num_children, int timeout)
 		execbuf.flags = engines[child % num_engines];
 		execbuf.rsvd1 = ctx[1];
 		gem_execbuf(fd, &execbuf);
+		gem_sync(fd, object.handle);
 
 		start = gettime();
 		cycles = 0;
-- 
2.14.2

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[PATCH igt 2/7] igt/gem_workarounds: Read the workaround registers from the active context

[Chris Wilson]

The workarounds are only valid whilst the GPU is active. To be sure we
are reading the registers in the right state, issue the reads from the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_workarounds.c | 137 +++++++++++++++++++++++++++---------------------
 1 file changed, 77 insertions(+), 60 deletions(-)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 5e30a7b8..074ffc0c 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -61,20 +61,6 @@ static struct write_only_list {
 static struct intel_wa_reg *wa_regs;
 static int num_wa_regs;
 
-static void wait_gpu(void)
-{
-	int fd = drm_open_driver(DRIVER_INTEL);
-	gem_quiescent_gpu(fd);
-	close(fd);
-}
-
-static void test_hang_gpu(void)
-{
-	int fd = drm_open_driver(DRIVER_INTEL);
-	igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
-	close(fd);
-}
-
 static void test_suspend_resume(void)
 {
 	igt_info("Suspending the device ...\n");
@@ -96,49 +82,97 @@ static bool write_only(const uint32_t addr)
 	return false;
 }
 
-static int workaround_fail_count(void)
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+
+static int workaround_fail_count(int fd)
 {
-	int i, fail_count = 0;
+	const int gen = intel_gen(intel_get_drm_devid(fd));
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_relocation_entry *reloc;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t result_sz, batch_sz;
+	uint32_t *base, *out;
+	int fail_count = 0;
+
+	reloc = calloc(num_wa_regs, sizeof(*reloc));
+	igt_assert(reloc);
+
+	result_sz = 4 * num_wa_regs;
+	result_sz = (result_sz + 4095) & -4096;
+
+	batch_sz = 16 * num_wa_regs;
+	batch_sz = (batch_sz + 4 + 4095) & -4096;
+
+	memset(obj, 0, sizeof(obj));
+	obj[0].handle = gem_create(fd, result_sz);
+	gem_set_caching(fd, obj[0].handle, 1);
+	obj[1].handle = gem_create(fd, batch_sz);
+	obj[1].relocs_ptr = to_user_pointer(reloc);
+	obj[1].relocation_count = num_wa_regs;
+
+	out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
+	for (int i = 0; i < num_wa_regs; i++) {
+		*out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
+		*out++ = wa_regs[i].addr;
+		reloc[i].target_handle = obj[0].handle;
+		reloc[i].offset = (out - base) * sizeof(*out);
+		reloc[i].delta = i * sizeof(uint32_t);
+		reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+		reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+		*out++ = reloc[i].delta;
+		if (gen >= 8)
+			*out++ = 0;
+	}
+	*out++ = MI_BATCH_BUFFER_END;
+	munmap(base, batch_sz);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = 2;
+	gem_execbuf(fd, &execbuf);
 
-	/* There is a small delay after coming ot of rc6 to the correct
-	   render context values will get loaded by hardware (bdw,chv).
-	   This here ensures that we have the correct context loaded before
-	   we start to read values */
-	wait_gpu();
+	gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
 
 	igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
 
-	for (i = 0; i < num_wa_regs; ++i) {
-		const uint32_t val = intel_register_read(wa_regs[i].addr);
-		const bool ok = (wa_regs[i].value & wa_regs[i].mask) ==
-			(val & wa_regs[i].mask);
+	out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
+	for (int i = 0; i < num_wa_regs; i++) {
+		const bool ok =
+			(wa_regs[i].value & wa_regs[i].mask) ==
+			(out[i] & wa_regs[i].mask);
+		char buf[80];
 
-		igt_debug("0x%05X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
-			  wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
-			  val, ok ? "OK" : "FAIL");
+		snprintf(buf, sizeof(buf),
+			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
+			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
+			 out[i]);
 
 		if (write_only(wa_regs[i].addr))
 			continue;
 
 		if (!ok) {
-			igt_warn("0x%05X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
-				 wa_regs[i].addr, wa_regs[i].value,
-				 wa_regs[i].mask,
-				 val, ok ? "OK" : "FAIL");
+			igt_warn("%s\tFAIL\n", buf);
 			fail_count++;
+		} else {
+			igt_debug("%s\tOK\n", buf);
 		}
 	}
+	munmap(out, result_sz);
+
+	gem_close(fd, obj[1].handle);
+	gem_close(fd, obj[0].handle);
+	free(reloc);
 
 	return fail_count;
 }
 
-static void check_workarounds(enum operation op)
+static void check_workarounds(int fd, enum operation op)
 {
-	igt_assert_eq(workaround_fail_count(), 0);
+	igt_assert_eq(workaround_fail_count(fd), 0);
 
 	switch (op) {
 	case GPU_RESET:
-		test_hang_gpu();
+		igt_force_gpu_reset(fd);
 		break;
 
 	case SUSPEND_RESUME:
@@ -152,40 +186,30 @@ static void check_workarounds(enum operation op)
 		igt_assert(0);
 	}
 
-	igt_assert_eq(workaround_fail_count(), 0);
+	igt_assert_eq(workaround_fail_count(fd), 0);
 }
 
 igt_main
 {
+	int device = -1;
+
 	igt_fixture {
-		int device = drm_open_driver_master(DRIVER_INTEL);
-		struct pci_device *pci_dev;
 		FILE *file;
 		char *line = NULL;
 		size_t line_size;
 		int i, fd;
 
+		device = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(device);
 
 		gen = intel_gen(intel_get_drm_devid(device));
 
-		pci_dev = intel_get_pci_device();
-		igt_require(pci_dev);
-
-		intel_register_access_init(pci_dev, 0, device);
-
 		fd = igt_debugfs_open(device, "i915_wa_registers", O_RDONLY);
 		file = fdopen(fd, "r");
 		igt_assert(getline(&line, &line_size, file) > 0);
 		igt_debug("i915_wa_registers: %s", line);
 		sscanf(line, "Workarounds applied: %d", &num_wa_regs);
-
-		/* For newer gens, the lri wa list has always something.
-		 * If it doesn't, go and add one. */
-		if (gen >= 8)
-			igt_assert_lt(0, num_wa_regs);
-		else
-			igt_assert_lte(0, num_wa_regs);
+		igt_require(num_wa_regs > 0);
 
 		wa_regs = malloc(num_wa_regs * sizeof(*wa_regs));
 		igt_assert(wa_regs);
@@ -205,21 +229,14 @@ igt_main
 		free(line);
 		fclose(file);
 		close(fd);
-		close(device);
 	}
 
 	igt_subtest("basic-read")
-		check_workarounds(SIMPLE_READ);
+		check_workarounds(device, SIMPLE_READ);
 
 	igt_subtest("reset")
-		check_workarounds(GPU_RESET);
+		check_workarounds(device, GPU_RESET);
 
 	igt_subtest("suspend-resume")
-		check_workarounds(SUSPEND_RESUME);
-
-	igt_fixture {
-		free(wa_regs);
-		intel_register_access_fini();
-	}
-
+		check_workarounds(device, SUSPEND_RESUME);
 }
-- 
2.14.2

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[PATCH igt 3/7] igt/gem_workarounds: Also exercise fresh contexts not the persistent default

[Chris Wilson]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_workarounds.c | 28 +++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 074ffc0c..62c10877 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -166,8 +166,14 @@ static int workaround_fail_count(int fd)
 	return fail_count;
 }
 
-static void check_workarounds(int fd, enum operation op)
+#define CONTEXT 0x1
+static void check_workarounds(int fd, enum operation op, unsigned int flags)
 {
+	uint32_t ctx = 0;
+
+	if (flags & CONTEXT)
+		ctx = gem_context_create(fd);
+
 	igt_assert_eq(workaround_fail_count(fd), 0);
 
 	switch (op) {
@@ -180,13 +186,16 @@ static void check_workarounds(int fd, enum operation op)
 		break;
 
 	case SIMPLE_READ:
-		return;
+		break;
 
 	default:
 		igt_assert(0);
 	}
 
 	igt_assert_eq(workaround_fail_count(fd), 0);
+
+	if (ctx)
+		gem_context_destroy(fd, ctx);
 }
 
 igt_main
@@ -232,11 +241,20 @@ igt_main
 	}
 
 	igt_subtest("basic-read")
-		check_workarounds(device, SIMPLE_READ);
+		check_workarounds(device, SIMPLE_READ, 0);
+
+	igt_subtest("basic-read-context")
+		check_workarounds(device, SIMPLE_READ, CONTEXT);
 
 	igt_subtest("reset")
-		check_workarounds(device, GPU_RESET);
+		check_workarounds(device, GPU_RESET, 0);
+
+	igt_subtest("reset-context")
+		check_workarounds(device, GPU_RESET, CONTEXT);
 
 	igt_subtest("suspend-resume")
-		check_workarounds(device, SUSPEND_RESUME);
+		check_workarounds(device, SUSPEND_RESUME, 0);
+
+	igt_subtest("suspend-resume-context")
+		check_workarounds(device, SUSPEND_RESUME, CONTEXT);
 }
-- 
2.14.2

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[PATCH igt 4/7] igt/gem_workarounds: Also test new fd (implicit default context)

[Chris Wilson]

To complete the picture also test a new fd with its implicit default
context. Now we have a test for a longstanding fd, new client, new
context.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_workarounds.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 62c10877..2a328959 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -166,11 +166,25 @@ static int workaround_fail_count(int fd)
 	return fail_count;
 }
 
+static int reopen(int fd)
+{
+	char path[256];
+
+	snprintf(path, sizeof(path), "/proc/self/fd/%d", fd);
+	fd = open(path, O_RDWR);
+	igt_assert_lte(0, fd);
+
+	return fd;
+}
+
 #define CONTEXT 0x1
+#define FDS 0x2
 static void check_workarounds(int fd, enum operation op, unsigned int flags)
 {
 	uint32_t ctx = 0;
 
+	if (flags & FDS)
+		fd = reopen(fd);
 	if (flags & CONTEXT)
 		ctx = gem_context_create(fd);
 
@@ -196,6 +210,8 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 
 	if (ctx)
 		gem_context_destroy(fd, ctx);
+	if (flags & FDS)
+		close(fd);
 }
 
 igt_main
@@ -246,15 +262,24 @@ igt_main
 	igt_subtest("basic-read-context")
 		check_workarounds(device, SIMPLE_READ, CONTEXT);
 
+	igt_subtest("basic-read-fd")
+		check_workarounds(device, SIMPLE_READ, FDS);
+
 	igt_subtest("reset")
 		check_workarounds(device, GPU_RESET, 0);
 
 	igt_subtest("reset-context")
 		check_workarounds(device, GPU_RESET, CONTEXT);
 
+	igt_subtest("reset-fd")
+		check_workarounds(device, GPU_RESET, FDS);
+
 	igt_subtest("suspend-resume")
 		check_workarounds(device, SUSPEND_RESUME, 0);
 
 	igt_subtest("suspend-resume-context")
 		check_workarounds(device, SUSPEND_RESUME, CONTEXT);
+
+	igt_subtest("suspend-resume-fd")
+		check_workarounds(device, SUSPEND_RESUME, FDS);
 }
-- 
2.14.2

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[PATCH igt 5/7] igt/gem_workarounds: Reduce manual list to combinatorial loops

[Chris Wilson]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_workarounds.c | 50 ++++++++++++++++++++++++-------------------------
 1 file changed, 24 insertions(+), 26 deletions(-)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 2a328959..55cab561 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -217,6 +217,24 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 igt_main
 {
 	int device = -1;
+	const struct {
+		const char *name;
+		enum operation op;
+	} ops[] =   {
+		{ "basic-read", SIMPLE_READ },
+		{ "reset", GPU_RESET },
+		{ "suspend-resume", SUSPEND_RESUME },
+		{ }
+	}, *op;
+	const struct {
+		const char *name;
+		unsigned int flags;
+	} modes[] =   {
+		{ "", 0 },
+		{ "-context", CONTEXT },
+		{ "-fd", FDS },
+		{ }
+	}, *m;
 
 	igt_fixture {
 		FILE *file;
@@ -256,30 +274,10 @@ igt_main
 		close(fd);
 	}
 
-	igt_subtest("basic-read")
-		check_workarounds(device, SIMPLE_READ, 0);
-
-	igt_subtest("basic-read-context")
-		check_workarounds(device, SIMPLE_READ, CONTEXT);
-
-	igt_subtest("basic-read-fd")
-		check_workarounds(device, SIMPLE_READ, FDS);
-
-	igt_subtest("reset")
-		check_workarounds(device, GPU_RESET, 0);
-
-	igt_subtest("reset-context")
-		check_workarounds(device, GPU_RESET, CONTEXT);
-
-	igt_subtest("reset-fd")
-		check_workarounds(device, GPU_RESET, FDS);
-
-	igt_subtest("suspend-resume")
-		check_workarounds(device, SUSPEND_RESUME, 0);
-
-	igt_subtest("suspend-resume-context")
-		check_workarounds(device, SUSPEND_RESUME, CONTEXT);
-
-	igt_subtest("suspend-resume-fd")
-		check_workarounds(device, SUSPEND_RESUME, FDS);
+	for (op = ops; op->name; op++) {
+		for (m = modes; m->name; m++) {
+			igt_subtest_f("%s%s", op->name, m->name)
+				check_workarounds(device, op->op, m->flags);
+		}
+	}
 }
-- 
2.14.2

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[PATCH igt 6/7] igt/gem_workarounds: Add hibernation coverage

[Chris Wilson]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_workarounds.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 55cab561..86d70369 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -34,6 +34,7 @@ static int gen;
 enum operation {
 	GPU_RESET,
 	SUSPEND_RESUME,
+	HIBERNATE_RESUME,
 	SIMPLE_READ,
 };
 
@@ -61,12 +62,6 @@ static struct write_only_list {
 static struct intel_wa_reg *wa_regs;
 static int num_wa_regs;
 
-static void test_suspend_resume(void)
-{
-	igt_info("Suspending the device ...\n");
-	igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_NONE);
-}
-
 static bool write_only(const uint32_t addr)
 {
 	int i;
@@ -196,7 +191,13 @@ static void check_workarounds(int fd, enum operation op, unsigned int flags)
 		break;
 
 	case SUSPEND_RESUME:
-		test_suspend_resume();
+		igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+					      SUSPEND_TEST_NONE);
+		break;
+
+	case HIBERNATE_RESUME:
+		igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
+					      SUSPEND_TEST_NONE);
 		break;
 
 	case SIMPLE_READ:
@@ -224,6 +225,7 @@ igt_main
 		{ "basic-read", SIMPLE_READ },
 		{ "reset", GPU_RESET },
 		{ "suspend-resume", SUSPEND_RESUME },
+		{ "hibernate-resume", HIBERNATE_RESUME },
 		{ }
 	}, *op;
 	const struct {
-- 
2.14.2

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[PATCH igt 7/7] lib: Ask the kernel to quiescent the GPU

[Chris Wilson]

Since the introduction of debugfs/i915_drop_caches, we have offered the
ability to wait upon all outstanding batches. This is more efficient and
less error prone (one example is the use of context priorities, we have
to idle at the lowest in order not to jump over any low priority tasks
we want to wait upon) than trying to do it all in userspace. Though we
could if we wanted to, it's just easier to use the existing facility
designed for the purpose -- that we were already partially using!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/drmtest.c | 28 +---------------------------
 1 file changed, 1 insertion(+), 27 deletions(-)

diff --git a/lib/drmtest.c b/lib/drmtest.c
index 8a07152c..4ae023d7 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -159,35 +159,9 @@ static bool has_known_intel_chipset(int fd)
  */
 void gem_quiescent_gpu(int fd)
 {
-	uint32_t bbe = MI_BATCH_BUFFER_END;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 obj;
-	unsigned ring;
-
 	igt_terminate_spin_batches();
 
-	memset(&obj, 0, sizeof(obj));
-	obj.handle = gem_create(fd, 4096);
-	gem_write(fd, obj.handle, 0, &bbe, sizeof(&bbe));
-
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(&obj);
-	execbuf.buffer_count = 1;
-
-	for (ring = 0; ring < 1<<6; ring++) {
-		execbuf.flags = ring;
-		__gem_execbuf(fd, &execbuf);
-	}
-
-	if (gem_has_bsd2(fd)) {
-		execbuf.flags = I915_EXEC_BSD | (2 << 13);
-		__gem_execbuf(fd, &execbuf);
-	}
-
-	gem_sync(fd, obj.handle);
-	gem_close(fd, obj.handle);
-
-	igt_drop_caches_set(fd, DROP_RETIRE | DROP_FREED);
+	igt_drop_caches_set(fd, DROP_ACTIVE | DROP_RETIRE | DROP_FREED);
 }
 
 /**
-- 
2.14.2

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✗ Fi.CI.BAT: failure for series starting with [1/7] igt/gem_sync: Sync before starting the clock

[Patchwork]

== Series Details ==

Series: series starting with [1/7] igt/gem_sync: Sync before starting the clock
URL   : https://patchwork.freedesktop.org/series/31189/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
09f8cb1a3758fa9868a07b83a3d3db2973d795cc igt/gem_sync: Sync before starting the clock

with latest DRM-Tip kernel build CI_DRM_3157
e650b9cdaff6 drm-tip: 2017y-09m-29d-11h-52m-41s UTC integration manifest

Testlist changes:
+igt@gem_workarounds@basic-read-context
+igt@gem_workarounds@basic-read-fd
+igt@gem_workarounds@hibernate-resume
+igt@gem_workarounds@hibernate-resume-context
+igt@gem_workarounds@hibernate-resume-fd
+igt@gem_workarounds@reset-context
+igt@gem_workarounds@reset-fd
+igt@gem_workarounds@suspend-resume-context
+igt@gem_workarounds@suspend-resume-fd

Test chamelium:
        Subgroup hdmi-crc-fast:
                dmesg-warn -> PASS       (fi-skl-6700k) fdo#103019
Test gem_sync:
        Subgroup basic-all:
                pass       -> DMESG-FAIL (fi-blb-e6850)
                pass       -> DMESG-FAIL (fi-pnv-d510)
Test gem_workarounds:
        Subgroup basic-read:
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                pass       -> SKIP       (fi-elk-e7500)
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
                pass       -> SKIP       (fi-ivb-3520m)
                pass       -> SKIP       (fi-ivb-3770)
                pass       -> SKIP       (fi-byt-j1900)
                pass       -> SKIP       (fi-byt-n2820)
                pass       -> SKIP       (fi-hsw-4770)
                pass       -> SKIP       (fi-hsw-4770r)
Test kms_busy:
        Subgroup basic-flip-c:
                incomplete -> PASS       (fi-bxt-j4205) fdo#102035
Test drv_module_reload:
        Subgroup basic-reload:
                pass       -> DMESG-WARN (fi-glk-1) fdo#102777

fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
fdo#102035 https://bugs.freedesktop.org/show_bug.cgi?id=102035
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:444s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:471s
fi-blb-e6850     total:289  pass:222  dwarn:1   dfail:1   fail:0   skip:65  time:426s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:526s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:277s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:501s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:492s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:495s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:480s
fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:554s
fi-cnl-y         total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  time:647s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:421s
fi-glk-1         total:289  pass:258  dwarn:2   dfail:0   fail:0   skip:29  time:567s
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:423s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:404s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:429s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:490s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:462s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:475s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:577s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:584s
fi-pnv-d510      total:289  pass:221  dwarn:1   dfail:1   fail:0   skip:66  time:549s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:453s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:752s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:483s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:472s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:564s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:417s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_279/
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Re: ✗ Fi.CI.BAT: failure for series starting with [1/7] igt/gem_sync: Sync before starting the clock

[Arkadiusz Hiler]

On Fri, Sep 29, 2017 at 03:52:49PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/7] igt/gem_sync: Sync before starting the clock
> URL   : https://patchwork.freedesktop.org/series/31189/
> State : failure
> 
> == Summary ==
> 
> IGT patchset tested on top of latest successful build
> 09f8cb1a3758fa9868a07b83a3d3db2973d795cc igt/gem_sync: Sync before starting the clock
> 
> with latest DRM-Tip kernel build CI_DRM_3157
> e650b9cdaff6 drm-tip: 2017y-09m-29d-11h-52m-41s UTC integration manifest
> 
> Testlist changes:
> +igt@gem_workarounds@basic-read-context
> +igt@gem_workarounds@basic-read-fd
> +igt@gem_workarounds@hibernate-resume
> +igt@gem_workarounds@hibernate-resume-context
> +igt@gem_workarounds@hibernate-resume-fd
> +igt@gem_workarounds@reset-context
> +igt@gem_workarounds@reset-fd
> +igt@gem_workarounds@suspend-resume-context
> +igt@gem_workarounds@suspend-resume-fd

Shame those haven't got a spin due to gem_sync dmesg-fail.

> Test chamelium:
>         Subgroup hdmi-crc-fast:
>                 dmesg-warn -> PASS       (fi-skl-6700k) fdo#103019
> Test gem_sync:
>         Subgroup basic-all:
>                 pass       -> DMESG-FAIL (fi-blb-e6850)
>                 pass       -> DMESG-FAIL (fi-pnv-d510)

What's up with those, anyway?

-- 
Cheers,
Arek

> Test gem_workarounds:
>         Subgroup basic-read:
>                 pass       -> SKIP       (fi-blb-e6850)
>                 pass       -> SKIP       (fi-pnv-d510)
>                 pass       -> SKIP       (fi-bwr-2160)
>                 pass       -> SKIP       (fi-elk-e7500)
>                 pass       -> SKIP       (fi-ilk-650)
>                 pass       -> SKIP       (fi-snb-2520m)
>                 pass       -> SKIP       (fi-snb-2600)
>                 pass       -> SKIP       (fi-ivb-3520m)
>                 pass       -> SKIP       (fi-ivb-3770)
>                 pass       -> SKIP       (fi-byt-j1900)
>                 pass       -> SKIP       (fi-byt-n2820)
>                 pass       -> SKIP       (fi-hsw-4770)
>                 pass       -> SKIP       (fi-hsw-4770r)
> Test kms_busy:
>         Subgroup basic-flip-c:
>                 incomplete -> PASS       (fi-bxt-j4205) fdo#102035
> Test drv_module_reload:
>         Subgroup basic-reload:
>                 pass       -> DMESG-WARN (fi-glk-1) fdo#102777
> 
> fdo#103019 https://bugs.freedesktop.org/show_bug.cgi?id=103019
> fdo#102035 https://bugs.freedesktop.org/show_bug.cgi?id=102035
> fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
> 
> fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:444s
> fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:471s
> fi-blb-e6850     total:289  pass:222  dwarn:1   dfail:1   fail:0   skip:65  time:426s
> fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:526s
> fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:277s
> fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:501s
> fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:492s
> fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:495s
> fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:480s
> fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:554s
> fi-cnl-y         total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  time:647s
> fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:421s
> fi-glk-1         total:289  pass:258  dwarn:2   dfail:0   fail:0   skip:29  time:567s
> fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:423s
> fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:404s
> fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:429s
> fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:490s
> fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:462s
> fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:475s
> fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:577s
> fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:584s
> fi-pnv-d510      total:289  pass:221  dwarn:1   dfail:1   fail:0   skip:66  time:549s
> fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:453s
> fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:752s
> fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:483s
> fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:472s
> fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:564s
> fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:417s
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_279/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: ✗ Fi.CI.BAT: failure for series starting with [1/7] igt/gem_sync: Sync before starting the clock

[Chris Wilson]

Quoting Arkadiusz Hiler (2017-10-03 12:55:48)
> On Fri, Sep 29, 2017 at 03:52:49PM +0000, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: series starting with [1/7] igt/gem_sync: Sync before starting the clock
> > URL   : https://patchwork.freedesktop.org/series/31189/
> > State : failure
> > 
> > == Summary ==
> > 
> > IGT patchset tested on top of latest successful build
> > 09f8cb1a3758fa9868a07b83a3d3db2973d795cc igt/gem_sync: Sync before starting the clock
> > 
> > with latest DRM-Tip kernel build CI_DRM_3157
> > e650b9cdaff6 drm-tip: 2017y-09m-29d-11h-52m-41s UTC integration manifest
> > 
> > Testlist changes:
> > +igt@gem_workarounds@basic-read-context
> > +igt@gem_workarounds@basic-read-fd
> > +igt@gem_workarounds@hibernate-resume
> > +igt@gem_workarounds@hibernate-resume-context
> > +igt@gem_workarounds@hibernate-resume-fd
> > +igt@gem_workarounds@reset-context
> > +igt@gem_workarounds@reset-fd
> > +igt@gem_workarounds@suspend-resume-context
> > +igt@gem_workarounds@suspend-resume-fd
> 
> Shame those haven't got a spin due to gem_sync dmesg-fail.
> 
> > Test chamelium:
> >         Subgroup hdmi-crc-fast:
> >                 dmesg-warn -> PASS       (fi-skl-6700k) fdo#103019
> > Test gem_sync:
> >         Subgroup basic-all:
> >                 pass       -> DMESG-FAIL (fi-blb-e6850)
> >                 pass       -> DMESG-FAIL (fi-pnv-d510)
> 
> What's up with those, anyway?

Just your irregular GPU stops responding. The stop rings request prior
to the GPU reset also failed, so likely the CS parser was stuck or it
was exploring an infinite batch or an empty address space.

That it affected gem_sync makes me wonder what happened with the
duplicate patch I accidentally included. It didn't trigger on my pnv, so
just the usual irrational GPU that we wait and see what patterns
evolve.
-Chris
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Re: [PATCH igt 7/7] lib: Ask the kernel to quiescent the GPU

[Joonas Lahtinen]

On Fri, 2017-09-29 at 16:26 +0100, Chris Wilson wrote:
> Since the introduction of debugfs/i915_drop_caches, we have offered the
> ability to wait upon all outstanding batches. This is more efficient and
> less error prone (one example is the use of context priorities, we have
> to idle at the lowest in order not to jump over any low priority tasks
> we want to wait upon) than trying to do it all in userspace. Though we
> could if we wanted to, it's just easier to use the existing facility
> designed for the purpose -- that we were already partially using!
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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Re: [PATCH igt 2/7] igt/gem_workarounds: Read the workaround registers from the active context

[Chris Wilson]

Quoting Chris Wilson (2017-09-29 16:26:37)
> +       out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
> +       for (int i = 0; i < num_wa_regs; i++) {
> +               const bool ok =
> +                       (wa_regs[i].value & wa_regs[i].mask) ==
> +                       (out[i] & wa_regs[i].mask);
> +               char buf[80];
>  
> -               igt_debug("0x%05X    0x%08X    0x%08X    0x%08X    %s\n",
> -                         wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
> -                         val, ok ? "OK" : "FAIL");
> +               snprintf(buf, sizeof(buf),
> +                        "0x%05X    0x%08X    0x%08X    0x%08X",
> +                        wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
> +                        out[i]);
>  
>                 if (write_only(wa_regs[i].addr))
>                         continue;

For fun I think we shouldn't skip the igt_debug here.
-Chris
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[PATCH igt v2] igt/gem_workarounds: Read the workaround registers from the active context

[Chris Wilson]

The workarounds are only valid whilst the GPU is active. To be sure we
are reading the registers in the right state, issue the reads from the GPU.

v2: Show ignored write-only failures as debug.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_workarounds.c | 147 ++++++++++++++++++++++++++----------------------
 1 file changed, 81 insertions(+), 66 deletions(-)

diff --git a/tests/gem_workarounds.c b/tests/gem_workarounds.c
index 5e30a7b8..95ec250a 100644
--- a/tests/gem_workarounds.c
+++ b/tests/gem_workarounds.c
@@ -61,20 +61,6 @@ static struct write_only_list {
 static struct intel_wa_reg *wa_regs;
 static int num_wa_regs;
 
-static void wait_gpu(void)
-{
-	int fd = drm_open_driver(DRIVER_INTEL);
-	gem_quiescent_gpu(fd);
-	close(fd);
-}
-
-static void test_hang_gpu(void)
-{
-	int fd = drm_open_driver(DRIVER_INTEL);
-	igt_post_hang_ring(fd, igt_hang_ring(fd, I915_EXEC_DEFAULT));
-	close(fd);
-}
-
 static void test_suspend_resume(void)
 {
 	igt_info("Suspending the device ...\n");
@@ -96,49 +82,95 @@ static bool write_only(const uint32_t addr)
 	return false;
 }
 
-static int workaround_fail_count(void)
-{
-	int i, fail_count = 0;
-
-	/* There is a small delay after coming ot of rc6 to the correct
-	   render context values will get loaded by hardware (bdw,chv).
-	   This here ensures that we have the correct context loaded before
-	   we start to read values */
-	wait_gpu();
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
 
-	igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
+static int workaround_fail_count(int fd)
+{
+	struct drm_i915_gem_exec_object2 obj[2];
+	struct drm_i915_gem_relocation_entry *reloc;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t result_sz, batch_sz;
+	uint32_t *base, *out;
+	int fail_count = 0;
+
+	reloc = calloc(num_wa_regs, sizeof(*reloc));
+	igt_assert(reloc);
+
+	result_sz = 4 * num_wa_regs;
+	result_sz = (result_sz + 4095) & -4096;
+
+	batch_sz = 16 * num_wa_regs;
+	batch_sz = (batch_sz + 4 + 4095) & -4096;
+
+	memset(obj, 0, sizeof(obj));
+	obj[0].handle = gem_create(fd, result_sz);
+	gem_set_caching(fd, obj[0].handle, 1);
+	obj[1].handle = gem_create(fd, batch_sz);
+	obj[1].relocs_ptr = to_user_pointer(reloc);
+	obj[1].relocation_count = num_wa_regs;
+
+	out = base = gem_mmap__cpu(fd, obj[1].handle, 0, batch_sz, PROT_WRITE);
+	for (int i = 0; i < num_wa_regs; i++) {
+		*out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
+		*out++ = wa_regs[i].addr;
+		reloc[i].target_handle = obj[0].handle;
+		reloc[i].offset = (out - base) * sizeof(*out);
+		reloc[i].delta = i * sizeof(uint32_t);
+		reloc[i].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
+		reloc[i].write_domain = I915_GEM_DOMAIN_INSTRUCTION;
+		*out++ = reloc[i].delta;
+		if (gen >= 8)
+			*out++ = 0;
+	}
+	*out++ = MI_BATCH_BUFFER_END;
+	munmap(base, batch_sz);
 
-	for (i = 0; i < num_wa_regs; ++i) {
-		const uint32_t val = intel_register_read(wa_regs[i].addr);
-		const bool ok = (wa_regs[i].value & wa_regs[i].mask) ==
-			(val & wa_regs[i].mask);
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(obj);
+	execbuf.buffer_count = 2;
+	gem_execbuf(fd, &execbuf);
 
-		igt_debug("0x%05X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
-			  wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
-			  val, ok ? "OK" : "FAIL");
+	gem_set_domain(fd, obj[0].handle, I915_GEM_DOMAIN_CPU, 0);
 
-		if (write_only(wa_regs[i].addr))
-			continue;
+	igt_debug("Address\tval\t\tmask\t\tread\t\tresult\n");
 
-		if (!ok) {
-			igt_warn("0x%05X\t0x%08X\t0x%08X\t0x%08X\t%s\n",
-				 wa_regs[i].addr, wa_regs[i].value,
-				 wa_regs[i].mask,
-				 val, ok ? "OK" : "FAIL");
+	out = gem_mmap__cpu(fd, obj[0].handle, 0, result_sz, PROT_READ);
+	for (int i = 0; i < num_wa_regs; i++) {
+		const bool ok =
+			(wa_regs[i].value & wa_regs[i].mask) ==
+			(out[i] & wa_regs[i].mask);
+		char buf[80];
+
+		snprintf(buf, sizeof(buf),
+			 "0x%05X\t0x%08X\t0x%08X\t0x%08X",
+			 wa_regs[i].addr, wa_regs[i].value, wa_regs[i].mask,
+			 out[i]);
+
+		if (ok) {
+			igt_debug("%s\tOK\n", buf);
+		} else if (write_only(wa_regs[i].addr)) {
+			igt_debug("%s\tIGNORED (w/o)\n", buf);
+		} else {
+			igt_warn("%s\tFAIL\n", buf);
 			fail_count++;
 		}
 	}
+	munmap(out, result_sz);
+
+	gem_close(fd, obj[1].handle);
+	gem_close(fd, obj[0].handle);
+	free(reloc);
 
 	return fail_count;
 }
 
-static void check_workarounds(enum operation op)
+static void check_workarounds(int fd, enum operation op)
 {
-	igt_assert_eq(workaround_fail_count(), 0);
+	igt_assert_eq(workaround_fail_count(fd), 0);
 
 	switch (op) {
 	case GPU_RESET:
-		test_hang_gpu();
+		igt_force_gpu_reset(fd);
 		break;
 
 	case SUSPEND_RESUME:
@@ -152,40 +184,30 @@ static void check_workarounds(enum operation op)
 		igt_assert(0);
 	}
 
-	igt_assert_eq(workaround_fail_count(), 0);
+	igt_assert_eq(workaround_fail_count(fd), 0);
 }
 
 igt_main
 {
+	int device = -1;
+
 	igt_fixture {
-		int device = drm_open_driver_master(DRIVER_INTEL);
-		struct pci_device *pci_dev;
 		FILE *file;
 		char *line = NULL;
 		size_t line_size;
 		int i, fd;
 
+		device = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(device);
 
 		gen = intel_gen(intel_get_drm_devid(device));
 
-		pci_dev = intel_get_pci_device();
-		igt_require(pci_dev);
-
-		intel_register_access_init(pci_dev, 0, device);
-
 		fd = igt_debugfs_open(device, "i915_wa_registers", O_RDONLY);
 		file = fdopen(fd, "r");
 		igt_assert(getline(&line, &line_size, file) > 0);
 		igt_debug("i915_wa_registers: %s", line);
 		sscanf(line, "Workarounds applied: %d", &num_wa_regs);
-
-		/* For newer gens, the lri wa list has always something.
-		 * If it doesn't, go and add one. */
-		if (gen >= 8)
-			igt_assert_lt(0, num_wa_regs);
-		else
-			igt_assert_lte(0, num_wa_regs);
+		igt_require(num_wa_regs > 0);
 
 		wa_regs = malloc(num_wa_regs * sizeof(*wa_regs));
 		igt_assert(wa_regs);
@@ -205,21 +227,14 @@ igt_main
 		free(line);
 		fclose(file);
 		close(fd);
-		close(device);
 	}
 
 	igt_subtest("basic-read")
-		check_workarounds(SIMPLE_READ);
+		check_workarounds(device, SIMPLE_READ);
 
 	igt_subtest("reset")
-		check_workarounds(GPU_RESET);
+		check_workarounds(device, GPU_RESET);
 
 	igt_subtest("suspend-resume")
-		check_workarounds(SUSPEND_RESUME);
-
-	igt_fixture {
-		free(wa_regs);
-		intel_register_access_fini();
-	}
-
+		check_workarounds(device, SUSPEND_RESUME);
 }
-- 
2.14.2

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✗ Fi.CI.BAT: failure for series starting with [1/7] igt/gem_sync: Sync before starting the clock (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/7] igt/gem_sync: Sync before starting the clock (rev2)
URL   : https://patchwork.freedesktop.org/series/31189/
State : failure

== Summary ==

IGT patchset tested on top of latest successful build
08a2f887b26c89cfb1e1b5715a23d561b75e0dab lib: Reduce dependency on glib

with latest DRM-Tip kernel build CI_DRM_3166
79f82050a245 drm-tip: 2017y-10m-03d-11h-31m-30s UTC integration manifest

Testlist changes:
+igt@gem_workarounds@basic-read-context
+igt@gem_workarounds@basic-read-fd
+igt@gem_workarounds@hibernate-resume
+igt@gem_workarounds@hibernate-resume-context
+igt@gem_workarounds@hibernate-resume-fd
+igt@gem_workarounds@reset-context
+igt@gem_workarounds@reset-fd
+igt@gem_workarounds@suspend-resume-context
+igt@gem_workarounds@suspend-resume-fd

Test gem_sync:
        Subgroup basic-all:
                pass       -> DMESG-FAIL (fi-blb-e6850)
                pass       -> FAIL       (fi-pnv-d510)
Test gem_workarounds:
        Subgroup basic-read:
                pass       -> SKIP       (fi-blb-e6850)
                pass       -> SKIP       (fi-pnv-d510)
                pass       -> SKIP       (fi-bwr-2160)
                pass       -> SKIP       (fi-elk-e7500)
                pass       -> SKIP       (fi-ilk-650)
                pass       -> SKIP       (fi-snb-2520m)
                pass       -> SKIP       (fi-snb-2600)
                pass       -> SKIP       (fi-ivb-3520m)
                pass       -> SKIP       (fi-ivb-3770)
                pass       -> SKIP       (fi-byt-j1900)
                pass       -> SKIP       (fi-byt-n2820)
                pass       -> SKIP       (fi-hsw-4770)
                pass       -> SKIP       (fi-hsw-4770r)

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:452s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:467s
fi-blb-e6850     total:289  pass:222  dwarn:1   dfail:1   fail:0   skip:65  time:403s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:555s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:287s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:527s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:528s
fi-byt-j1900     total:289  pass:253  dwarn:1   dfail:0   fail:0   skip:35  time:540s
fi-byt-n2820     total:289  pass:249  dwarn:1   dfail:0   fail:0   skip:39  time:535s
fi-cfl-s         total:289  pass:256  dwarn:1   dfail:0   fail:0   skip:32  time:557s
fi-cnl-y         total:289  pass:261  dwarn:1   dfail:0   fail:0   skip:27  time:624s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:435s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:589s
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:442s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:423s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:461s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:507s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:472s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:501s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:574s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:587s
fi-pnv-d510      total:289  pass:221  dwarn:1   dfail:0   fail:1   skip:66  time:661s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:480s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:528s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:570s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:475s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:581s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:437s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_288/
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Re: ✗ Fi.CI.BAT: failure for series starting with [1/7] igt/gem_sync: Sync before starting the clock (rev2)

[Chris Wilson]

Quoting Patchwork (2017-10-03 14:34:13)
> == Series Details ==
> 
> Series: series starting with [1/7] igt/gem_sync: Sync before starting the clock (rev2)
> URL   : https://patchwork.freedesktop.org/series/31189/
> State : failure
> 
> == Summary ==
> 
> IGT patchset tested on top of latest successful build
> 08a2f887b26c89cfb1e1b5715a23d561b75e0dab lib: Reduce dependency on glib
> 
> with latest DRM-Tip kernel build CI_DRM_3166
> 79f82050a245 drm-tip: 2017y-10m-03d-11h-31m-30s UTC integration manifest
> 
> Testlist changes:
> +igt@gem_workarounds@basic-read-context
> +igt@gem_workarounds@basic-read-fd
> +igt@gem_workarounds@hibernate-resume
> +igt@gem_workarounds@hibernate-resume-context
> +igt@gem_workarounds@hibernate-resume-fd
> +igt@gem_workarounds@reset-context
> +igt@gem_workarounds@reset-fd
> +igt@gem_workarounds@suspend-resume-context
> +igt@gem_workarounds@suspend-resume-fd
> 
> Test gem_sync:
>         Subgroup basic-all:
>                 pass       -> DMESG-FAIL (fi-blb-e6850)
>                 pass       -> FAIL       (fi-pnv-d510)

It really doesn't like it. Let's try afresh...
-Chris
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