From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751103AbdJCG4J (ORCPT ); Tue, 3 Oct 2017 02:56:09 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:33201 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750720AbdJCG4I (ORCPT ); Tue, 3 Oct 2017 02:56:08 -0400 X-Google-Smtp-Source: AOwi7QCy+SHy2rz6lTOWprxooRHCI7dW8hTSCTW3vQx9YLJ65gkaAofbG1rkffmh7dsFvHpmiMLNQw== From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v4 0/5] clk: Add Aspeed clock driver Date: Tue, 3 Oct 2017 17:25:35 +1030 Message-Id: <20171003065540.11722-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is v4. See patches for detailed changelogs. v4: Address review from Andrew and Stephen. v3: Address review from Andrew and has seen more testing on hardware v2: split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infrastructure, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 698 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ 4 files changed, 763 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: joel@jms.id.au (Joel Stanley) Date: Tue, 3 Oct 2017 17:25:35 +1030 Subject: [PATCH v4 0/5] clk: Add Aspeed clock driver Message-ID: <20171003065540.11722-1-joel@jms.id.au> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This driver supports the ast2500, ast2400 (and derivative) BMC SoCs from Aspeed. This is v4. See patches for detailed changelogs. v4: Address review from Andrew and Stephen. v3: Address review from Andrew and has seen more testing on hardware v2: split the driver out into a series of patches to make them easier to review. All of the important clocks are supported, with most non-essential ones also implemented where information is available. I am working with Aspeed to clear up some of the missing information, including the missing parent-sibling relationships. We need to know the rate of the apb clock in order to correctly program the clocksource driver, so the apb and it's parents are created in the CLK_OF_DECLARE_DRIVER callback. The rest of the clocks are created at normal driver probe time. I followed the Gemini driver's lead with using the regmap where I could, but also having a pointer to the base address for use with the common clock callbacks. The driver borrows from the clk_gate common clock infrastructure, but modifies it in order to support the clock gate and reset pair that most of the clocks have. This pair must be reset-ungated-released, with appropriate delays, according to the datasheet. The first patch introduces the core clock registration parts, and describes the clocks. The second creates the core clocks, giving the system enough to boot (but without uart). Next come the non-core clocks, and finally the reset controller that is used for the few cocks that don't have a gate to go with their reset pair. Please review! Cheers, Joel Joel Stanley (5): clk: Add clock driver for ASPEED BMC SoCs clk: aspeed: Register core clocks clk: aspeed: Add platform driver and register PLLs clk: aspeed: Register gated clocks clk: aspeed: Add reset controller drivers/clk/Kconfig | 12 + drivers/clk/Makefile | 1 + drivers/clk/clk-aspeed.c | 698 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/aspeed-clock.h | 52 +++ 4 files changed, 763 insertions(+) create mode 100644 drivers/clk/clk-aspeed.c create mode 100644 include/dt-bindings/clock/aspeed-clock.h -- 2.14.1