From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [CI 2/9] drm/i915/preempt: Default to disabled mid-command preemption levels
Date: Tue, 3 Oct 2017 21:34:46 +0100 [thread overview]
Message-ID: <20171003203453.15692-2-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20171003203453.15692-1-chris@chris-wilson.co.uk>
From: Michał Winiarski <michal.winiarski@intel.com>
Supporting fine-granularity preemption levels may require changes in
userspace batch buffer programming. Therefore, we need to fallback to
safe default values, rather that use hardware defaults. Userspace is
still able to enable fine-granularity, since we're whitelisting the
register controlling it in WaEnablePreemptionGranularityControlByUMD.
v2: Extend w/a to cover Cannonlake
v3: Fix commentary to include both fake w/a names.
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
drivers/gpu/drm/i915/intel_engine_cs.c | 25 +++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 39ad9327e2a0..e7dba5539b11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7003,6 +7003,12 @@ enum {
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
+#define GEN9_PREEMPT_3D_OBJECT_LEVEL (1<<0)
+#define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1))
+#define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0)
+#define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1)
+#define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0)
+#define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1)
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 040c85e496fa..5615f033c807 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1071,6 +1071,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_FLUSH_COHERENT_LINES));
+ /*
+ * Supporting preemption with fine-granularity requires changes in the
+ * batch buffer programming. Since we can't break old userspace, we
+ * need to set our default preemption level to safe value. Userspace is
+ * still able to use more fine-grained preemption levels, since in
+ * WaEnablePreemptionGranularityControlByUMD we're whitelisting the
+ * per-ctx register. As such, WaDisable{3D,GPGPU}MidCmdPreemption are
+ * not real HW workarounds, but merely a way to start using preemption
+ * while maintaining old contract with userspace.
+ */
+
+ /* WaDisable3DMidCmdPreemption:skl,bxt,glk,cfl,[cnl] */
+ WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
+
+ /* WaDisableGPGPUMidCmdPreemption:skl,bxt,blk,cfl,[cnl] */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
if (ret)
@@ -1272,6 +1290,13 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
/* FtrEnableFastAnisoL1BankingFix: cnl */
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
+ /* WaDisable3DMidCmdPreemption:cnl */
+ WA_CLR_BIT_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL);
+
+ /* WaDisableGPGPUMidCmdPreemption:cnl */
+ WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
+ GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
--
2.14.2
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next prev parent reply other threads:[~2017-10-03 20:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-03 20:34 [CI 1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD Chris Wilson
2017-10-03 20:34 ` Chris Wilson [this message]
2017-10-03 20:34 ` [CI 3/9] drm/i915/execlists: Distinguish the incomplete context notifies Chris Wilson
2017-10-03 20:34 ` [CI 4/9] drm/i915: Introduce a preempt context Chris Wilson
2017-10-03 20:34 ` [CI 5/9] drm/i915/execlists: Move bdw GPGPU w/a to emit_bb Chris Wilson
2017-10-03 20:34 ` [CI 6/9] drm/i915/execlists: Keep request->priority for its lifetime Chris Wilson
2017-10-03 20:34 ` [CI 7/9] drm/i915: Expand I915_PARAM_HAS_SCHEDULER into a capability bitmask Chris Wilson
2017-10-03 20:34 ` [CI 8/9] drm/i915/execlists: Preemption! Chris Wilson
2017-10-03 20:34 ` [CI 9/9] drm/i915/scheduler: Support user-defined priorities Chris Wilson
2017-10-03 21:14 ` ✗ Fi.CI.BAT: warning for series starting with [CI,1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD Patchwork
2017-10-04 14:33 [CI 1/9] " Chris Wilson
2017-10-04 14:33 ` [CI 2/9] drm/i915/preempt: Default to disabled mid-command preemption levels Chris Wilson
2017-10-04 15:52 [CI 1/9] drm/i915/preempt: Fix WaEnablePreemptionGranularityControlByUMD Chris Wilson
2017-10-04 15:52 ` [CI 2/9] drm/i915/preempt: Default to disabled mid-command preemption levels Chris Wilson
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