From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miquel Raynal Subject: [PATCH 09/16] serial: mvebu-uart: add TX interrupt trigger for pulse interrupts Date: Fri, 6 Oct 2017 12:13:37 +0200 Message-ID: <20171006101344.15590-10-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Return-path: Received: from mail.free-electrons.com ([62.4.15.54]:50807 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751931AbdJFKOO (ORCPT ); Fri, 6 Oct 2017 06:14:14 -0400 In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org List-Id: linux-gpio@vger.kernel.org To: Greg Kroah-Hartman , Linus Walleij , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Jiri Slaby , Catalin Marinas , Will Deacon Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Thomas Petazzoni , Antoine Tenart , Nadav Haklai , Wilson Ding , Allen Yan , Miquel Raynal From: Allen Yan Pulse interrupts (extended UART only) needs a change of state to trigger the TX interrupt. In addition to enabling the TX_READY_INT_EN flag, produce a FIFO state change from 'empty' to 'not full'. For this, write only one data byte in TX start, making the TX FIFO not empty, and wait for the TX interrupt to continue the transfer. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal --- drivers/tty/serial/mvebu-uart.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 67f302748b78..46d10209637a 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -165,8 +165,16 @@ static void mvebu_uart_stop_tx(struct uart_port *port) static void mvebu_uart_start_tx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_INTR(port)); + unsigned int ctl; + struct circ_buf *xmit = &port->state->xmit; + if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { + writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + ctl = readl(port->membase + UART_INTR(port)); ctl |= CTRL_TX_RDY_INT(port); writel(ctl, port->membase + UART_INTR(port)); } -- 2.11.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: miquel.raynal@free-electrons.com (Miquel Raynal) Date: Fri, 6 Oct 2017 12:13:37 +0200 Subject: [PATCH 09/16] serial: mvebu-uart: add TX interrupt trigger for pulse interrupts In-Reply-To: <20171006101344.15590-1-miquel.raynal@free-electrons.com> References: <20171006101344.15590-1-miquel.raynal@free-electrons.com> Message-ID: <20171006101344.15590-10-miquel.raynal@free-electrons.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Allen Yan Pulse interrupts (extended UART only) needs a change of state to trigger the TX interrupt. In addition to enabling the TX_READY_INT_EN flag, produce a FIFO state change from 'empty' to 'not full'. For this, write only one data byte in TX start, making the TX FIFO not empty, and wait for the TX interrupt to continue the transfer. Signed-off-by: Allen Yan Signed-off-by: Miquel Raynal --- drivers/tty/serial/mvebu-uart.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c index 67f302748b78..46d10209637a 100644 --- a/drivers/tty/serial/mvebu-uart.c +++ b/drivers/tty/serial/mvebu-uart.c @@ -165,8 +165,16 @@ static void mvebu_uart_stop_tx(struct uart_port *port) static void mvebu_uart_start_tx(struct uart_port *port) { - unsigned int ctl = readl(port->membase + UART_INTR(port)); + unsigned int ctl; + struct circ_buf *xmit = &port->state->xmit; + if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { + writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + + ctl = readl(port->membase + UART_INTR(port)); ctl |= CTRL_TX_RDY_INT(port); writel(ctl, port->membase + UART_INTR(port)); } -- 2.11.0