From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752290AbdJFNSJ (ORCPT ); Fri, 6 Oct 2017 09:18:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47490 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751981AbdJFNRn (ORCPT ); Fri, 6 Oct 2017 09:17:43 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 82C663D97B Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=rkrcmar@redhat.com Date: Fri, 6 Oct 2017 15:17:40 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Wanpeng Li Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Paolo Bonzini , Wanpeng Li Subject: Re: [PATCH v6 2/3] KVM: LAPIC: Keep timer running when switching between one-shot and periodic mode Message-ID: <20171006131739.GC16466@flask> References: <1507254866-5020-1-git-send-email-wanpeng.li@hotmail.com> <1507254866-5020-3-git-send-email-wanpeng.li@hotmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1507254866-5020-3-git-send-email-wanpeng.li@hotmail.com> X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Fri, 06 Oct 2017 13:17:43 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-10-05 18:54-0700, Wanpeng Li: > From: Wanpeng Li > > If we take TSC-deadline mode timer out of the picture, the Intel SDM > does not say that the timer is disable when the timer mode is change, > either from one-shot to periodic or vice versa. > > After this patch, the timer is no longer disarmed on change of mode, so > the counter (TMCCT) keeps counting down. > > So what does a write to LVTT changes ? On baremetal, the change of mode > is probably taken into account only when the counter reach 0. When this > happen, LVTT is use to figure out if the counter should restard counting > down from TMICT (so periodic mode) or stop counting (if one-shot mode). > > This patch is based on observation of the behavior of the APIC timer on > baremetal as well as check that they does not go against the description > written in the Intel SDM. > > Cc: Paolo Bonzini > Cc: Radim Krčmář > Signed-off-by: Wanpeng Li > --- > arch/x86/kvm/lapic.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) Queued the first two patches, thanks. > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 8841bb5..14f63b3 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -1329,10 +1329,14 @@ static void apic_update_lvtt(struct kvm_lapic *apic) > > if (apic->lapic_timer.timer_mode != timer_mode) { > if (apic_lvtt_tscdeadline(apic) != (timer_mode == > - APIC_LVT_TIMER_TSCDEADLINE)) > + APIC_LVT_TIMER_TSCDEADLINE)) { > kvm_lapic_set_reg(apic, APIC_TMICT, 0); > + hrtimer_cancel(&apic->lapic_timer.timer); > + } > + if (apic_lvtt_oneshot(apic) && (timer_mode == > + APIC_LVT_TIMER_PERIODIC)) > + limit_periodic_timer_frequency(apic); > apic->lapic_timer.timer_mode = timer_mode; > - hrtimer_cancel(&apic->lapic_timer.timer); > } > } > > -- > 2.7.4 >