From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752101AbdJFOPB (ORCPT ); Fri, 6 Oct 2017 10:15:01 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38856 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751454AbdJFOPA (ORCPT ); Fri, 6 Oct 2017 10:15:00 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com C4D0BC057F93 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=rkrcmar@redhat.com Date: Fri, 6 Oct 2017 16:14:53 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= To: Wanpeng Li Cc: "linux-kernel@vger.kernel.org" , kvm , Paolo Bonzini , Wanpeng Li Subject: Re: [PATCH v6 3/3] KVM: LAPIC: Apply change to TDCR right away to the timer Message-ID: <20171006141453.GD16466@flask> References: <1507254866-5020-1-git-send-email-wanpeng.li@hotmail.com> <1507254866-5020-4-git-send-email-wanpeng.li@hotmail.com> <20171006131453.GB16466@flask> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 06 Oct 2017 14:14:59 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-10-06 21:59+0800, Wanpeng Li: > 2017-10-06 21:14 GMT+08:00 Radim Krčmář : > > 2017-10-05 18:54-0700, Wanpeng Li: > >> From: Wanpeng Li > >> > >> The description in the Intel SDM of how the divide configuration > >> register is used: "The APIC timer frequency will be the processor's bus > >> clock or core crystal clock frequency divided by the value specified in > >> the divide configuration register." > >> > >> Observation of baremetal shown that when the TDCR is change, the TMCCT > >> does not change or make a big jump in value, but the rate at which it > >> count down change. > >> > >> The patch update the emulation to APIC timer to so that a change to the > >> divide configuration would be reflected in the value of the counter and > >> when the next interrupt is triggered. > >> > >> Cc: Paolo Bonzini > >> Cc: Radim Krčmář > >> Signed-off-by: Wanpeng Li > >> --- > >> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > >> @@ -1458,6 +1458,36 @@ static void start_sw_period(struct kvm_lapic *apic) > >> +static bool update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) > >> +{ > >> + ktime_t now, remaining; > >> + u64 tscl = rdtsc(), delta; > >> + > >> + now = ktime_get(); > >> + remaining = ktime_sub(apic->lapic_timer.target_expiration, now); > >> + if (ktime_to_ns(remaining) < 0) > >> + remaining = 0; > >> + delta = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); > > > > Hm, can this happen? > > Yeah, when the hrtimer has already expired. I can catch it during testing. I thought that "if (ktime_to_ns(remaining) < 0)" is there to catch that, isn't that a bug elsewhere?